vpe_v6_1.c | Explore in Territory

/*
 * Copyright 2022 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#include <linux/firmware.h>
#include <drm/drm_drv.h>

#include "amdgpu.h"
#include "amdgpu_ucode.h"
#include "amdgpu_vpe.h"
#include "vpe_v6_1.h"
#include "soc15_common.h"
#include "ivsrcid/vpe/irqsrcs_vpe_6_1.h"
#include "vpe/vpe_6_1_0_offset.h"
#include "vpe/vpe_6_1_0_sh_mask.h"

MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;

#define VPE_THREAD1_UCODE_OFFSET …

#define regVPEC_COLLABORATE_CNTL …
#define regVPEC_COLLABORATE_CNTL_BASE_IDX …
#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN__SHIFT …
#define VPEC_COLLABORATE_CNTL__COLLABORATE_MODE_EN_MASK …

#define regVPEC_COLLABORATE_CFG …
#define regVPEC_COLLABORATE_CFG_BASE_IDX …
#define VPEC_COLLABORATE_CFG__MASTER_ID__SHIFT …
#define VPEC_COLLABORATE_CFG__MASTER_EN__SHIFT …
#define VPEC_COLLABORATE_CFG__SLAVE0_ID__SHIFT …
#define VPEC_COLLABORATE_CFG__SLAVE0_EN__SHIFT …
#define VPEC_COLLABORATE_CFG__MASTER_ID_MASK …
#define VPEC_COLLABORATE_CFG__MASTER_EN_MASK …
#define VPEC_COLLABORATE_CFG__SLAVE0_ID_MASK …
#define VPEC_COLLABORATE_CFG__SLAVE0_EN_MASK …

#define regVPEC_CNTL_6_1_1 …
#define regVPEC_CNTL_6_1_1_BASE_IDX …
#define regVPEC_QUEUE_RESET_REQ_6_1_1 …
#define regVPEC_QUEUE_RESET_REQ_6_1_1_BASE_IDX …
#define regVPEC_PUB_DUMMY2_6_1_1 …
#define regVPEC_PUB_DUMMY2_6_1_1_BASE_IDX …

static uint32_t vpe_v6_1_get_reg_offset(struct amdgpu_vpe *vpe, uint32_t inst, uint32_t offset)
{ … }

static void vpe_v6_1_halt(struct amdgpu_vpe *vpe, bool halt)
{ … }

static int vpe_v6_1_irq_init(struct amdgpu_vpe *vpe)
{ … }

static void vpe_v6_1_set_collaborate_mode(struct amdgpu_vpe *vpe, bool enable)
{ … }

static int vpe_v6_1_load_microcode(struct amdgpu_vpe *vpe)
{ … }

static int vpe_v6_1_ring_start(struct amdgpu_vpe *vpe)
{ … }

static int vpe_v_6_1_ring_stop(struct amdgpu_vpe *vpe)
{ … }

static int vpe_v6_1_set_trap_irq_state(struct amdgpu_device *adev,
				       struct amdgpu_irq_src *source,
				       unsigned int type,
				       enum amdgpu_interrupt_state state)
{ … }

static int vpe_v6_1_process_trap_irq(struct amdgpu_device *adev,
				     struct amdgpu_irq_src *source,
				     struct amdgpu_iv_entry *entry)
{ … }

static int vpe_v6_1_set_regs(struct amdgpu_vpe *vpe)
{ … }

static const struct vpe_funcs vpe_v6_1_funcs = …;

static const struct amdgpu_irq_src_funcs vpe_v6_1_trap_irq_funcs = …;

void vpe_v6_1_set_funcs(struct amdgpu_vpe *vpe)
{ … }
linux/drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c
