/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #if !defined (_soc21_ENUM_HEADER) #define _soc21_ENUM_HEADER #ifndef _DRIVER_BUILD #ifndef GL_ZERO #define GL__ZERO … #define GL__ONE … #define GL__SRC_COLOR … #define GL__ONE_MINUS_SRC_COLOR … #define GL__DST_COLOR … #define GL__ONE_MINUS_DST_COLOR … #define GL__SRC_ALPHA … #define GL__ONE_MINUS_SRC_ALPHA … #define GL__DST_ALPHA … #define GL__ONE_MINUS_DST_ALPHA … #define GL__SRC_ALPHA_SATURATE … #define GL__CONSTANT_COLOR … #define GL__ONE_MINUS_CONSTANT_COLOR … #define GL__CONSTANT_ALPHA … #define GL__ONE_MINUS_CONSTANT_ALPHA … #endif #endif /******************************************************* * Chip Enums *******************************************************/ /* * DSM_DATA_SEL enum */ DSM_DATA_SEL; /* * DSM_ENABLE_ERROR_INJECT enum */ DSM_ENABLE_ERROR_INJECT; /* * DSM_SELECT_INJECT_DELAY enum */ DSM_SELECT_INJECT_DELAY; /* * DSM_SINGLE_WRITE enum */ DSM_SINGLE_WRITE; /* * ENUM_NUM_SIMD_PER_CU enum */ ENUM_NUM_SIMD_PER_CU; /* * GATCL1RequestType enum */ GATCL1RequestType; /* * GL0V_CACHE_POLICIES enum */ GL0V_CACHE_POLICIES; /* * GL1_CACHE_POLICIES enum */ GL1_CACHE_POLICIES; /* * GL1_CACHE_STORE_POLICIES enum */ GL1_CACHE_STORE_POLICIES; /* * GL2_CACHE_POLICIES enum */ GL2_CACHE_POLICIES; /* * Hdp_SurfaceEndian enum */ Hdp_SurfaceEndian; /* * MTYPE enum */ MTYPE; /* * PERFMON_COUNTER_MODE enum */ PERFMON_COUNTER_MODE; /* * PERFMON_SPM_MODE enum */ PERFMON_SPM_MODE; /* * RMI_CID enum */ RMI_CID; /* * ReadPolicy enum */ ReadPolicy; /* * SDMA_PERFMON_SEL enum */ SDMA_PERFMON_SEL; /* * SDMA_PERF_SEL enum */ SDMA_PERF_SEL; /* * TCC_CACHE_POLICIES enum */ TCC_CACHE_POLICIES; /* * TCC_MTYPE enum */ TCC_MTYPE; /* * UTCL0FaultType enum */ UTCL0FaultType; /* * UTCL0RequestType enum */ UTCL0RequestType; /* * UTCL1FaultType enum */ UTCL1FaultType; /* * UTCL1RequestType enum */ UTCL1RequestType; /* * VMEMCMD_RETURN_ORDER enum */ VMEMCMD_RETURN_ORDER; /* * WritePolicy enum */ WritePolicy; /******************************************************* * CNVC_CFG Enums *******************************************************/ /* * CNVC_BYPASS enum */ CNVC_BYPASS; /* * CNVC_COEF_FORMAT_ENUM enum */ CNVC_COEF_FORMAT_ENUM; /* * CNVC_ENABLE enum */ CNVC_ENABLE; /* * CNVC_PENDING enum */ CNVC_PENDING; /* * COLOR_KEYER_MODE enum */ COLOR_KEYER_MODE; /* * DENORM_TRUNCATE enum */ DENORM_TRUNCATE; /* * FORMAT_CROSSBAR enum */ FORMAT_CROSSBAR; /* * PIX_EXPAND_MODE enum */ PIX_EXPAND_MODE; /* * PRE_CSC_MODE_ENUM enum */ PRE_CSC_MODE_ENUM; /* * PRE_DEGAM_MODE enum */ PRE_DEGAM_MODE; /* * PRE_DEGAM_SELECT enum */ PRE_DEGAM_SELECT; /* * SURFACE_PIXEL_FORMAT enum */ SURFACE_PIXEL_FORMAT; /* * XNORM enum */ XNORM; /******************************************************* * CNVC_CUR Enums *******************************************************/ /* * CUR_ENABLE enum */ CUR_ENABLE; /* * CUR_EXPAND_MODE enum */ CUR_EXPAND_MODE; /* * CUR_INV_CLAMP enum */ CUR_INV_CLAMP; /* * CUR_MODE enum */ CUR_MODE; /* * CUR_PENDING enum */ CUR_PENDING; /* * CUR_ROM_EN enum */ CUR_ROM_EN; /******************************************************* * DSCL Enums *******************************************************/ /* * COEF_RAM_SELECT_RD enum */ COEF_RAM_SELECT_RD; /* * DSCL_MODE_SEL enum */ DSCL_MODE_SEL; /* * LB_ALPHA_EN enum */ LB_ALPHA_EN; /* * LB_INTERLEAVE_EN enum */ LB_INTERLEAVE_EN; /* * LB_MEMORY_CONFIG enum */ LB_MEMORY_CONFIG; /* * OBUF_BYPASS_SEL enum */ OBUF_BYPASS_SEL; /* * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum */ OBUF_IS_HALF_RECOUT_WIDTH_SEL; /* * OBUF_USE_FULL_BUFFER_SEL enum */ OBUF_USE_FULL_BUFFER_SEL; /* * SCL_2TAP_HARDCODE enum */ SCL_2TAP_HARDCODE; /* * SCL_ALPHA_COEF enum */ SCL_ALPHA_COEF; /* * SCL_AUTOCAL_MODE enum */ SCL_AUTOCAL_MODE; /* * SCL_BOUNDARY enum */ SCL_BOUNDARY; /* * SCL_CHROMA_COEF enum */ SCL_CHROMA_COEF; /* * SCL_COEF_FILTER_TYPE_SEL enum */ SCL_COEF_FILTER_TYPE_SEL; /* * SCL_COEF_RAM_SEL enum */ SCL_COEF_RAM_SEL; /* * SCL_SHARP_EN enum */ SCL_SHARP_EN; /******************************************************* * CM Enums *******************************************************/ /* * CMC_3DLUT_30BIT_ENUM enum */ CMC_3DLUT_30BIT_ENUM; /* * CMC_3DLUT_RAM_SEL enum */ CMC_3DLUT_RAM_SEL; /* * CMC_3DLUT_SIZE_ENUM enum */ CMC_3DLUT_SIZE_ENUM; /* * CMC_LUT_2_CONFIG_ENUM enum */ CMC_LUT_2_CONFIG_ENUM; /* * CMC_LUT_2_MODE_ENUM enum */ CMC_LUT_2_MODE_ENUM; /* * CMC_LUT_NUM_SEG enum */ CMC_LUT_NUM_SEG; /* * CMC_LUT_RAM_SEL enum */ CMC_LUT_RAM_SEL; /* * CM_BYPASS enum */ CM_BYPASS; /* * CM_COEF_FORMAT_ENUM enum */ CM_COEF_FORMAT_ENUM; /* * CM_DATA_SIGNED enum */ CM_DATA_SIGNED; /* * CM_EN enum */ CM_EN; /* * CM_GAMMA_LUT_MODE_ENUM enum */ CM_GAMMA_LUT_MODE_ENUM; /* * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum */ CM_GAMMA_LUT_PWL_DISABLE_ENUM; /* * CM_GAMMA_LUT_SEL_ENUM enum */ CM_GAMMA_LUT_SEL_ENUM; /* * CM_GAMUT_REMAP_MODE_ENUM enum */ CM_GAMUT_REMAP_MODE_ENUM; /* * CM_LUT_2_CONFIG_ENUM enum */ CM_LUT_2_CONFIG_ENUM; /* * CM_LUT_2_MODE_ENUM enum */ CM_LUT_2_MODE_ENUM; /* * CM_LUT_4_CONFIG_ENUM enum */ CM_LUT_4_CONFIG_ENUM; /* * CM_LUT_4_MODE_ENUM enum */ CM_LUT_4_MODE_ENUM; /* * CM_LUT_CONFIG_MODE enum */ CM_LUT_CONFIG_MODE; /* * CM_LUT_NUM_SEG enum */ CM_LUT_NUM_SEG; /* * CM_LUT_RAM_SEL enum */ CM_LUT_RAM_SEL; /* * CM_LUT_READ_COLOR_SEL enum */ CM_LUT_READ_COLOR_SEL; /* * CM_LUT_READ_DBG enum */ CM_LUT_READ_DBG; /* * CM_PENDING enum */ CM_PENDING; /* * CM_POST_CSC_MODE_ENUM enum */ CM_POST_CSC_MODE_ENUM; /* * CM_WRITE_BASE_ONLY enum */ CM_WRITE_BASE_ONLY; /******************************************************* * DPP_TOP Enums *******************************************************/ /* * CRC_CUR_SEL enum */ CRC_CUR_SEL; /* * CRC_INTERLACE_SEL enum */ CRC_INTERLACE_SEL; /* * CRC_IN_CUR_SEL enum */ CRC_IN_CUR_SEL; /* * CRC_IN_PIX_SEL enum */ CRC_IN_PIX_SEL; /* * CRC_SRC_SEL enum */ CRC_SRC_SEL; /* * CRC_STEREO_SEL enum */ CRC_STEREO_SEL; /* * TEST_CLK_SEL enum */ TEST_CLK_SEL; /******************************************************* * DC_PERFMON Enums *******************************************************/ /* * PERFCOUNTER_ACTIVE enum */ PERFCOUNTER_ACTIVE; /* * PERFCOUNTER_CNT0_STATE enum */ PERFCOUNTER_CNT0_STATE; /* * PERFCOUNTER_CNT1_STATE enum */ PERFCOUNTER_CNT1_STATE; /* * PERFCOUNTER_CNT2_STATE enum */ PERFCOUNTER_CNT2_STATE; /* * PERFCOUNTER_CNT3_STATE enum */ PERFCOUNTER_CNT3_STATE; /* * PERFCOUNTER_CNT4_STATE enum */ PERFCOUNTER_CNT4_STATE; /* * PERFCOUNTER_CNT5_STATE enum */ PERFCOUNTER_CNT5_STATE; /* * PERFCOUNTER_CNT6_STATE enum */ PERFCOUNTER_CNT6_STATE; /* * PERFCOUNTER_CNT7_STATE enum */ PERFCOUNTER_CNT7_STATE; /* * PERFCOUNTER_CNTL_SEL enum */ PERFCOUNTER_CNTL_SEL; /* * PERFCOUNTER_CNTOFF_START_DIS enum */ PERFCOUNTER_CNTOFF_START_DIS; /* * PERFCOUNTER_COUNTED_VALUE_TYPE enum */ PERFCOUNTER_COUNTED_VALUE_TYPE; /* * PERFCOUNTER_CVALUE_SEL enum */ PERFCOUNTER_CVALUE_SEL; /* * PERFCOUNTER_HW_CNTL_SEL enum */ PERFCOUNTER_HW_CNTL_SEL; /* * PERFCOUNTER_HW_STOP1_SEL enum */ PERFCOUNTER_HW_STOP1_SEL; /* * PERFCOUNTER_HW_STOP2_SEL enum */ PERFCOUNTER_HW_STOP2_SEL; /* * PERFCOUNTER_INC_MODE enum */ PERFCOUNTER_INC_MODE; /* * PERFCOUNTER_INT_EN enum */ PERFCOUNTER_INT_EN; /* * PERFCOUNTER_INT_TYPE enum */ PERFCOUNTER_INT_TYPE; /* * PERFCOUNTER_OFF_MASK enum */ PERFCOUNTER_OFF_MASK; /* * PERFCOUNTER_RESTART_EN enum */ PERFCOUNTER_RESTART_EN; /* * PERFCOUNTER_RUNEN_MODE enum */ PERFCOUNTER_RUNEN_MODE; /* * PERFCOUNTER_STATE_SEL0 enum */ PERFCOUNTER_STATE_SEL0; /* * PERFCOUNTER_STATE_SEL1 enum */ PERFCOUNTER_STATE_SEL1; /* * PERFCOUNTER_STATE_SEL2 enum */ PERFCOUNTER_STATE_SEL2; /* * PERFCOUNTER_STATE_SEL3 enum */ PERFCOUNTER_STATE_SEL3; /* * PERFCOUNTER_STATE_SEL4 enum */ PERFCOUNTER_STATE_SEL4; /* * PERFCOUNTER_STATE_SEL5 enum */ PERFCOUNTER_STATE_SEL5; /* * PERFCOUNTER_STATE_SEL6 enum */ PERFCOUNTER_STATE_SEL6; /* * PERFCOUNTER_STATE_SEL7 enum */ PERFCOUNTER_STATE_SEL7; /* * PERFMON_CNTOFF_AND_OR enum */ PERFMON_CNTOFF_AND_OR; /* * PERFMON_CNTOFF_INT_EN enum */ PERFMON_CNTOFF_INT_EN; /* * PERFMON_CNTOFF_INT_TYPE enum */ PERFMON_CNTOFF_INT_TYPE; /* * PERFMON_STATE enum */ PERFMON_STATE; /******************************************************* * HUBP Enums *******************************************************/ /* * BIGK_FRAGMENT_SIZE enum */ BIGK_FRAGMENT_SIZE; /* * CHUNK_SIZE enum */ CHUNK_SIZE; /* * COMPAT_LEVEL enum */ COMPAT_LEVEL; /* * DPTE_GROUP_SIZE enum */ DPTE_GROUP_SIZE; /* * FORCE_ONE_ROW_FOR_FRAME enum */ FORCE_ONE_ROW_FOR_FRAME; /* * HUBP_BLANK_EN enum */ HUBP_BLANK_EN; /* * HUBP_IN_BLANK enum */ HUBP_IN_BLANK; /* * HUBP_MEASURE_WIN_MODE_DCFCLK enum */ HUBP_MEASURE_WIN_MODE_DCFCLK; /* * HUBP_NO_OUTSTANDING_REQ enum */ HUBP_NO_OUTSTANDING_REQ; /* * HUBP_SOFT_RESET enum */ HUBP_SOFT_RESET; /* * HUBP_TTU_DISABLE enum */ HUBP_TTU_DISABLE; /* * HUBP_VREADY_AT_OR_AFTER_VSYNC enum */ HUBP_VREADY_AT_OR_AFTER_VSYNC; /* * HUBP_VTG_SEL enum */ HUBP_VTG_SEL; /* * H_MIRROR_EN enum */ H_MIRROR_EN; /* * LEGACY_PIPE_INTERLEAVE enum */ LEGACY_PIPE_INTERLEAVE; /* * META_CHUNK_SIZE enum */ META_CHUNK_SIZE; /* * META_LINEAR enum */ META_LINEAR; /* * MIN_CHUNK_SIZE enum */ MIN_CHUNK_SIZE; /* * MIN_META_CHUNK_SIZE enum */ MIN_META_CHUNK_SIZE; /* * PIPE_ALIGNED enum */ PIPE_ALIGNED; /* * PTE_BUFFER_MODE enum */ PTE_BUFFER_MODE; /* * PTE_ROW_HEIGHT_LINEAR enum */ PTE_ROW_HEIGHT_LINEAR; /* * ROTATION_ANGLE enum */ ROTATION_ANGLE; /* * SWATH_HEIGHT enum */ SWATH_HEIGHT; /* * USE_MALL_FOR_CURSOR enum */ USE_MALL_FOR_CURSOR; /* * USE_MALL_FOR_PSTATE_CHANGE enum */ USE_MALL_FOR_PSTATE_CHANGE; /* * USE_MALL_FOR_STATIC_SCREEN enum */ USE_MALL_FOR_STATIC_SCREEN; /* * VMPG_SIZE enum */ VMPG_SIZE; /* * VM_GROUP_SIZE enum */ VM_GROUP_SIZE; /******************************************************* * HUBPREQ Enums *******************************************************/ /* * DFQ_MIN_FREE_ENTRIES enum */ DFQ_MIN_FREE_ENTRIES; /* * DFQ_NUM_ENTRIES enum */ DFQ_NUM_ENTRIES; /* * DFQ_SIZE enum */ DFQ_SIZE; /* * DMDATA_VM_DONE enum */ DMDATA_VM_DONE; /* * EXPANSION_MODE enum */ EXPANSION_MODE; /* * FLIP_RATE enum */ FLIP_RATE; /* * INT_MASK enum */ INT_MASK; /* * PIPE_IN_FLUSH_URGENT enum */ PIPE_IN_FLUSH_URGENT; /* * PRQ_MRQ_FLUSH_URGENT enum */ PRQ_MRQ_FLUSH_URGENT; /* * ROW_TTU_MODE enum */ ROW_TTU_MODE; /* * SURFACE_DCC enum */ SURFACE_DCC; /* * SURFACE_DCC_IND_128B enum */ SURFACE_DCC_IND_128B; /* * SURFACE_DCC_IND_64B enum */ SURFACE_DCC_IND_64B; /* * SURFACE_DCC_IND_BLK enum */ SURFACE_DCC_IND_BLK; /* * SURFACE_FLIP_AWAY_INT_TYPE enum */ SURFACE_FLIP_AWAY_INT_TYPE; /* * SURFACE_FLIP_EXEC_DEBUG_MODE enum */ SURFACE_FLIP_EXEC_DEBUG_MODE; /* * SURFACE_FLIP_INT_TYPE enum */ SURFACE_FLIP_INT_TYPE; /* * SURFACE_FLIP_IN_STEREOSYNC enum */ SURFACE_FLIP_IN_STEREOSYNC; /* * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum */ SURFACE_FLIP_MODE_FOR_STEREOSYNC; /* * SURFACE_FLIP_STEREO_SELECT_DISABLE enum */ SURFACE_FLIP_STEREO_SELECT_DISABLE; /* * SURFACE_FLIP_STEREO_SELECT_POLARITY enum */ SURFACE_FLIP_STEREO_SELECT_POLARITY; /* * SURFACE_FLIP_TYPE enum */ SURFACE_FLIP_TYPE; /* * SURFACE_FLIP_VUPDATE_SKIP_NUM enum */ SURFACE_FLIP_VUPDATE_SKIP_NUM; /* * SURFACE_INUSE_RAED_NO_LATCH enum */ SURFACE_INUSE_RAED_NO_LATCH; /* * SURFACE_TMZ enum */ SURFACE_TMZ; /* * SURFACE_UPDATE_LOCK enum */ SURFACE_UPDATE_LOCK; /******************************************************* * HUBPRET Enums *******************************************************/ /* * CROSSBAR_FOR_ALPHA enum */ CROSSBAR_FOR_ALPHA; /* * CROSSBAR_FOR_CB_B enum */ CROSSBAR_FOR_CB_B; /* * CROSSBAR_FOR_CR_R enum */ CROSSBAR_FOR_CR_R; /* * CROSSBAR_FOR_Y_G enum */ CROSSBAR_FOR_Y_G; /* * DETILE_BUFFER_PACKER_ENABLE enum */ DETILE_BUFFER_PACKER_ENABLE; /* * MEM_PWR_DIS_MODE enum */ MEM_PWR_DIS_MODE; /* * MEM_PWR_FORCE_MODE enum */ MEM_PWR_FORCE_MODE; /* * MEM_PWR_STATUS enum */ MEM_PWR_STATUS; /* * PIPE_INT_MASK_MODE enum */ PIPE_INT_MASK_MODE; /* * PIPE_INT_TYPE_MODE enum */ PIPE_INT_TYPE_MODE; /* * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum */ PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE; /******************************************************* * CURSOR Enums *******************************************************/ /* * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum */ CROB_MEM_PWR_LIGHT_SLEEP_MODE; /* * CURSOR_2X_MAGNIFY enum */ CURSOR_2X_MAGNIFY; /* * CURSOR_ENABLE enum */ CURSOR_ENABLE; /* * CURSOR_LINES_PER_CHUNK enum */ CURSOR_LINES_PER_CHUNK; /* * CURSOR_MODE enum */ CURSOR_MODE; /* * CURSOR_PERFMON_LATENCY_MEASURE_EN enum */ CURSOR_PERFMON_LATENCY_MEASURE_EN; /* * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum */ CURSOR_PERFMON_LATENCY_MEASURE_SEL; /* * CURSOR_PITCH enum */ CURSOR_PITCH; /* * CURSOR_REQ_MODE enum */ CURSOR_REQ_MODE; /* * CURSOR_SNOOP enum */ CURSOR_SNOOP; /* * CURSOR_STEREO_EN enum */ CURSOR_STEREO_EN; /* * CURSOR_SURFACE_TMZ enum */ CURSOR_SURFACE_TMZ; /* * CURSOR_SYSTEM enum */ CURSOR_SYSTEM; /* * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum */ CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS; /* * DMDATA_DONE enum */ DMDATA_DONE; /* * DMDATA_MODE enum */ DMDATA_MODE; /* * DMDATA_QOS_MODE enum */ DMDATA_QOS_MODE; /* * DMDATA_REPEAT enum */ DMDATA_REPEAT; /* * DMDATA_UNDERFLOW enum */ DMDATA_UNDERFLOW; /* * DMDATA_UNDERFLOW_CLEAR enum */ DMDATA_UNDERFLOW_CLEAR; /* * DMDATA_UPDATED enum */ DMDATA_UPDATED; /******************************************************* * HUBBUB_SDPIF Enums *******************************************************/ /* * RESPONSE_STATUS enum */ RESPONSE_STATUS; /******************************************************* * HUBBUB_RET_PATH Enums *******************************************************/ /* * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum */ DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE; /* * DCHUBBUB_MEM_PWR_DIS_MODE enum */ DCHUBBUB_MEM_PWR_DIS_MODE; /* * DCHUBBUB_MEM_PWR_MODE enum */ DCHUBBUB_MEM_PWR_MODE; /******************************************************* * MPC_CFG Enums *******************************************************/ /* * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum */ MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET; /* * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum */ MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET; /* * MPC_CFG_ADR_VUPDATE_LOCK_SET enum */ MPC_CFG_ADR_VUPDATE_LOCK_SET; /* * MPC_CFG_CFG_VUPDATE_LOCK_SET enum */ MPC_CFG_CFG_VUPDATE_LOCK_SET; /* * MPC_CFG_CUR_VUPDATE_LOCK_SET enum */ MPC_CFG_CUR_VUPDATE_LOCK_SET; /* * MPC_CFG_MPC_TEST_CLK_SEL enum */ MPC_CFG_MPC_TEST_CLK_SEL; /* * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum */ MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN; /* * MPC_CRC_CALC_INTERLACE_MODE enum */ MPC_CRC_CALC_INTERLACE_MODE; /* * MPC_CRC_CALC_MODE enum */ MPC_CRC_CALC_MODE; /* * MPC_CRC_CALC_STEREO_MODE enum */ MPC_CRC_CALC_STEREO_MODE; /* * MPC_CRC_SOURCE_SELECT enum */ MPC_CRC_SOURCE_SELECT; /* * MPC_DEBUG_BUS1_DATA_SELECT enum */ MPC_DEBUG_BUS1_DATA_SELECT; /* * MPC_DEBUG_BUS2_DATA_SELECT enum */ MPC_DEBUG_BUS2_DATA_SELECT; /* * MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT enum */ MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT; /* * MPC_DEBUG_BUS_MPCC_BYTE_SELECT enum */ MPC_DEBUG_BUS_MPCC_BYTE_SELECT; /******************************************************* * MPC_OCSC Enums *******************************************************/ /* * MPC_OCSC_COEF_FORMAT enum */ MPC_OCSC_COEF_FORMAT; /* * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum */ MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN; /* * MPC_OUT_CSC_MODE enum */ MPC_OUT_CSC_MODE; /* * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum */ MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE; /* * MPC_OUT_RATE_CONTROL_DISABLE_SET enum */ MPC_OUT_RATE_CONTROL_DISABLE_SET; /******************************************************* * MPCC Enums *******************************************************/ /* * MPCC_BG_COLOR_BPC enum */ MPCC_BG_COLOR_BPC; /* * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum */ MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY; /* * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum */ MPCC_CONTROL_MPCC_ALPHA_BLND_MODE; /* * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum */ MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE; /* * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum */ MPCC_CONTROL_MPCC_BOT_GAIN_MODE; /* * MPCC_CONTROL_MPCC_MODE enum */ MPCC_CONTROL_MPCC_MODE; /* * MPCC_SM_CONTROL_MPCC_SM_EN enum */ MPCC_SM_CONTROL_MPCC_SM_EN; /* * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum */ MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT; /* * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum */ MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL; /* * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum */ MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL; /* * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum */ MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT; /* * MPCC_SM_CONTROL_MPCC_SM_MODE enum */ MPCC_SM_CONTROL_MPCC_SM_MODE; /* * MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN enum */ MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN; /******************************************************* * MPCC_OGAM Enums *******************************************************/ /* * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum */ MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM; /* * MPCC_GAMUT_REMAP_MODE_ENUM enum */ MPCC_GAMUT_REMAP_MODE_ENUM; /* * MPCC_OGAM_LUT_2_CONFIG_ENUM enum */ MPCC_OGAM_LUT_2_CONFIG_ENUM; /* * MPCC_OGAM_LUT_CONFIG_MODE enum */ MPCC_OGAM_LUT_CONFIG_MODE; /* * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum */ MPCC_OGAM_LUT_PWL_DISABLE_ENUM; /* * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum */ MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL; /* * MPCC_OGAM_LUT_RAM_SEL enum */ MPCC_OGAM_LUT_RAM_SEL; /* * MPCC_OGAM_LUT_READ_COLOR_SEL enum */ MPCC_OGAM_LUT_READ_COLOR_SEL; /* * MPCC_OGAM_LUT_READ_DBG enum */ MPCC_OGAM_LUT_READ_DBG; /* * MPCC_OGAM_LUT_SEL_ENUM enum */ MPCC_OGAM_LUT_SEL_ENUM; /* * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum */ MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM; /* * MPCC_OGAM_NUM_SEG enum */ MPCC_OGAM_NUM_SEG; /* * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum */ MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN; /******************************************************* * MPCC_MCM Enums *******************************************************/ /* * MPCC_MCM_3DLUT_30BIT_ENUM enum */ MPCC_MCM_3DLUT_30BIT_ENUM; /* * MPCC_MCM_3DLUT_RAM_SEL enum */ MPCC_MCM_3DLUT_RAM_SEL; /* * MPCC_MCM_3DLUT_SIZE_ENUM enum */ MPCC_MCM_3DLUT_SIZE_ENUM; /* * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum */ MPCC_MCM_GAMMA_LUT_MODE_ENUM; /* * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum */ MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM; /* * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum */ MPCC_MCM_GAMMA_LUT_SEL_ENUM; /* * MPCC_MCM_LUT_2_MODE_ENUM enum */ MPCC_MCM_LUT_2_MODE_ENUM; /* * MPCC_MCM_LUT_CONFIG_MODE enum */ MPCC_MCM_LUT_CONFIG_MODE; /* * MPCC_MCM_LUT_NUM_SEG enum */ MPCC_MCM_LUT_NUM_SEG; /* * MPCC_MCM_LUT_RAM_SEL enum */ MPCC_MCM_LUT_RAM_SEL; /* * MPCC_MCM_LUT_READ_COLOR_SEL enum */ MPCC_MCM_LUT_READ_COLOR_SEL; /* * MPCC_MCM_LUT_READ_DBG enum */ MPCC_MCM_LUT_READ_DBG; /* * MPCC_MCM_MEM_PWR_FORCE_ENUM enum */ MPCC_MCM_MEM_PWR_FORCE_ENUM; /* * MPCC_MCM_MEM_PWR_STATE_ENUM enum */ MPCC_MCM_MEM_PWR_STATE_ENUM; /******************************************************* * ABM Enums *******************************************************/ /******************************************************* * DPG Enums *******************************************************/ /* * ENUM_DPG_BIT_DEPTH enum */ ENUM_DPG_BIT_DEPTH; /* * ENUM_DPG_DYNAMIC_RANGE enum */ ENUM_DPG_DYNAMIC_RANGE; /* * ENUM_DPG_EN enum */ ENUM_DPG_EN; /* * ENUM_DPG_FIELD_POLARITY enum */ ENUM_DPG_FIELD_POLARITY; /* * ENUM_DPG_MODE enum */ ENUM_DPG_MODE; /******************************************************* * FMT Enums *******************************************************/ /* * FMTMEM_PWR_DIS_CTRL enum */ FMTMEM_PWR_DIS_CTRL; /* * FMTMEM_PWR_FORCE_CTRL enum */ FMTMEM_PWR_FORCE_CTRL; /* * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum */ FMT_BIT_DEPTH_CONTROL_25FRC_SEL; /* * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum */ FMT_BIT_DEPTH_CONTROL_50FRC_SEL; /* * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum */ FMT_BIT_DEPTH_CONTROL_75FRC_SEL; /* * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum */ FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH; /* * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum */ FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH; /* * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum */ FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL; /* * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum */ FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH; /* * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum */ FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE; /* * FMT_CLAMP_CNTL_COLOR_FORMAT enum */ FMT_CLAMP_CNTL_COLOR_FORMAT; /* * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum */ FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS; /* * FMT_CONTROL_PIXEL_ENCODING enum */ FMT_CONTROL_PIXEL_ENCODING; /* * FMT_CONTROL_SUBSAMPLING_MODE enum */ FMT_CONTROL_SUBSAMPLING_MODE; /* * FMT_CONTROL_SUBSAMPLING_ORDER enum */ FMT_CONTROL_SUBSAMPLING_ORDER; /* * FMT_DEBUG_CNTL_COLOR_SELECT enum */ FMT_DEBUG_CNTL_COLOR_SELECT; /* * FMT_DYNAMIC_EXP_MODE enum */ FMT_DYNAMIC_EXP_MODE; /* * FMT_FRAME_RANDOM_ENABLE_CONTROL enum */ FMT_FRAME_RANDOM_ENABLE_CONTROL; /* * FMT_POWER_STATE_ENUM enum */ FMT_POWER_STATE_ENUM; /* * FMT_RGB_RANDOM_ENABLE_CONTROL enum */ FMT_RGB_RANDOM_ENABLE_CONTROL; /* * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum */ FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL; /* * FMT_SPATIAL_DITHER_MODE enum */ FMT_SPATIAL_DITHER_MODE; /* * FMT_STEREOSYNC_OVERRIDE_CONTROL enum */ FMT_STEREOSYNC_OVERRIDE_CONTROL; /* * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum */ FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0; /******************************************************* * OPPBUF Enums *******************************************************/ /* * OPPBUF_DISPLAY_SEGMENTATION enum */ OPPBUF_DISPLAY_SEGMENTATION; /******************************************************* * OPP_PIPE Enums *******************************************************/ /* * OPP_PIPE_CLOCK_ENABLE_CONTROL enum */ OPP_PIPE_CLOCK_ENABLE_CONTROL; /* * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum */ OPP_PIPE_DIGTIAL_BYPASS_CONTROL; /******************************************************* * OPP_PIPE_CRC Enums *******************************************************/ /* * OPP_PIPE_CRC_CONT_EN enum */ OPP_PIPE_CRC_CONT_EN; /* * OPP_PIPE_CRC_EN enum */ OPP_PIPE_CRC_EN; /* * OPP_PIPE_CRC_INTERLACE_EN enum */ OPP_PIPE_CRC_INTERLACE_EN; /* * OPP_PIPE_CRC_INTERLACE_MODE enum */ OPP_PIPE_CRC_INTERLACE_MODE; /* * OPP_PIPE_CRC_ONE_SHOT_PENDING enum */ OPP_PIPE_CRC_ONE_SHOT_PENDING; /* * OPP_PIPE_CRC_PIXEL_SELECT enum */ OPP_PIPE_CRC_PIXEL_SELECT; /* * OPP_PIPE_CRC_SOURCE_SELECT enum */ OPP_PIPE_CRC_SOURCE_SELECT; /* * OPP_PIPE_CRC_STEREO_EN enum */ OPP_PIPE_CRC_STEREO_EN; /* * OPP_PIPE_CRC_STEREO_MODE enum */ OPP_PIPE_CRC_STEREO_MODE; /******************************************************* * OPP_TOP Enums *******************************************************/ /* * OPP_ABM_DEBUG_BUS_SELECT_CONTROL enum */ OPP_ABM_DEBUG_BUS_SELECT_CONTROL; /* * OPP_DPG_DEBUG_BUS_SELECT_CONTROL enum */ OPP_DPG_DEBUG_BUS_SELECT_CONTROL; /* * OPP_FMT_DEBUG_BUS_SELECT_CONTROL enum */ OPP_FMT_DEBUG_BUS_SELECT_CONTROL; /* * OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL enum */ OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL; /* * OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL enum */ OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL; /* * OPP_TEST_CLK_SEL_CONTROL enum */ OPP_TEST_CLK_SEL_CONTROL; /* * OPP_TOP_CLOCK_ENABLE_STATUS enum */ OPP_TOP_CLOCK_ENABLE_STATUS; /* * OPP_TOP_CLOCK_GATING_CONTROL enum */ OPP_TOP_CLOCK_GATING_CONTROL; /******************************************************* * DSCRM Enums *******************************************************/ /* * ENUM_DSCRM_EN enum */ ENUM_DSCRM_EN; /******************************************************* * OTG Enums *******************************************************/ /* * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum */ MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK; /* * MASTER_UPDATE_LOCK_SEL enum */ MASTER_UPDATE_LOCK_SEL; /* * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum */ MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE; /* * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum */ OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN; /* * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum */ OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB; /* * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum */ OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR; /* * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum */ OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE; /* * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum */ OTG_CONTROL_OTG_DISABLE_POINT_CNTL; /* * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum */ OTG_CONTROL_OTG_FIELD_NUMBER_CNTL; /* * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum */ OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY; /* * OTG_CONTROL_OTG_MASTER_EN enum */ OTG_CONTROL_OTG_MASTER_EN; /* * OTG_CONTROL_OTG_OUT_MUX enum */ OTG_CONTROL_OTG_OUT_MUX; /* * OTG_CONTROL_OTG_START_POINT_CNTL enum */ OTG_CONTROL_OTG_START_POINT_CNTL; /* * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum */ OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN; /* * OTG_CRC_CNTL_OTG_CRC1_EN enum */ OTG_CRC_CNTL_OTG_CRC1_EN; /* * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum */ OTG_CRC_CNTL_OTG_CRC_CONT_EN; /* * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum */ OTG_CRC_CNTL_OTG_CRC_CONT_MODE; /* * OTG_CRC_CNTL_OTG_CRC_EN enum */ OTG_CRC_CNTL_OTG_CRC_EN; /* * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum */ OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE; /* * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum */ OTG_CRC_CNTL_OTG_CRC_STEREO_MODE; /* * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum */ OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS; /* * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum */ OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT; /* * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum */ OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT; /* * OTG_DIG_UPDATE_VCOUNT_MODE enum */ OTG_DIG_UPDATE_VCOUNT_MODE; /* * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum */ OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE; /* * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum */ OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY; /* * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum */ OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME; /* * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum */ OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN; /* * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum */ OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY; /* * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum */ OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY; /* * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum */ OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT; /* * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum */ OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK; /* * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum */ OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR; /* * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum */ OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE; /* * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum */ OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL; /* * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum */ OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL; /* * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum */ OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL; /* * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum */ OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL; /* * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum */ OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD; /* * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum */ OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL; /* * OTG_GLOBAL_UPDATE_LOCK_EN enum */ OTG_GLOBAL_UPDATE_LOCK_EN; /* * OTG_GSL_MASTER_MODE enum */ OTG_GSL_MASTER_MODE; /* * OTG_HORZ_REPETITION_COUNT enum */ OTG_HORZ_REPETITION_COUNT; /* * OTG_H_SYNC_A_POL enum */ OTG_H_SYNC_A_POL; /* * OTG_H_TIMING_DIV_MODE enum */ OTG_H_TIMING_DIV_MODE; /* * OTG_H_TIMING_DIV_MODE_MANUAL enum */ OTG_H_TIMING_DIV_MODE_MANUAL; /* * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum */ OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE; /* * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum */ OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD; /* * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum */ OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK; /* * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum */ OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE; /* * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum */ OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK; /* * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum */ OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE; /* * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum */ OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK; /* * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum */ OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE; /* * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum */ OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK; /* * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum */ OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE; /* * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum */ OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK; /* * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum */ OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE; /* * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum */ OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK; /* * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum */ OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE; /* * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum */ OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK; /* * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum */ OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE; /* * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum */ OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE; /* * OTG_MASTER_UPDATE_LOCK_DB_EN enum */ OTG_MASTER_UPDATE_LOCK_DB_EN; /* * OTG_MASTER_UPDATE_LOCK_GSL_EN enum */ OTG_MASTER_UPDATE_LOCK_GSL_EN; /* * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum */ OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE; /* * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum */ OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL; /* * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum */ OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR; /* * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum */ OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR; /* * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum */ OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE; /* * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum */ OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE; /* * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum */ OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE; /* * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum */ OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE; /* * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum */ OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL; /* * OTG_STEREO_CONTROL_OTG_STEREO_EN enum */ OTG_STEREO_CONTROL_OTG_STEREO_EN; /* * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum */ OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY; /* * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum */ OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY; /* * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum */ OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE; /* * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum */ OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR; /* * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum */ OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT; /* * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum */ OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN; /* * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum */ OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT; /* * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum */ OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT; /* * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum */ OTG_TRIGA_FALLING_EDGE_DETECT_CNTL; /* * OTG_TRIGA_FREQUENCY_SELECT enum */ OTG_TRIGA_FREQUENCY_SELECT; /* * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum */ OTG_TRIGA_RISING_EDGE_DETECT_CNTL; /* * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum */ OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR; /* * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum */ OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT; /* * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum */ OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN; /* * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum */ OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT; /* * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum */ OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT; /* * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum */ OTG_TRIGB_FALLING_EDGE_DETECT_CNTL; /* * OTG_TRIGB_FREQUENCY_SELECT enum */ OTG_TRIGB_FREQUENCY_SELECT; /* * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum */ OTG_TRIGB_RISING_EDGE_DETECT_CNTL; /* * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum */ OTG_UPDATE_LOCK_OTG_UPDATE_LOCK; /* * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum */ OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR; /* * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum */ OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE; /* * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum */ OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE; /* * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum */ OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY; /* * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum */ OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR; /* * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum */ OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE; /* * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum */ OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE; /* * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum */ OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR; /* * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum */ OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE; /* * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum */ OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE; /* * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum */ OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE; /* * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum */ OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR; /* * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum */ OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR; /* * OTG_VUPDATE_BLOCK_DISABLE enum */ OTG_VUPDATE_BLOCK_DISABLE; /* * OTG_V_SYNC_A_POL enum */ OTG_V_SYNC_A_POL; /* * OTG_V_SYNC_MODE enum */ OTG_V_SYNC_MODE; /* * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum */ OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD; /* * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum */ OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT; /* * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum */ OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC; /* * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum */ OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL; /* * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum */ OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL; /* * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum */ OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK; /******************************************************* * OPTC_MISC Enums *******************************************************/ /* * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum */ OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL; /******************************************************* * DMCUB Enums *******************************************************/ /* * DC_DMCUB_INT_TYPE enum */ DC_DMCUB_INT_TYPE; /* * DC_DMCUB_TIMER_WINDOW enum */ DC_DMCUB_TIMER_WINDOW; /******************************************************* * RBBMIF Enums *******************************************************/ /* * INVALID_REG_ACCESS_TYPE enum */ INVALID_REG_ACCESS_TYPE; /******************************************************* * IHC Enums *******************************************************/ /* * DMU_DC_GPU_TIMER_READ_SELECT enum */ DMU_DC_GPU_TIMER_READ_SELECT; /* * DMU_DC_GPU_TIMER_START_POSITION enum */ DMU_DC_GPU_TIMER_START_POSITION; /* * IHC_INTERRUPT_DEST enum */ IHC_INTERRUPT_DEST; /* * IHC_INTERRUPT_LINE_STATUS enum */ IHC_INTERRUPT_LINE_STATUS; /******************************************************* * DMU_MISC Enums *******************************************************/ /* * DC_SMU_INTERRUPT_ENABLE enum */ DC_SMU_INTERRUPT_ENABLE; /* * DMU_CLOCK_ON enum */ DMU_CLOCK_ON; /* * SMU_INTR enum */ SMU_INTR; /******************************************************* * DCCG Enums *******************************************************/ /* * ALLOW_SR_ON_TRANS_REQ enum */ ALLOW_SR_ON_TRANS_REQ; /* * AMCLOCK_ENABLE enum */ AMCLOCK_ENABLE; /* * CLEAR_SMU_INTR enum */ CLEAR_SMU_INTR; /* * CLOCK_BRANCH_SOFT_RESET enum */ CLOCK_BRANCH_SOFT_RESET; /* * DCCG_AUDIO_DTO0_SOURCE_SEL enum */ DCCG_AUDIO_DTO0_SOURCE_SEL; /* * DCCG_AUDIO_DTO2_SOURCE_SEL enum */ DCCG_AUDIO_DTO2_SOURCE_SEL; /* * DCCG_AUDIO_DTO_SEL enum */ DCCG_AUDIO_DTO_SEL; /* * DCCG_AUDIO_DTO_USE_512FBR_DTO enum */ DCCG_AUDIO_DTO_USE_512FBR_DTO; /* * DCCG_DBG_BLOCK_SEL enum */ DCCG_DBG_BLOCK_SEL; /* * DCCG_DBG_EN enum */ DCCG_DBG_EN; /* * DCCG_DEEP_COLOR_CNTL enum */ DCCG_DEEP_COLOR_CNTL; /* * DCCG_FIFO_ERRDET_OVR_EN enum */ DCCG_FIFO_ERRDET_OVR_EN; /* * DCCG_FIFO_ERRDET_RESET enum */ DCCG_FIFO_ERRDET_RESET; /* * DCCG_FIFO_ERRDET_STATE enum */ DCCG_FIFO_ERRDET_STATE; /* * DCCG_PERF_MODE_HSYNC enum */ DCCG_PERF_MODE_HSYNC; /* * DCCG_PERF_MODE_VSYNC enum */ DCCG_PERF_MODE_VSYNC; /* * DCCG_PERF_OTG_SELECT enum */ DCCG_PERF_OTG_SELECT; /* * DCCG_PERF_RUN enum */ DCCG_PERF_RUN; /* * DC_MEM_GLOBAL_PWR_REQ_DIS enum */ DC_MEM_GLOBAL_PWR_REQ_DIS; /* * DIO_FIFO_ERROR enum */ DIO_FIFO_ERROR; /* * DISABLE_CLOCK_GATING enum */ DISABLE_CLOCK_GATING; /* * DISABLE_CLOCK_GATING_IN_DCO enum */ DISABLE_CLOCK_GATING_IN_DCO; /* * DISPCLK_CHG_FWD_CORR_DISABLE enum */ DISPCLK_CHG_FWD_CORR_DISABLE; /* * DISPCLK_FREQ_RAMP_DONE enum */ DISPCLK_FREQ_RAMP_DONE; /* * DPREFCLK_SRC_SEL enum */ DPREFCLK_SRC_SEL; /* * DP_DTO_DS_DISABLE enum */ DP_DTO_DS_DISABLE; /* * DS_HW_CAL_ENABLE enum */ DS_HW_CAL_ENABLE; /* * DS_JITTER_COUNT_SRC_SEL enum */ DS_JITTER_COUNT_SRC_SEL; /* * DS_REF_SRC enum */ DS_REF_SRC; /* * DVOACLKC_IN_PHASE enum */ DVOACLKC_IN_PHASE; /* * DVOACLKC_MVP_IN_PHASE enum */ DVOACLKC_MVP_IN_PHASE; /* * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum */ DVOACLKC_MVP_SKEW_PHASE_OVERRIDE; /* * DVOACLKD_IN_PHASE enum */ DVOACLKD_IN_PHASE; /* * DVOACLK_COARSE_SKEW_CNTL enum */ DVOACLK_COARSE_SKEW_CNTL; /* * DVOACLK_FINE_SKEW_CNTL enum */ DVOACLK_FINE_SKEW_CNTL; /* * DVO_ENABLE_RST enum */ DVO_ENABLE_RST; /* * ENABLE enum */ ENABLE; /* * ENABLE_CLOCK enum */ ENABLE_CLOCK; /* * FORCE_DISABLE_CLOCK enum */ FORCE_DISABLE_CLOCK; /* * HDMICHARCLK_SRC_SEL enum */ HDMICHARCLK_SRC_SEL; /* * HDMISTREAMCLK_DTO_FORCE_DIS enum */ HDMISTREAMCLK_DTO_FORCE_DIS; /* * HDMISTREAMCLK_SRC_SEL enum */ HDMISTREAMCLK_SRC_SEL; /* * JITTER_REMOVE_DISABLE enum */ JITTER_REMOVE_DISABLE; /* * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum */ MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL; /* * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum */ MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL; /* * OTG_ADD_PIXEL enum */ OTG_ADD_PIXEL; /* * OTG_DROP_PIXEL enum */ OTG_DROP_PIXEL; /* * PHYSYMCLK_FORCE_EN enum */ PHYSYMCLK_FORCE_EN; /* * PHYSYMCLK_FORCE_SRC_SEL enum */ PHYSYMCLK_FORCE_SRC_SEL; /* * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum */ PIPE_PHYPLL_PIXEL_RATE_SOURCE; /* * PIPE_PIXEL_RATE_PLL_SOURCE enum */ PIPE_PIXEL_RATE_PLL_SOURCE; /* * PIPE_PIXEL_RATE_SOURCE enum */ PIPE_PIXEL_RATE_SOURCE; /* * PLL_CFG_IF_SOFT_RESET enum */ PLL_CFG_IF_SOFT_RESET; /* * SYMCLK_FE_FORCE_EN enum */ SYMCLK_FE_FORCE_EN; /* * SYMCLK_FE_FORCE_SRC enum */ SYMCLK_FE_FORCE_SRC; /* * TEST_CLK_DIV_SEL enum */ TEST_CLK_DIV_SEL; /* * VSYNC_CNT_LATCH_MASK enum */ VSYNC_CNT_LATCH_MASK; /* * VSYNC_CNT_RESET_SEL enum */ VSYNC_CNT_RESET_SEL; /* * XTAL_REF_CLOCK_SOURCE_SEL enum */ XTAL_REF_CLOCK_SOURCE_SEL; /* * XTAL_REF_SEL enum */ XTAL_REF_SEL; /******************************************************* * HPD Enums *******************************************************/ /* * HPD_INT_CONTROL_ACK enum */ HPD_INT_CONTROL_ACK; /* * HPD_INT_CONTROL_POLARITY enum */ HPD_INT_CONTROL_POLARITY; /* * HPD_INT_CONTROL_RX_INT_ACK enum */ HPD_INT_CONTROL_RX_INT_ACK; /******************************************************* * DP Enums *******************************************************/ /* * DPHY_8B10B_CUR_DISP enum */ DPHY_8B10B_CUR_DISP; /* * DPHY_8B10B_RESET enum */ DPHY_8B10B_RESET; /* * DPHY_ALT_SCRAMBLER_RESET_EN enum */ DPHY_ALT_SCRAMBLER_RESET_EN; /* * DPHY_ALT_SCRAMBLER_RESET_SEL enum */ DPHY_ALT_SCRAMBLER_RESET_SEL; /* * DPHY_ATEST_SEL_LANE0 enum */ DPHY_ATEST_SEL_LANE0; /* * DPHY_ATEST_SEL_LANE1 enum */ DPHY_ATEST_SEL_LANE1; /* * DPHY_ATEST_SEL_LANE2 enum */ DPHY_ATEST_SEL_LANE2; /* * DPHY_ATEST_SEL_LANE3 enum */ DPHY_ATEST_SEL_LANE3; /* * DPHY_BYPASS enum */ DPHY_BYPASS; /* * DPHY_CRC_CONT_EN enum */ DPHY_CRC_CONT_EN; /* * DPHY_CRC_EN enum */ DPHY_CRC_EN; /* * DPHY_CRC_FIELD enum */ DPHY_CRC_FIELD; /* * DPHY_CRC_MST_PHASE_ERROR_ACK enum */ DPHY_CRC_MST_PHASE_ERROR_ACK; /* * DPHY_CRC_SEL enum */ DPHY_CRC_SEL; /* * DPHY_FEC_ENABLE enum */ DPHY_FEC_ENABLE; /* * DPHY_FEC_READY enum */ DPHY_FEC_READY; /* * DPHY_LOAD_BS_COUNT_START enum */ DPHY_LOAD_BS_COUNT_START; /* * DPHY_PRBS_EN enum */ DPHY_PRBS_EN; /* * DPHY_PRBS_SEL enum */ DPHY_PRBS_SEL; /* * DPHY_RX_FAST_TRAINING_CAPABLE enum */ DPHY_RX_FAST_TRAINING_CAPABLE; /* * DPHY_SCRAMBLER_ADVANCE enum */ DPHY_SCRAMBLER_ADVANCE; /* * DPHY_SCRAMBLER_DIS enum */ DPHY_SCRAMBLER_DIS; /* * DPHY_SCRAMBLER_KCODE enum */ DPHY_SCRAMBLER_KCODE; /* * DPHY_SCRAMBLER_SEL enum */ DPHY_SCRAMBLER_SEL; /* * DPHY_SKEW_BYPASS enum */ DPHY_SKEW_BYPASS; /* * DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM enum */ DPHY_STREAM_RESET_DURING_FAST_TRAINING_ENUM; /* * DPHY_SW_FAST_TRAINING_START enum */ DPHY_SW_FAST_TRAINING_START; /* * DPHY_TRAINING_PATTERN_SEL enum */ DPHY_TRAINING_PATTERN_SEL; /* * DP_COMPONENT_DEPTH enum */ DP_COMPONENT_DEPTH; /* * DP_CP_ENCRYPTION_TYPE enum */ DP_CP_ENCRYPTION_TYPE; /* * DP_DPHY_8B10B_EXT_DISP enum */ DP_DPHY_8B10B_EXT_DISP; /* * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum */ DP_DPHY_FAST_TRAINING_COMPLETE_ACK; /* * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum */ DP_DPHY_FAST_TRAINING_COMPLETE_MASK; /* * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum */ DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN; /* * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum */ DP_DPHY_HBR2_PATTERN_CONTROL_MODE; /* * DP_DSC_MODE enum */ DP_DSC_MODE; /* * DP_EMBEDDED_PANEL_MODE enum */ DP_EMBEDDED_PANEL_MODE; /* * DP_LINK_TRAINING_COMPLETE enum */ DP_LINK_TRAINING_COMPLETE; /* * DP_LINK_TRAINING_SWITCH_MODE enum */ DP_LINK_TRAINING_SWITCH_MODE; /* * DP_ML_PHY_SEQ_MODE enum */ DP_ML_PHY_SEQ_MODE; /* * DP_MSA_V_TIMING_OVERRIDE_EN enum */ DP_MSA_V_TIMING_OVERRIDE_EN; /* * DP_MSE_BLANK_CODE enum */ DP_MSE_BLANK_CODE; /* * DP_MSE_LINK_LINE enum */ DP_MSE_LINK_LINE; /* * DP_MSE_SAT_ENCRYPT0 enum */ DP_MSE_SAT_ENCRYPT0; /* * DP_MSE_SAT_ENCRYPT1 enum */ DP_MSE_SAT_ENCRYPT1; /* * DP_MSE_SAT_ENCRYPT2 enum */ DP_MSE_SAT_ENCRYPT2; /* * DP_MSE_SAT_ENCRYPT3 enum */ DP_MSE_SAT_ENCRYPT3; /* * DP_MSE_SAT_ENCRYPT4 enum */ DP_MSE_SAT_ENCRYPT4; /* * DP_MSE_SAT_ENCRYPT5 enum */ DP_MSE_SAT_ENCRYPT5; /* * DP_MSE_SAT_UPDATE_ACT enum */ DP_MSE_SAT_UPDATE_ACT; /* * DP_MSE_TIMESTAMP_MODE enum */ DP_MSE_TIMESTAMP_MODE; /* * DP_MSE_ZERO_ENCODER enum */ DP_MSE_ZERO_ENCODER; /* * DP_MSO_NUM_OF_SST_LINKS enum */ DP_MSO_NUM_OF_SST_LINKS; /* * DP_PIXEL_ENCODING enum */ DP_PIXEL_ENCODING; /* * DP_PIXEL_PER_CYCLE_PROCESSING_NUM enum */ DP_PIXEL_PER_CYCLE_PROCESSING_NUM; /* * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum */ DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE; /* * DP_SEC_ASP_PRIORITY enum */ DP_SEC_ASP_PRIORITY; /* * DP_SEC_AUDIO_MUTE enum */ DP_SEC_AUDIO_MUTE; /* * DP_SEC_COLLISION_ACK enum */ DP_SEC_COLLISION_ACK; /* * DP_SEC_GSP0_PRIORITY enum */ DP_SEC_GSP0_PRIORITY; /* * DP_SEC_GSP_SEND enum */ DP_SEC_GSP_SEND; /* * DP_SEC_GSP_SEND_ANY_LINE enum */ DP_SEC_GSP_SEND_ANY_LINE; /* * DP_SEC_GSP_SEND_PPS enum */ DP_SEC_GSP_SEND_PPS; /* * DP_SEC_LINE_REFERENCE enum */ DP_SEC_LINE_REFERENCE; /* * DP_SEC_TIMESTAMP_MODE enum */ DP_SEC_TIMESTAMP_MODE; /* * DP_STEER_OVERFLOW_ACK enum */ DP_STEER_OVERFLOW_ACK; /* * DP_STEER_OVERFLOW_MASK enum */ DP_STEER_OVERFLOW_MASK; /* * DP_SYNC_POLARITY enum */ DP_SYNC_POLARITY; /* * DP_TU_OVERFLOW_ACK enum */ DP_TU_OVERFLOW_ACK; /* * DP_UDI_LANES enum */ DP_UDI_LANES; /* * DP_VID_ENHANCED_FRAME_MODE enum */ DP_VID_ENHANCED_FRAME_MODE; /* * DP_VID_M_N_DOUBLE_BUFFER_MODE enum */ DP_VID_M_N_DOUBLE_BUFFER_MODE; /* * DP_VID_M_N_GEN_EN enum */ DP_VID_M_N_GEN_EN; /* * DP_VID_N_MUL enum */ DP_VID_N_MUL; /* * DP_VID_STREAM_DISABLE_ACK enum */ DP_VID_STREAM_DISABLE_ACK; /* * DP_VID_STREAM_DISABLE_MASK enum */ DP_VID_STREAM_DISABLE_MASK; /* * DP_VID_STREAM_DIS_DEFER enum */ DP_VID_STREAM_DIS_DEFER; /* * DP_VID_VBID_FIELD_POL enum */ DP_VID_VBID_FIELD_POL; /* * FEC_ACTIVE_STATUS enum */ FEC_ACTIVE_STATUS; /******************************************************* * DIG Enums *******************************************************/ /* * DIG_BE_CNTL_HPD_SELECT enum */ DIG_BE_CNTL_HPD_SELECT; /* * DIG_BE_CNTL_MODE enum */ DIG_BE_CNTL_MODE; /* * DIG_DIGITAL_BYPASS_ENABLE enum */ DIG_DIGITAL_BYPASS_ENABLE; /* * DIG_DIGITAL_BYPASS_SEL enum */ DIG_DIGITAL_BYPASS_SEL; /* * DIG_FE_CNTL_SOURCE_SELECT enum */ DIG_FE_CNTL_SOURCE_SELECT; /* * DIG_FE_CNTL_STEREOSYNC_SELECT enum */ DIG_FE_CNTL_STEREOSYNC_SELECT; /* * DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX enum */ DIG_FIFO_CTRL_FORCE_RECOMP_MINMAX; /* * DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL enum */ DIG_FIFO_CTRL_USE_OVERWRITE_LEVEL; /* * DIG_FIFO_FORCE_RECAL_AVERAGE enum */ DIG_FIFO_FORCE_RECAL_AVERAGE; /* * DIG_FIFO_OUTPUT_PROCESSING_MODE enum */ DIG_FIFO_OUTPUT_PROCESSING_MODE; /* * DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR enum */ DIG_FIFO_OVERFLOW_UNDERFLOW_ERROR; /* * DIG_FIFO_READ_CLOCK_SRC enum */ DIG_FIFO_READ_CLOCK_SRC; /* * DIG_INPUT_PIXEL_SEL enum */ DIG_INPUT_PIXEL_SEL; /* * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum */ DIG_OUTPUT_CRC_CNTL_LINK_SEL; /* * DIG_OUTPUT_CRC_DATA_SEL enum */ DIG_OUTPUT_CRC_DATA_SEL; /* * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum */ DIG_RANDOM_PATTERN_SEED_RAN_PAT; /* * DIG_SL_PIXEL_GROUPING enum */ DIG_SL_PIXEL_GROUPING; /* * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum */ DIG_TEST_PATTERN_EXTERNAL_RESET_EN; /* * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum */ DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL; /* * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum */ DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN; /* * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum */ DIG_TEST_PATTERN_RANDOM_PATTERN_RESET; /* * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum */ DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN; /* * DOLBY_VISION_ENABLE enum */ DOLBY_VISION_ENABLE; /* * HDMI_ACP_SEND enum */ HDMI_ACP_SEND; /* * HDMI_ACR_AUDIO_PRIORITY enum */ HDMI_ACR_AUDIO_PRIORITY; /* * HDMI_ACR_CONT enum */ HDMI_ACR_CONT; /* * HDMI_ACR_N_MULTIPLE enum */ HDMI_ACR_N_MULTIPLE; /* * HDMI_ACR_SELECT enum */ HDMI_ACR_SELECT; /* * HDMI_ACR_SEND enum */ HDMI_ACR_SEND; /* * HDMI_ACR_SOURCE enum */ HDMI_ACR_SOURCE; /* * HDMI_AUDIO_DELAY_EN enum */ HDMI_AUDIO_DELAY_EN; /* * HDMI_AUDIO_INFO_CONT enum */ HDMI_AUDIO_INFO_CONT; /* * HDMI_AUDIO_INFO_SEND enum */ HDMI_AUDIO_INFO_SEND; /* * HDMI_CLOCK_CHANNEL_RATE enum */ HDMI_CLOCK_CHANNEL_RATE; /* * HDMI_DATA_SCRAMBLE_EN enum */ HDMI_DATA_SCRAMBLE_EN; /* * HDMI_DEEP_COLOR_DEPTH enum */ HDMI_DEEP_COLOR_DEPTH; /* * HDMI_DEFAULT_PAHSE enum */ HDMI_DEFAULT_PAHSE; /* * HDMI_ERROR_ACK enum */ HDMI_ERROR_ACK; /* * HDMI_ERROR_MASK enum */ HDMI_ERROR_MASK; /* * HDMI_GC_AVMUTE enum */ HDMI_GC_AVMUTE; /* * HDMI_GC_AVMUTE_CONT enum */ HDMI_GC_AVMUTE_CONT; /* * HDMI_GC_CONT enum */ HDMI_GC_CONT; /* * HDMI_GC_SEND enum */ HDMI_GC_SEND; /* * HDMI_GENERIC_CONT enum */ HDMI_GENERIC_CONT; /* * HDMI_GENERIC_SEND enum */ HDMI_GENERIC_SEND; /* * HDMI_ISRC_CONT enum */ HDMI_ISRC_CONT; /* * HDMI_ISRC_SEND enum */ HDMI_ISRC_SEND; /* * HDMI_KEEPOUT_MODE enum */ HDMI_KEEPOUT_MODE; /* * HDMI_METADATA_ENABLE enum */ HDMI_METADATA_ENABLE; /* * HDMI_MPEG_INFO_CONT enum */ HDMI_MPEG_INFO_CONT; /* * HDMI_MPEG_INFO_SEND enum */ HDMI_MPEG_INFO_SEND; /* * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum */ HDMI_NO_EXTRA_NULL_PACKET_FILLED; /* * HDMI_NULL_SEND enum */ HDMI_NULL_SEND; /* * HDMI_PACKET_GEN_VERSION enum */ HDMI_PACKET_GEN_VERSION; /* * HDMI_PACKET_LINE_REFERENCE enum */ HDMI_PACKET_LINE_REFERENCE; /* * HDMI_PACKING_PHASE_OVERRIDE enum */ HDMI_PACKING_PHASE_OVERRIDE; /* * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum */ LVTMA_RANDOM_PATTERN_SEED_RAN_PAT; /* * TMDS_COLOR_FORMAT enum */ TMDS_COLOR_FORMAT; /* * TMDS_CTL0_DATA_INVERT enum */ TMDS_CTL0_DATA_INVERT; /* * TMDS_CTL0_DATA_MODULATION enum */ TMDS_CTL0_DATA_MODULATION; /* * TMDS_CTL0_DATA_SEL enum */ TMDS_CTL0_DATA_SEL; /* * TMDS_CTL0_PATTERN_OUT_EN enum */ TMDS_CTL0_PATTERN_OUT_EN; /* * TMDS_CTL1_DATA_INVERT enum */ TMDS_CTL1_DATA_INVERT; /* * TMDS_CTL1_DATA_MODULATION enum */ TMDS_CTL1_DATA_MODULATION; /* * TMDS_CTL1_DATA_SEL enum */ TMDS_CTL1_DATA_SEL; /* * TMDS_CTL1_PATTERN_OUT_EN enum */ TMDS_CTL1_PATTERN_OUT_EN; /* * TMDS_CTL2_DATA_INVERT enum */ TMDS_CTL2_DATA_INVERT; /* * TMDS_CTL2_DATA_MODULATION enum */ TMDS_CTL2_DATA_MODULATION; /* * TMDS_CTL2_DATA_SEL enum */ TMDS_CTL2_DATA_SEL; /* * TMDS_CTL2_PATTERN_OUT_EN enum */ TMDS_CTL2_PATTERN_OUT_EN; /* * TMDS_CTL3_DATA_INVERT enum */ TMDS_CTL3_DATA_INVERT; /* * TMDS_CTL3_DATA_MODULATION enum */ TMDS_CTL3_DATA_MODULATION; /* * TMDS_CTL3_DATA_SEL enum */ TMDS_CTL3_DATA_SEL; /* * TMDS_CTL3_PATTERN_OUT_EN enum */ TMDS_CTL3_PATTERN_OUT_EN; /* * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum */ TMDS_DATA_SYNCHRONIZATION_DSINTSEL; /* * TMDS_PIXEL_ENCODING enum */ TMDS_PIXEL_ENCODING; /* * TMDS_REG_TEST_OUTPUTA_CNTLA enum */ TMDS_REG_TEST_OUTPUTA_CNTLA; /* * TMDS_REG_TEST_OUTPUTB_CNTLB enum */ TMDS_REG_TEST_OUTPUTB_CNTLB; /* * TMDS_STEREOSYNC_CTL_SEL_REG enum */ TMDS_STEREOSYNC_CTL_SEL_REG; /* * TMDS_SYNC_PHASE enum */ TMDS_SYNC_PHASE; /* * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum */ TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA; /* * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum */ TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB; /* * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum */ TMDS_TRANSMITTER_CONTROL_IDSCKSELA; /* * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum */ TMDS_TRANSMITTER_CONTROL_IDSCKSELB; /* * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum */ TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN; /* * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum */ TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK; /* * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum */ TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN; /* * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum */ TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK; /* * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum */ TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS; /* * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum */ TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS; /* * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum */ TMDS_TRANSMITTER_ENABLE_HPD_MASK; /* * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum */ TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK; /* * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum */ TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK; /******************************************************* * DP_AUX Enums *******************************************************/ /* * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum */ DP_AUX_ARB_CONTROL_ARB_PRIORITY; /* * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum */ DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG; /* * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum */ DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ; /* * DP_AUX_ARB_STATUS enum */ DP_AUX_ARB_STATUS; /* * DP_AUX_CONTROL_HPD_SEL enum */ DP_AUX_CONTROL_HPD_SEL; /* * DP_AUX_CONTROL_TEST_MODE enum */ DP_AUX_CONTROL_TEST_MODE; /* * DP_AUX_DEFINITE_ERR_REACHED_ACK enum */ DP_AUX_DEFINITE_ERR_REACHED_ACK; /* * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum */ DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; /* * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum */ DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START; /* * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum */ DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP; /* * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum */ DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN; /* * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum */ DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN; /* * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum */ DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW; /* * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum */ DP_AUX_DPHY_RX_CONTROL_START_WINDOW; /* * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum */ DP_AUX_DPHY_RX_DETECTION_THRESHOLD; /* * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum */ DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY; /* * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum */ DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE; /* * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum */ DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL; /* * DP_AUX_ERR_OCCURRED_ACK enum */ DP_AUX_ERR_OCCURRED_ACK; /* * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum */ DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ; /* * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum */ DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW; /* * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum */ DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT; /* * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum */ DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN; /* * DP_AUX_INT_ACK enum */ DP_AUX_INT_ACK; /* * DP_AUX_LS_UPDATE_ACK enum */ DP_AUX_LS_UPDATE_ACK; /* * DP_AUX_PHY_WAKE_PRIORITY enum */ DP_AUX_PHY_WAKE_PRIORITY; /* * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum */ DP_AUX_POTENTIAL_ERR_REACHED_ACK; /* * DP_AUX_RESET enum */ DP_AUX_RESET; /* * DP_AUX_RESET_DONE enum */ DP_AUX_RESET_DONE; /* * DP_AUX_RX_TIMEOUT_LEN_MUL enum */ DP_AUX_RX_TIMEOUT_LEN_MUL; /* * DP_AUX_SW_CONTROL_LS_READ_TRIG enum */ DP_AUX_SW_CONTROL_LS_READ_TRIG; /* * DP_AUX_SW_CONTROL_SW_GO enum */ DP_AUX_SW_CONTROL_SW_GO; /* * DP_AUX_TX_PRECHARGE_LEN_MUL enum */ DP_AUX_TX_PRECHARGE_LEN_MUL; /******************************************************* * DOUT_I2C Enums *******************************************************/ /* * DOUT_I2C_ACK enum */ DOUT_I2C_ACK; /* * DOUT_I2C_ARBITRATION_ABORT_XFER enum */ DOUT_I2C_ARBITRATION_ABORT_XFER; /* * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum */ DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG; /* * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum */ DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO; /* * DOUT_I2C_ARBITRATION_SW_PRIORITY enum */ DOUT_I2C_ARBITRATION_SW_PRIORITY; /* * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum */ DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ; /* * DOUT_I2C_CONTROL_DBG_REF_SEL enum */ DOUT_I2C_CONTROL_DBG_REF_SEL; /* * DOUT_I2C_CONTROL_DDC_SELECT enum */ DOUT_I2C_CONTROL_DDC_SELECT; /* * DOUT_I2C_CONTROL_GO enum */ DOUT_I2C_CONTROL_GO; /* * DOUT_I2C_CONTROL_SEND_RESET enum */ DOUT_I2C_CONTROL_SEND_RESET; /* * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum */ DOUT_I2C_CONTROL_SEND_RESET_LENGTH; /* * DOUT_I2C_CONTROL_SOFT_RESET enum */ DOUT_I2C_CONTROL_SOFT_RESET; /* * DOUT_I2C_CONTROL_SW_STATUS_RESET enum */ DOUT_I2C_CONTROL_SW_STATUS_RESET; /* * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum */ DOUT_I2C_CONTROL_TRANSACTION_COUNT; /* * DOUT_I2C_DATA_INDEX_WRITE enum */ DOUT_I2C_DATA_INDEX_WRITE; /* * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum */ DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN; /* * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum */ DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN; /* * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum */ DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL; /* * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum */ DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE; /* * DOUT_I2C_DDC_SPEED_THRESHOLD enum */ DOUT_I2C_DDC_SPEED_THRESHOLD; /* * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum */ DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET; /* * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum */ DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE; /* * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum */ DOUT_I2C_TRANSACTION_STOP_ON_NACK; /******************************************************* * DIO_MISC Enums *******************************************************/ /* * CLOCK_GATING_EN enum */ CLOCK_GATING_EN; /* * DAC_MUX_SELECT enum */ DAC_MUX_SELECT; /* * DIOMEM_PWR_DIS_CTRL enum */ DIOMEM_PWR_DIS_CTRL; /* * DIOMEM_PWR_FORCE_CTRL enum */ DIOMEM_PWR_FORCE_CTRL; /* * DIOMEM_PWR_FORCE_CTRL2 enum */ DIOMEM_PWR_FORCE_CTRL2; /* * DIOMEM_PWR_SEL_CTRL enum */ DIOMEM_PWR_SEL_CTRL; /* * DIOMEM_PWR_SEL_CTRL2 enum */ DIOMEM_PWR_SEL_CTRL2; /* * DIO_DBG_BLOCK_SEL enum */ DIO_DBG_BLOCK_SEL; /* * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum */ DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE; /* * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum */ DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE; /* * ENUM_DIO_DCN_ACTIVE_STATUS enum */ ENUM_DIO_DCN_ACTIVE_STATUS; /* * GENERIC_STEREOSYNC_SEL enum */ GENERIC_STEREOSYNC_SEL; /* * PM_ASSERT_RESET enum */ PM_ASSERT_RESET; /* * SOFT_RESET enum */ SOFT_RESET; /* * TMDS_MUX_SELECT enum */ TMDS_MUX_SELECT; /******************************************************* * DME Enums *******************************************************/ /* * DME_MEM_POWER_STATE_ENUM enum */ DME_MEM_POWER_STATE_ENUM; /* * DME_MEM_PWR_DIS_CTRL enum */ DME_MEM_PWR_DIS_CTRL; /* * DME_MEM_PWR_FORCE_CTRL enum */ DME_MEM_PWR_FORCE_CTRL; /* * METADATA_HUBP_SEL enum */ METADATA_HUBP_SEL; /* * METADATA_STREAM_TYPE_SEL enum */ METADATA_STREAM_TYPE_SEL; /******************************************************* * VPG Enums *******************************************************/ /* * VPG_MEM_PWR_DIS_CTRL enum */ VPG_MEM_PWR_DIS_CTRL; /* * VPG_MEM_PWR_FORCE_CTRL enum */ VPG_MEM_PWR_FORCE_CTRL; /******************************************************* * AFMT Enums *******************************************************/ /* * AFMT_ACP_TYPE enum */ AFMT_ACP_TYPE; /* * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum */ AFMT_AUDIO_CRC_CONTROL_CH_SEL; /* * AFMT_AUDIO_CRC_CONTROL_CONT enum */ AFMT_AUDIO_CRC_CONTROL_CONT; /* * AFMT_AUDIO_CRC_CONTROL_SOURCE enum */ AFMT_AUDIO_CRC_CONTROL_SOURCE; /* * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum */ AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD; /* * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum */ AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND; /* * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum */ AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS; /* * AFMT_AUDIO_SRC_CONTROL_SELECT enum */ AFMT_AUDIO_SRC_CONTROL_SELECT; /* * AFMT_HDMI_AUDIO_SEND_MAX_PACKETS enum */ AFMT_HDMI_AUDIO_SEND_MAX_PACKETS; /* * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum */ AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE; /* * AFMT_INTERRUPT_STATUS_CHG_MASK enum */ AFMT_INTERRUPT_STATUS_CHG_MASK; /* * AFMT_MEM_PWR_DIS_CTRL enum */ AFMT_MEM_PWR_DIS_CTRL; /* * AFMT_MEM_PWR_FORCE_CTRL enum */ AFMT_MEM_PWR_FORCE_CTRL; /* * AFMT_RAMP_CONTROL0_SIGN enum */ AFMT_RAMP_CONTROL0_SIGN; /* * AFMT_VBI_PACKET_CONTROL_ACP_SOURCE enum */ AFMT_VBI_PACKET_CONTROL_ACP_SOURCE; /* * AUDIO_LAYOUT_SELECT enum */ AUDIO_LAYOUT_SELECT; /******************************************************* * HPO_TOP Enums *******************************************************/ /* * HPO_TOP_CLOCK_GATING_DISABLE enum */ HPO_TOP_CLOCK_GATING_DISABLE; /* * HPO_TOP_TEST_CLK_SEL enum */ HPO_TOP_TEST_CLK_SEL; /******************************************************* * DP_STREAM_MAPPER Enums *******************************************************/ /* * DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET enum */ DP_STREAM_MAPPER_DP_STREAM_LINK_TARGET; /******************************************************* * HDMI_STREAM_ENC Enums *******************************************************/ /* * HDMI_STREAM_ENC_DB_DISABLE_CONTROL enum */ HDMI_STREAM_ENC_DB_DISABLE_CONTROL; /* * HDMI_STREAM_ENC_DSC_MODE enum */ HDMI_STREAM_ENC_DSC_MODE; /* * HDMI_STREAM_ENC_ENABLE_CONTROL enum */ HDMI_STREAM_ENC_ENABLE_CONTROL; /* * HDMI_STREAM_ENC_ODM_COMBINE_MODE enum */ HDMI_STREAM_ENC_ODM_COMBINE_MODE; /* * HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum */ HDMI_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR; /* * HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum */ HDMI_STREAM_ENC_OVERWRITE_LEVEL_SELECT; /* * HDMI_STREAM_ENC_PIXEL_ENCODING enum */ HDMI_STREAM_ENC_PIXEL_ENCODING; /* * HDMI_STREAM_ENC_READ_CLOCK_CONTROL enum */ HDMI_STREAM_ENC_READ_CLOCK_CONTROL; /* * HDMI_STREAM_ENC_RESET_CONTROL enum */ HDMI_STREAM_ENC_RESET_CONTROL; /* * HDMI_STREAM_ENC_STREAM_ACTIVE enum */ HDMI_STREAM_ENC_STREAM_ACTIVE; /******************************************************* * HDMI_TB_ENC Enums *******************************************************/ /* * BORROWBUFFER_MEM_POWER_STATE_ENUM enum */ BORROWBUFFER_MEM_POWER_STATE_ENUM; /* * HDMI_BORROW_MODE enum */ HDMI_BORROW_MODE; /* * HDMI_TB_ENC_ACP_SEND enum */ HDMI_TB_ENC_ACP_SEND; /* * HDMI_TB_ENC_ACR_AUDIO_PRIORITY enum */ HDMI_TB_ENC_ACR_AUDIO_PRIORITY; /* * HDMI_TB_ENC_ACR_CONT enum */ HDMI_TB_ENC_ACR_CONT; /* * HDMI_TB_ENC_ACR_N_MULTIPLE enum */ HDMI_TB_ENC_ACR_N_MULTIPLE; /* * HDMI_TB_ENC_ACR_SELECT enum */ HDMI_TB_ENC_ACR_SELECT; /* * HDMI_TB_ENC_ACR_SEND enum */ HDMI_TB_ENC_ACR_SEND; /* * HDMI_TB_ENC_ACR_SOURCE enum */ HDMI_TB_ENC_ACR_SOURCE; /* * HDMI_TB_ENC_AUDIO_INFO_CONT enum */ HDMI_TB_ENC_AUDIO_INFO_CONT; /* * HDMI_TB_ENC_AUDIO_INFO_SEND enum */ HDMI_TB_ENC_AUDIO_INFO_SEND; /* * HDMI_TB_ENC_CRC_SRC_SEL enum */ HDMI_TB_ENC_CRC_SRC_SEL; /* * HDMI_TB_ENC_CRC_TYPE enum */ HDMI_TB_ENC_CRC_TYPE; /* * HDMI_TB_ENC_DEEP_COLOR_DEPTH enum */ HDMI_TB_ENC_DEEP_COLOR_DEPTH; /* * HDMI_TB_ENC_DEFAULT_PAHSE enum */ HDMI_TB_ENC_DEFAULT_PAHSE; /* * HDMI_TB_ENC_DSC_MODE enum */ HDMI_TB_ENC_DSC_MODE; /* * HDMI_TB_ENC_ENABLE enum */ HDMI_TB_ENC_ENABLE; /* * HDMI_TB_ENC_GC_AVMUTE enum */ HDMI_TB_ENC_GC_AVMUTE; /* * HDMI_TB_ENC_GC_AVMUTE_CONT enum */ HDMI_TB_ENC_GC_AVMUTE_CONT; /* * HDMI_TB_ENC_GC_CONT enum */ HDMI_TB_ENC_GC_CONT; /* * HDMI_TB_ENC_GC_SEND enum */ HDMI_TB_ENC_GC_SEND; /* * HDMI_TB_ENC_GENERIC_CONT enum */ HDMI_TB_ENC_GENERIC_CONT; /* * HDMI_TB_ENC_GENERIC_LOCK_EN enum */ HDMI_TB_ENC_GENERIC_LOCK_EN; /* * HDMI_TB_ENC_GENERIC_SEND enum */ HDMI_TB_ENC_GENERIC_SEND; /* * HDMI_TB_ENC_ISRC_CONT enum */ HDMI_TB_ENC_ISRC_CONT; /* * HDMI_TB_ENC_ISRC_SEND enum */ HDMI_TB_ENC_ISRC_SEND; /* * HDMI_TB_ENC_METADATA_ENABLE enum */ HDMI_TB_ENC_METADATA_ENABLE; /* * HDMI_TB_ENC_PACKET_LINE_REFERENCE enum */ HDMI_TB_ENC_PACKET_LINE_REFERENCE; /* * HDMI_TB_ENC_PIXEL_ENCODING enum */ HDMI_TB_ENC_PIXEL_ENCODING; /* * HDMI_TB_ENC_RESET enum */ HDMI_TB_ENC_RESET; /* * HDMI_TB_ENC_SYNC_PHASE enum */ HDMI_TB_ENC_SYNC_PHASE; /* * INPUT_FIFO_ERROR_TYPE enum */ INPUT_FIFO_ERROR_TYPE; /******************************************************* * DP_STREAM_ENC Enums *******************************************************/ /* * DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR enum */ DP_STREAM_ENC_OVERFLOW_UNDERFLOW_ERROR; /* * DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT enum */ DP_STREAM_ENC_OVERWRITE_LEVEL_SELECT; /* * DP_STREAM_ENC_READ_CLOCK_CONTROL enum */ DP_STREAM_ENC_READ_CLOCK_CONTROL; /* * DP_STREAM_ENC_RESET_CONTROL enum */ DP_STREAM_ENC_RESET_CONTROL; /* * DP_STREAM_ENC_STREAM_ACTIVE enum */ DP_STREAM_ENC_STREAM_ACTIVE; /******************************************************* * DP_SYM32_ENC Enums *******************************************************/ /* * ENUM_DP_SYM32_ENC_AUDIO_MUTE enum */ ENUM_DP_SYM32_ENC_AUDIO_MUTE; /* * ENUM_DP_SYM32_ENC_CONTINUOUS_MODE enum */ ENUM_DP_SYM32_ENC_CONTINUOUS_MODE; /* * ENUM_DP_SYM32_ENC_CRC_VALID enum */ ENUM_DP_SYM32_ENC_CRC_VALID; /* * ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH enum */ ENUM_DP_SYM32_ENC_DP_COMPONENT_DEPTH; /* * ENUM_DP_SYM32_ENC_ENABLE enum */ ENUM_DP_SYM32_ENC_ENABLE; /* * ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED enum */ ENUM_DP_SYM32_ENC_GSP_DEADLINE_MISSED; /* * ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION enum */ ENUM_DP_SYM32_ENC_GSP_ONE_SHOT_TRIGGER_POSITION; /* * ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE enum */ ENUM_DP_SYM32_ENC_GSP_PAYLOAD_SIZE; /* * ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING enum */ ENUM_DP_SYM32_ENC_GSP_TRIGGER_PENDING; /* * ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM enum */ ENUM_DP_SYM32_ENC_MEM_PWR_FORCE_ENUM; /* * ENUM_DP_SYM32_ENC_OVERFLOW_STATUS enum */ ENUM_DP_SYM32_ENC_OVERFLOW_STATUS; /* * ENUM_DP_SYM32_ENC_PENDING enum */ ENUM_DP_SYM32_ENC_PENDING; /* * ENUM_DP_SYM32_ENC_PIXEL_ENCODING enum */ ENUM_DP_SYM32_ENC_PIXEL_ENCODING; /* * ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE enum */ ENUM_DP_SYM32_ENC_PIXEL_ENCODING_TYPE; /* * ENUM_DP_SYM32_ENC_POWER_STATE_ENUM enum */ ENUM_DP_SYM32_ENC_POWER_STATE_ENUM; /* * ENUM_DP_SYM32_ENC_RESET enum */ ENUM_DP_SYM32_ENC_RESET; /* * ENUM_DP_SYM32_ENC_SDP_PRIORITY enum */ ENUM_DP_SYM32_ENC_SDP_PRIORITY; /* * ENUM_DP_SYM32_ENC_SOF_REFERENCE enum */ ENUM_DP_SYM32_ENC_SOF_REFERENCE; /* * ENUM_DP_SYM32_ENC_VID_STREAM_DEFER enum */ ENUM_DP_SYM32_ENC_VID_STREAM_DEFER; /******************************************************* * DP_DPHY_SYM32 Enums *******************************************************/ /* * ENUM_DP_DPHY_SYM32_CRC_END_EVENT enum */ ENUM_DP_DPHY_SYM32_CRC_END_EVENT; /* * ENUM_DP_DPHY_SYM32_CRC_START_EVENT enum */ ENUM_DP_DPHY_SYM32_CRC_START_EVENT; /* * ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE enum */ ENUM_DP_DPHY_SYM32_CRC_TAP_SOURCE; /* * ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS enum */ ENUM_DP_DPHY_SYM32_CRC_USE_NUM_SYMBOLS; /* * ENUM_DP_DPHY_SYM32_ENABLE enum */ ENUM_DP_DPHY_SYM32_ENABLE; /* * ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE enum */ ENUM_DP_DPHY_SYM32_ENCRYPT_TYPE; /* * ENUM_DP_DPHY_SYM32_MODE enum */ ENUM_DP_DPHY_SYM32_MODE; /* * ENUM_DP_DPHY_SYM32_NUM_LANES enum */ ENUM_DP_DPHY_SYM32_NUM_LANES; /* * ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING enum */ ENUM_DP_DPHY_SYM32_RATE_UPDATE_PENDING; /* * ENUM_DP_DPHY_SYM32_RESET enum */ ENUM_DP_DPHY_SYM32_RESET; /* * ENUM_DP_DPHY_SYM32_RESET_STATUS enum */ ENUM_DP_DPHY_SYM32_RESET_STATUS; /* * ENUM_DP_DPHY_SYM32_SAT_UPDATE enum */ ENUM_DP_DPHY_SYM32_SAT_UPDATE; /* * ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING enum */ ENUM_DP_DPHY_SYM32_SAT_UPDATE_PENDING; /* * ENUM_DP_DPHY_SYM32_STATUS enum */ ENUM_DP_DPHY_SYM32_STATUS; /* * ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE enum */ ENUM_DP_DPHY_SYM32_STREAM_OVR_ENABLE; /* * ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE enum */ ENUM_DP_DPHY_SYM32_STREAM_OVR_TYPE; /* * ENUM_DP_DPHY_SYM32_TP_PRBS_SEL enum */ ENUM_DP_DPHY_SYM32_TP_PRBS_SEL; /* * ENUM_DP_DPHY_SYM32_TP_SELECT enum */ ENUM_DP_DPHY_SYM32_TP_SELECT; /******************************************************* * APG Enums *******************************************************/ /* * APG_AUDIO_CRC_CONTROL_CH_SEL enum */ APG_AUDIO_CRC_CONTROL_CH_SEL; /* * APG_AUDIO_CRC_CONTROL_CONT enum */ APG_AUDIO_CRC_CONTROL_CONT; /* * APG_DBG_ACP_TYPE enum */ APG_DBG_ACP_TYPE; /* * APG_DBG_AUDIO_DTO_BASE enum */ APG_DBG_AUDIO_DTO_BASE; /* * APG_DBG_AUDIO_DTO_DIV enum */ APG_DBG_AUDIO_DTO_DIV; /* * APG_DBG_AUDIO_DTO_MULTI enum */ APG_DBG_AUDIO_DTO_MULTI; /* * APG_DBG_MUX_SEL enum */ APG_DBG_MUX_SEL; /* * APG_DP_ASP_CHANNEL_COUNT_OVERRIDE enum */ APG_DP_ASP_CHANNEL_COUNT_OVERRIDE; /* * APG_MEM_POWER_STATE enum */ APG_MEM_POWER_STATE; /* * APG_MEM_PWR_DIS_CTRL enum */ APG_MEM_PWR_DIS_CTRL; /* * APG_MEM_PWR_FORCE_CTRL enum */ APG_MEM_PWR_FORCE_CTRL; /* * APG_PACKET_CONTROL_ACP_SOURCE enum */ APG_PACKET_CONTROL_ACP_SOURCE; /* * APG_PACKET_CONTROL_AUDIO_INFO_SOURCE enum */ APG_PACKET_CONTROL_AUDIO_INFO_SOURCE; /* * APG_RAMP_CONTROL_SIGN enum */ APG_RAMP_CONTROL_SIGN; /******************************************************* * DCIO Enums *******************************************************/ /* * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum */ DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL; /* * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum */ DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL; /* * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum */ DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS; /* * DCIO_DBG_ASYNC_4BIT_SEL enum */ DCIO_DBG_ASYNC_4BIT_SEL; /* * DCIO_DBG_ASYNC_BLOCK_SEL enum */ DCIO_DBG_ASYNC_BLOCK_SEL; /* * DCIO_DCRXPHY_SOFT_RESET enum */ DCIO_DCRXPHY_SOFT_RESET; /* * DCIO_DC_GENERICA_SEL enum */ DCIO_DC_GENERICA_SEL; /* * DCIO_DC_GENERICB_SEL enum */ DCIO_DC_GENERICB_SEL; /* * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum */ DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL; /* * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum */ DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL; /* * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum */ DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL; /* * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum */ DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL; /* * DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE enum */ DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE; /* * DCIO_DC_GPU_TIMER_READ_SELECT enum */ DCIO_DC_GPU_TIMER_READ_SELECT; /* * DCIO_DC_GPU_TIMER_START_POSITION enum */ DCIO_DC_GPU_TIMER_START_POSITION; /* * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum */ DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL; /* * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum */ DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL; /* * DCIO_DIO_EXT_VSYNC_MASK enum */ DCIO_DIO_EXT_VSYNC_MASK; /* * DCIO_DIO_OTG_EXT_VSYNC_MUX enum */ DCIO_DIO_OTG_EXT_VSYNC_MUX; /* * DCIO_DPCS_INTERRUPT_MASK enum */ DCIO_DPCS_INTERRUPT_MASK; /* * DCIO_DPCS_INTERRUPT_TYPE enum */ DCIO_DPCS_INTERRUPT_TYPE; /* * DCIO_DSYNC_SOFT_RESET enum */ DCIO_DSYNC_SOFT_RESET; /* * DCIO_GENLK_CLK_GSL_MASK enum */ DCIO_GENLK_CLK_GSL_MASK; /* * DCIO_GENLK_VSYNC_GSL_MASK enum */ DCIO_GENLK_VSYNC_GSL_MASK; /* * DCIO_GSL_SEL enum */ DCIO_GSL_SEL; /* * DCIO_PHY_HPO_ENC_SRC_SEL enum */ DCIO_PHY_HPO_ENC_SRC_SEL; /* * DCIO_SWAPLOCK_A_GSL_MASK enum */ DCIO_SWAPLOCK_A_GSL_MASK; /* * DCIO_SWAPLOCK_B_GSL_MASK enum */ DCIO_SWAPLOCK_B_GSL_MASK; /* * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum */ DCIO_UNIPHY_CHANNEL_XBAR_SOURCE; /* * DCIO_UNIPHY_IMPCAL_SEL enum */ DCIO_UNIPHY_IMPCAL_SEL; /* * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum */ DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT; /* * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum */ DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK; /******************************************************* * DCIO_CHIP Enums *******************************************************/ /* * DCIOCHIP_AUX_ALL_PWR_OK enum */ DCIOCHIP_AUX_ALL_PWR_OK; /* * DCIOCHIP_AUX_CSEL0P9 enum */ DCIOCHIP_AUX_CSEL0P9; /* * DCIOCHIP_AUX_CSEL1P1 enum */ DCIOCHIP_AUX_CSEL1P1; /* * DCIOCHIP_AUX_FALLSLEWSEL enum */ DCIOCHIP_AUX_FALLSLEWSEL; /* * DCIOCHIP_AUX_HYS_TUNE enum */ DCIOCHIP_AUX_HYS_TUNE; /* * DCIOCHIP_AUX_RECEIVER_SEL enum */ DCIOCHIP_AUX_RECEIVER_SEL; /* * DCIOCHIP_AUX_RSEL0P9 enum */ DCIOCHIP_AUX_RSEL0P9; /* * DCIOCHIP_AUX_RSEL1P1 enum */ DCIOCHIP_AUX_RSEL1P1; /* * DCIOCHIP_AUX_SPIKESEL enum */ DCIOCHIP_AUX_SPIKESEL; /* * DCIOCHIP_AUX_VOD_TUNE enum */ DCIOCHIP_AUX_VOD_TUNE; /* * DCIOCHIP_GPIO_MASK_EN enum */ DCIOCHIP_GPIO_MASK_EN; /* * DCIOCHIP_HPD_SEL enum */ DCIOCHIP_HPD_SEL; /* * DCIOCHIP_I2C_COMPSEL enum */ DCIOCHIP_I2C_COMPSEL; /* * DCIOCHIP_I2C_FALLSLEWSEL enum */ DCIOCHIP_I2C_FALLSLEWSEL; /* * DCIOCHIP_I2C_RECEIVER_SEL enum */ DCIOCHIP_I2C_RECEIVER_SEL; /* * DCIOCHIP_I2C_VPH_1V2_EN enum */ DCIOCHIP_I2C_VPH_1V2_EN; /* * DCIOCHIP_INVERT enum */ DCIOCHIP_INVERT; /* * DCIOCHIP_MASK enum */ DCIOCHIP_MASK; /* * DCIOCHIP_PAD_MODE enum */ DCIOCHIP_PAD_MODE; /* * DCIOCHIP_PD_EN enum */ DCIOCHIP_PD_EN; /* * DCIOCHIP_REF_27_SRC_SEL enum */ DCIOCHIP_REF_27_SRC_SEL; /******************************************************* * PWRSEQ Enums *******************************************************/ /* * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum */ PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE; /* * PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN enum */ PWRSEQ_BL_PWM_CNTL2_BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN; /* * PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT enum */ PWRSEQ_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT; /* * PWRSEQ_BL_PWM_CNTL_BL_PWM_EN enum */ PWRSEQ_BL_PWM_CNTL_BL_PWM_EN; /* * PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum */ PWRSEQ_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN; /* * PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum */ PWRSEQ_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; /* * PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum */ PWRSEQ_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN; /* * PWRSEQ_BL_PWM_GRP1_REG_LOCK enum */ PWRSEQ_BL_PWM_GRP1_REG_LOCK; /* * PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum */ PWRSEQ_BL_PWM_GRP1_UPDATE_AT_FRAME_START; /* * PWRSEQ_GPIO_MASK_EN enum */ PWRSEQ_GPIO_MASK_EN; /* * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON enum */ PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON; /* * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL enum */ PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_BLON_POL; /* * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON enum */ PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON; /* * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL enum */ PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_DIGON_POL; /* * PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL enum */ PWRSEQ_PANEL_PWRSEQ_CNTL_PANEL_SYNCEN_POL; /* * PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE enum */ PWRSEQ_PANEL_PWRSEQ_CNTL_TARGET_STATE; /* * PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN enum */ PWRSEQ_PANEL_PWRSEQ_DELAY2_PANEL_VARY_BL_OVERRIDE_EN; /******************************************************* * AZCONTROLLER Enums *******************************************************/ /* * AZ_CORB_SIZE enum */ AZ_CORB_SIZE; /* * AZ_GLOBAL_CAPABILITIES enum */ AZ_GLOBAL_CAPABILITIES; /* * AZ_RIRB_SIZE enum */ AZ_RIRB_SIZE; /* * AZ_RIRB_WRITE_POINTER_RESET enum */ AZ_RIRB_WRITE_POINTER_RESET; /* * AZ_STATE_CHANGE_STATUS enum */ AZ_STATE_CHANGE_STATUS; /* * CORB_READ_POINTER_RESET enum */ CORB_READ_POINTER_RESET; /* * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum */ DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE; /* * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum */ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL; /* * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum */ GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED; /* * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum */ GENERIC_AZ_CONTROLLER_REGISTER_STATUS; /* * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum */ GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED; /* * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum */ GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE; /* * GLOBAL_CONTROL_CONTROLLER_RESET enum */ GLOBAL_CONTROL_CONTROLLER_RESET; /* * GLOBAL_CONTROL_FLUSH_CONTROL enum */ GLOBAL_CONTROL_FLUSH_CONTROL; /* * GLOBAL_STATUS_FLUSH_STATUS enum */ GLOBAL_STATUS_FLUSH_STATUS; /* * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum */ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY; /* * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum */ IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID; /* * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum */ RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL; /* * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum */ RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL; /* * STREAM_0_SYNCHRONIZATION enum */ STREAM_0_SYNCHRONIZATION; /* * STREAM_10_SYNCHRONIZATION enum */ STREAM_10_SYNCHRONIZATION; /* * STREAM_11_SYNCHRONIZATION enum */ STREAM_11_SYNCHRONIZATION; /* * STREAM_12_SYNCHRONIZATION enum */ STREAM_12_SYNCHRONIZATION; /* * STREAM_13_SYNCHRONIZATION enum */ STREAM_13_SYNCHRONIZATION; /* * STREAM_14_SYNCHRONIZATION enum */ STREAM_14_SYNCHRONIZATION; /* * STREAM_15_SYNCHRONIZATION enum */ STREAM_15_SYNCHRONIZATION; /* * STREAM_1_SYNCHRONIZATION enum */ STREAM_1_SYNCHRONIZATION; /* * STREAM_2_SYNCHRONIZATION enum */ STREAM_2_SYNCHRONIZATION; /* * STREAM_3_SYNCHRONIZATION enum */ STREAM_3_SYNCHRONIZATION; /* * STREAM_4_SYNCHRONIZATION enum */ STREAM_4_SYNCHRONIZATION; /* * STREAM_5_SYNCHRONIZATION enum */ STREAM_5_SYNCHRONIZATION; /* * STREAM_6_SYNCHRONIZATION enum */ STREAM_6_SYNCHRONIZATION; /* * STREAM_7_SYNCHRONIZATION enum */ STREAM_7_SYNCHRONIZATION; /* * STREAM_8_SYNCHRONIZATION enum */ STREAM_8_SYNCHRONIZATION; /* * STREAM_9_SYNCHRONIZATION enum */ STREAM_9_SYNCHRONIZATION; /******************************************************* * AZENDPOINT Enums *******************************************************/ /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V; /* * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum */ AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG; /* * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum */ AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE; /* * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum */ AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; /* * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum */ AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; /* * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum */ AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; /* * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum */ AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE; /******************************************************* * AZF0CONTROLLER Enums *******************************************************/ /* * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum */ AZALIA_SOFT_RESET_REFCLK_SOFT_RESET; /* * MEM_PWR_DIS_CTRL enum */ MEM_PWR_DIS_CTRL; /* * MEM_PWR_FORCE_CTRL enum */ MEM_PWR_FORCE_CTRL; /* * MEM_PWR_FORCE_CTRL2 enum */ MEM_PWR_FORCE_CTRL2; /* * MEM_PWR_SEL_CTRL enum */ MEM_PWR_SEL_CTRL; /* * MEM_PWR_SEL_CTRL2 enum */ MEM_PWR_SEL_CTRL2; /******************************************************* * AZF0ROOT Enums *******************************************************/ /* * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum */ CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY; /* * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum */ CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY; /******************************************************* * AZINPUTENDPOINT Enums *******************************************************/ /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE; /* * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum */ AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE; /* * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum */ AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE; /******************************************************* * AZROOT Enums *******************************************************/ /* * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum */ AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET; /******************************************************* * AZF0STREAM Enums *******************************************************/ /* * AZ_LATENCY_COUNTER_CONTROL enum */ AZ_LATENCY_COUNTER_CONTROL; /******************************************************* * AZSTREAM Enums *******************************************************/ /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN; /* * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum */ OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE; /* * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum */ OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE; /******************************************************* * AZF0ENDPOINT Enums *******************************************************/ /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum */ AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE; /* * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum */ AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; /* * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum */ AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; /******************************************************* * AZF0INPUTENDPOINT Enums *******************************************************/ /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE; /* * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum */ AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED; /******************************************************* * DSCC Enums *******************************************************/ /* * DSCC_BITS_PER_COMPONENT_ENUM enum */ DSCC_BITS_PER_COMPONENT_ENUM; /* * DSCC_DSC_VERSION_MAJOR_ENUM enum */ DSCC_DSC_VERSION_MAJOR_ENUM; /* * DSCC_DSC_VERSION_MINOR_ENUM enum */ DSCC_DSC_VERSION_MINOR_ENUM; /* * DSCC_ENABLE_ENUM enum */ DSCC_ENABLE_ENUM; /* * DSCC_ICH_RESET_ENUM enum */ DSCC_ICH_RESET_ENUM; /* * DSCC_LINEBUF_DEPTH_ENUM enum */ DSCC_LINEBUF_DEPTH_ENUM; /* * DSCC_MEM_PWR_DIS_ENUM enum */ DSCC_MEM_PWR_DIS_ENUM; /* * DSCC_MEM_PWR_FORCE_ENUM enum */ DSCC_MEM_PWR_FORCE_ENUM; /* * POWER_STATE_ENUM enum */ POWER_STATE_ENUM; /******************************************************* * DSCCIF Enums *******************************************************/ /* * DSCCIF_BITS_PER_COMPONENT_ENUM enum */ DSCCIF_BITS_PER_COMPONENT_ENUM; /* * DSCCIF_ENABLE_ENUM enum */ DSCCIF_ENABLE_ENUM; /* * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum */ DSCCIF_INPUT_PIXEL_FORMAT_ENUM; /******************************************************* * DSC_TOP Enums *******************************************************/ /* * CLOCK_GATING_DISABLE_ENUM enum */ CLOCK_GATING_DISABLE_ENUM; /* * ENABLE_ENUM enum */ ENABLE_ENUM; /* * TEST_CLOCK_MUX_SELECT_ENUM enum */ TEST_CLOCK_MUX_SELECT_ENUM; /******************************************************* * DWB_TOP Enums *******************************************************/ /* * DWB_CRC_CONT_EN_ENUM enum */ DWB_CRC_CONT_EN_ENUM; /* * DWB_CRC_SRC_SEL_ENUM enum */ DWB_CRC_SRC_SEL_ENUM; /* * DWB_DATA_OVERFLOW_INT_TYPE_ENUM enum */ DWB_DATA_OVERFLOW_INT_TYPE_ENUM; /* * DWB_DATA_OVERFLOW_TYPE_ENUM enum */ DWB_DATA_OVERFLOW_TYPE_ENUM; /* * DWB_DEBUG_SEL_ENUM enum */ DWB_DEBUG_SEL_ENUM; /* * DWB_MEM_PWR_FORCE_ENUM enum */ DWB_MEM_PWR_FORCE_ENUM; /* * DWB_MEM_PWR_STATE_ENUM enum */ DWB_MEM_PWR_STATE_ENUM; /* * DWB_TEST_CLK_SEL_ENUM enum */ DWB_TEST_CLK_SEL_ENUM; /* * FC_EYE_SELECTION_ENUM enum */ FC_EYE_SELECTION_ENUM; /* * FC_FRAME_CAPTURE_RATE_ENUM enum */ FC_FRAME_CAPTURE_RATE_ENUM; /* * FC_STEREO_EYE_POLARITY_ENUM enum */ FC_STEREO_EYE_POLARITY_ENUM; /******************************************************* * DWBCP Enums *******************************************************/ /* * DWB_GAMUT_REMAP_COEF_FORMAT_ENUM enum */ DWB_GAMUT_REMAP_COEF_FORMAT_ENUM; /* * DWB_GAMUT_REMAP_MODE_ENUM enum */ DWB_GAMUT_REMAP_MODE_ENUM; /* * DWB_LUT_NUM_SEG enum */ DWB_LUT_NUM_SEG; /* * DWB_OGAM_LUT_CONFIG_MODE_ENUM enum */ DWB_OGAM_LUT_CONFIG_MODE_ENUM; /* * DWB_OGAM_LUT_HOST_SEL_ENUM enum */ DWB_OGAM_LUT_HOST_SEL_ENUM; /* * DWB_OGAM_LUT_READ_COLOR_SEL_ENUM enum */ DWB_OGAM_LUT_READ_COLOR_SEL_ENUM; /* * DWB_OGAM_LUT_READ_DBG_ENUM enum */ DWB_OGAM_LUT_READ_DBG_ENUM; /* * DWB_OGAM_MODE_ENUM enum */ DWB_OGAM_MODE_ENUM; /* * DWB_OGAM_PWL_DISABLE_ENUM enum */ DWB_OGAM_PWL_DISABLE_ENUM; /* * DWB_OGAM_SELECT_ENUM enum */ DWB_OGAM_SELECT_ENUM; /******************************************************* * RDPCSPIPE Enums *******************************************************/ /* * RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN enum */ RDPCSPIPE_CLOCK_CNTL_LANE_CLK_EN; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_APBCLK_EN; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_CLOCK_ON; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_EN; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_CLK_GATE_DIS; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_PIPE_PHYD32CLK_CLOCK_ON; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_EN; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS; /* * RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS enum */ RDPCSPIPE_CLOCK_CNTL_RDPCS_SRAMCLK_PASS; /* * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN enum */ RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_EN; /* * RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN enum */ RDPCSPIPE_CNTL_RDPCS_PIPE_FIFO_LANE_EN; /* * RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET enum */ RDPCSPIPE_CNTL_RDPCS_PIPE_SOFT_RESET; /* * RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET enum */ RDPCSPIPE_CNTL_RDPCS_SRAM_SOFT_RESET; /* * RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK enum */ RDPCSPIPE_DBG_APB_COUNT_EXPIRE_MASK; /* * RDPCSPIPE_DBG_OCLA_SEL enum */ RDPCSPIPE_DBG_OCLA_SEL; /* * RDPCSPIPE_ENC_TYPE enum */ RDPCSPIPE_ENC_TYPE; /* * RDPCSPIPE_FIFO_EMPTY enum */ RDPCSPIPE_FIFO_EMPTY; /* * RDPCSPIPE_FIFO_FULL enum */ RDPCSPIPE_FIFO_FULL; /* * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK enum */ RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_APB_PSLVERR_MASK; /* * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum */ RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE; /* * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum */ RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK; /* * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum */ RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE; /* * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum */ RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK; /* * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK enum */ RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_PIPE_FIFO_ERROR_MASK; /* * RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum */ RDPCSPIPE_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK; /* * RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK enum */ RDPCSPIPE_MSG_BUS_COUNT_EXPIRE_MASK; /* * RDPCSPIPE_PACK_MODE enum */ RDPCSPIPE_PACK_MODE; /* * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum */ RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL; /* * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum */ RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL; /* * RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum */ RDPCSPIPE_PHY_CNTL0_RDPCS_PHY_REF_RANGE; /* * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum */ RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE; /* * RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum */ RDPCSPIPE_PHY_CNTL0_RDPCS_SRAM_INIT_DONE; /* * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum */ RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV; /* * RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum */ RDPCSPIPE_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV; /* * RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum */ RDPCSPIPE_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV; /* * RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum */ RDPCSPIPE_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL; /* * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum */ RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT; /* * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum */ RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_RATE; /* * RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum */ RDPCSPIPE_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH; /* * RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum */ RDPCSPIPE_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE; /* * RDPCSPIPE_PHY_IF_WIDTH enum */ RDPCSPIPE_PHY_IF_WIDTH; /* * RDPCSPIPE_PHY_RATE enum */ RDPCSPIPE_PHY_RATE; /* * RDPCSPIPE_PHY_REF_ALT_CLK_EN enum */ RDPCSPIPE_PHY_REF_ALT_CLK_EN; /* * RDPCSPIPE_TEST_CLK_SEL enum */ RDPCSPIPE_TEST_CLK_SEL; /* * RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB enum */ RDPCS_PIPE_CNTL_TX_LANE_PACK_FROM_MSB; /* * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum */ RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_FORCE; /* * RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum */ RDPCS_PIPE_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE; /* * RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK enum */ RPDCSPIPE_CNTL_TX_LANE_BIT_ORDER_REVERSE_BEFORE_PACK; /******************************************************* * GDS Enums *******************************************************/ /* * GDS_PERFCOUNT_SELECT enum */ GDS_PERFCOUNT_SELECT; /******************************************************* * CB Enums *******************************************************/ /* * BlendOp enum */ BlendOp; /* * BlendOpt enum */ BlendOpt; /* * CBMode enum */ CBMode; /* * CBPerfClearFilterSel enum */ CBPerfClearFilterSel; /* * CBPerfOpFilterSel enum */ CBPerfOpFilterSel; /* * CBPerfSel enum */ CBPerfSel; /* * CBRamList enum */ CBRamList; /* * CmaskCode enum */ CmaskCode; /* * CombFunc enum */ CombFunc; /* * MemArbMode enum */ MemArbMode; /* * SourceFormat enum */ SourceFormat; /******************************************************* * SC Enums *******************************************************/ /* * BinEventCntl enum */ BinEventCntl; /* * BinMapMode enum */ BinMapMode; /* * BinSizeExtend enum */ BinSizeExtend; /* * BinningMode enum */ BinningMode; /* * CovToShaderSel enum */ CovToShaderSel; /* * PkrMap enum */ PkrMap; /* * PkrXsel enum */ PkrXsel; /* * PkrXsel2 enum */ PkrXsel2; /* * PkrYsel enum */ PkrYsel; /* * RbMap enum */ RbMap; /* * RbXsel enum */ RbXsel; /* * RbXsel2 enum */ RbXsel2; /* * RbYsel enum */ RbYsel; /* * SC_PERFCNT_SEL enum */ SC_PERFCNT_SEL; /* * ScMap enum */ ScMap; /* * ScUncertaintyRegionMode enum */ ScUncertaintyRegionMode; /* * ScUncertaintyRegionMult enum */ ScUncertaintyRegionMult; /* * ScXsel enum */ ScXsel; /* * ScYsel enum */ ScYsel; /* * SeMap enum */ SeMap; /* * SePairMap enum */ SePairMap; /* * SePairXsel enum */ SePairXsel; /* * SePairYsel enum */ SePairYsel; /* * SeXsel enum */ SeXsel; /* * SeYsel enum */ SeYsel; /* * VRSCombinerModeSC enum */ VRSCombinerModeSC; /* * VRSrate enum */ VRSrate; /******************************************************* * TC Enums *******************************************************/ /* * TC_EA_CID enum */ TC_EA_CID; /* * TC_NACKS enum */ TC_NACKS; /* * TC_OP enum */ TC_OP; /* * TC_OP_MASKS enum */ TC_OP_MASKS; /******************************************************* * GL2 Enums *******************************************************/ /* * GL2_EA_CID enum */ GL2_EA_CID; /* * GL2_NACKS enum */ GL2_NACKS; /* * GL2_OP enum */ GL2_OP; /* * GL2_OP_MASKS enum */ GL2_OP_MASKS; /******************************************************* * RLC Enums *******************************************************/ /* * RLC_DOORBELL_MODE enum */ RLC_DOORBELL_MODE; /* * RLC_PERFCOUNTER_SEL enum */ RLC_PERFCOUNTER_SEL; /* * RLC_PERFMON_STATE enum */ RLC_PERFMON_STATE; /* * RSPM_CMD enum */ RSPM_CMD; /******************************************************* * SPI Enums *******************************************************/ /* * CLKGATE_BASE_MODE enum */ CLKGATE_BASE_MODE; /* * CLKGATE_SM_MODE enum */ CLKGATE_SM_MODE; /* * SPI_FOG_MODE enum */ SPI_FOG_MODE; /* * SPI_LB_WAVES_SELECT enum */ SPI_LB_WAVES_SELECT; /* * SPI_PERFCNT_SEL enum */ SPI_PERFCNT_SEL; /* * SPI_PNT_SPRITE_OVERRIDE enum */ SPI_PNT_SPRITE_OVERRIDE; /* * SPI_PS_LDS_GROUP_SIZE enum */ SPI_PS_LDS_GROUP_SIZE; /* * SPI_SAMPLE_CNTL enum */ SPI_SAMPLE_CNTL; /* * SPI_SHADER_EX_FORMAT enum */ SPI_SHADER_EX_FORMAT; /* * SPI_SHADER_FORMAT enum */ SPI_SHADER_FORMAT; /******************************************************* * SQ Enums *******************************************************/ /* * SH_MEM_ADDRESS_MODE enum */ SH_MEM_ADDRESS_MODE; /* * SH_MEM_ALIGNMENT_MODE enum */ SH_MEM_ALIGNMENT_MODE; /* * SQG_PERF_SEL enum */ SQG_PERF_SEL; /* * SQ_CAC_POWER_SEL enum */ SQ_CAC_POWER_SEL; /* * SQ_EDC_INFO_SOURCE enum */ SQ_EDC_INFO_SOURCE; /* * SQ_IBUF_ST enum */ SQ_IBUF_ST; /* * SQ_IMG_FILTER_TYPE enum */ SQ_IMG_FILTER_TYPE; /* * SQ_IND_CMD_CMD enum */ SQ_IND_CMD_CMD; /* * SQ_IND_CMD_MODE enum */ SQ_IND_CMD_MODE; /* * SQ_INST_STR_ST enum */ SQ_INST_STR_ST; /* * SQ_INST_TYPE enum */ SQ_INST_TYPE; /* * SQ_LLC_CTL enum */ SQ_LLC_CTL; /* * SQ_NO_INST_ISSUE enum */ SQ_NO_INST_ISSUE; /* * SQ_OOB_SELECT enum */ SQ_OOB_SELECT; /* * SQ_PERF_SEL enum */ SQ_PERF_SEL; /* * SQ_ROUND_MODE enum */ SQ_ROUND_MODE; /* * SQ_RSRC_BUF_TYPE enum */ SQ_RSRC_BUF_TYPE; /* * SQ_RSRC_FLAT_TYPE enum */ SQ_RSRC_FLAT_TYPE; /* * SQ_RSRC_IMG_TYPE enum */ SQ_RSRC_IMG_TYPE; /* * SQ_SEL_XYZW01 enum */ SQ_SEL_XYZW01; /* * SQ_TEX_ANISO_RATIO enum */ SQ_TEX_ANISO_RATIO; /* * SQ_TEX_BORDER_COLOR enum */ SQ_TEX_BORDER_COLOR; /* * SQ_TEX_CLAMP enum */ SQ_TEX_CLAMP; /* * SQ_TEX_DEPTH_COMPARE enum */ SQ_TEX_DEPTH_COMPARE; /* * SQ_TEX_MIP_FILTER enum */ SQ_TEX_MIP_FILTER; /* * SQ_TEX_XY_FILTER enum */ SQ_TEX_XY_FILTER; /* * SQ_TEX_Z_FILTER enum */ SQ_TEX_Z_FILTER; /* * SQ_TT_MODE enum */ SQ_TT_MODE; /* * SQ_TT_RT_FREQ enum */ SQ_TT_RT_FREQ; /* * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum */ SQ_TT_TOKEN_MASK_INST_EXCLUDE; /* * SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT enum */ SQ_TT_TOKEN_MASK_INST_EXCLUDE_SHIFT; /* * SQ_TT_TOKEN_MASK_REG_EXCLUDE enum */ SQ_TT_TOKEN_MASK_REG_EXCLUDE; /* * SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT enum */ SQ_TT_TOKEN_MASK_REG_EXCLUDE_SHIFT; /* * SQ_TT_TOKEN_MASK_REG_INCLUDE enum */ SQ_TT_TOKEN_MASK_REG_INCLUDE; /* * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum */ SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT; /* * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum */ SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT; /* * SQ_TT_UTIL_TIMER enum */ SQ_TT_UTIL_TIMER; /* * SQ_TT_WAVESTART_MODE enum */ SQ_TT_WAVESTART_MODE; /* * SQ_TT_WTYPE_INCLUDE enum */ SQ_TT_WTYPE_INCLUDE; /* * SQ_TT_WTYPE_INCLUDE_SHIFT enum */ SQ_TT_WTYPE_INCLUDE_SHIFT; /* * SQ_WATCH_MODES enum */ SQ_WATCH_MODES; /* * SQ_WAVE_FWD_PROG_INTERVAL enum */ SQ_WAVE_FWD_PROG_INTERVAL; /* * SQ_WAVE_IB_ECC_ST enum */ SQ_WAVE_IB_ECC_ST; /* * SQ_WAVE_SCHED_MODES enum */ SQ_WAVE_SCHED_MODES; /* * SQ_WAVE_TYPE enum */ SQ_WAVE_TYPE; /* * SQ_WAVE_TYPE value */ #define SQ_WAVE_TYPE_PS0 … /* * SQIND_PARTITIONS value */ #define SQIND_GLOBAL_REGS_OFFSET … #define SQIND_GLOBAL_REGS_SIZE … #define SQIND_LOCAL_REGS_OFFSET … #define SQIND_LOCAL_REGS_SIZE … #define SQIND_WAVE_HWREGS_OFFSET … #define SQIND_WAVE_HWREGS_SIZE … #define SQIND_WAVE_SGPRS_OFFSET … #define SQIND_WAVE_SGPRS_SIZE … #define SQIND_WAVE_VGPRS_OFFSET … #define SQIND_WAVE_VGPRS_SIZE … /* * SQ_GFXDEC value */ #define SQ_GFXDEC_BEGIN … #define SQ_GFXDEC_END … #define SQ_GFXDEC_STATE_ID_SHIFT … /* * SQDEC value */ #define SQDEC_BEGIN … #define SQDEC_END … /* * SQPERFSDEC value */ #define SQPERFSDEC_BEGIN … #define SQPERFSDEC_END … /* * SQPERFDDEC value */ #define SQPERFDDEC_BEGIN … #define SQPERFDDEC_END … /* * SQGFXUDEC value */ #define SQGFXUDEC_BEGIN … #define SQGFXUDEC_END … /* * SQPWRDEC value */ #define SQPWRDEC_BEGIN … #define SQPWRDEC_END … /* * SQ_DISPATCHER value */ #define SQ_DISPATCHER_GFX_MIN … #define SQ_DISPATCHER_GFX_CNT_PER_RING … /* * SQ_MAX value */ #define SQ_MAX_PGM_SGPRS … #define SQ_MAX_PGM_VGPRS … /* * SQ_EXCP_BITS value */ #define SQ_EX_MODE_EXCP_VALU_BASE … #define SQ_EX_MODE_EXCP_VALU_SIZE … #define SQ_EX_MODE_EXCP_INVALID … #define SQ_EX_MODE_EXCP_INPUT_DENORM … #define SQ_EX_MODE_EXCP_DIV0 … #define SQ_EX_MODE_EXCP_OVERFLOW … #define SQ_EX_MODE_EXCP_UNDERFLOW … #define SQ_EX_MODE_EXCP_INEXACT … #define SQ_EX_MODE_EXCP_INT_DIV0 … #define SQ_EX_MODE_EXCP_ADDR_WATCH0 … #define SQ_EX_MODE_EXCP_MEM_VIOL … /* * SQ_EXCP_HI_BITS value */ #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 … #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 … #define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 … /* * HW_INSERTED_INST_ID value */ #define INST_ID_PRIV_START … #define INST_ID_ECC_INTERRUPT_MSG … #define INST_ID_TTRACE_NEW_PC_MSG … #define INST_ID_HW_TRAP … #define INST_ID_KILL_SEQ … #define INST_ID_SPI_WREXEC … #define INST_ID_HW_TRAP_GET_TBA … #define INST_ID_HOST_REG_TRAP_MSG … /* * SIMM16_WAITCNT_PARTITIONS value */ #define SIMM16_WAITCNT_EXP_CNT_START … #define SIMM16_WAITCNT_EXP_CNT_SIZE … #define SIMM16_WAITCNT_LGKM_CNT_START … #define SIMM16_WAITCNT_LGKM_CNT_SIZE … #define SIMM16_WAITCNT_VM_CNT_START … #define SIMM16_WAITCNT_VM_CNT_SIZE … #define SIMM16_WAITCNT_DEPCTR_SA_SDST_START … #define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE … #define SIMM16_WAITCNT_DEPCTR_VA_VCC_START … #define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE … #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START … #define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE … #define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_START … #define SIMM16_WAITCNT_DEPCTR_HOLD_CNT_SIZE … #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START … #define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE … #define SIMM16_WAITCNT_DEPCTR_VA_SDST_START … #define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE … #define SIMM16_WAITCNT_DEPCTR_VA_VDST_START … #define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE … /* * SIMM16_WAIT_EVENT_PARTITIONS value */ #define SIMM16_WAIT_EVENT_EXP_RDY_START … #define SIMM16_WAIT_EVENT_EXP_RDY_SIZE … /* * SQ_WAVE_IB_DEP_COUNTER_SIZES value */ #define SQ_WAVE_IB_DEP_SA_SDST_SIZE … #define SQ_WAVE_IB_DEP_SA_EXEC_SIZE … #define SQ_WAVE_IB_DEP_SA_M0_SIZE … #define SQ_WAVE_IB_DEP_VM_VSRC_SIZE … #define SQ_WAVE_IB_DEP_HOLD_CNT_SIZE … #define SQ_WAVE_IB_DEP_VA_SSRC_SIZE … #define SQ_WAVE_IB_DEP_VA_SDST_SIZE … #define SQ_WAVE_IB_DEP_VA_VCC_SIZE … #define SQ_WAVE_IB_DEP_VA_EXEC_SIZE … #define SQ_WAVE_IB_DEP_VA_VDST_SIZE … #define SQ_WAVE_IB_DEP_LDS_DIR_SIZE … /* * SQ_EDC_FUE_CNTL_BITS value */ #define SQ_EDC_FUE_CNTL_SIMD0 … #define SQ_EDC_FUE_CNTL_SIMD1 … #define SQ_EDC_FUE_CNTL_SIMD2 … #define SQ_EDC_FUE_CNTL_SIMD3 … #define SQ_EDC_FUE_CNTL_SQ … #define SQ_EDC_FUE_CNTL_LDS … #define SQ_EDC_FUE_CNTL_TD … #define SQ_EDC_FUE_CNTL_TA … #define SQ_EDC_FUE_CNTL_TCP … /******************************************************* * COMP Enums *******************************************************/ /* * CSCNTL_TYPE enum */ CSCNTL_TYPE; /* * CSDATA_TYPE enum */ CSDATA_TYPE; /* * CSDATA_TYPE_WIDTH value */ #define CSDATA_TYPE_WIDTH … /* * CSDATA_ADDR_WIDTH value */ #define CSDATA_ADDR_WIDTH … /* * CSDATA_DATA_WIDTH value */ #define CSDATA_DATA_WIDTH … /* * CSCNTL_TYPE_WIDTH value */ #define CSCNTL_TYPE_WIDTH … /* * CSCNTL_ADDR_WIDTH value */ #define CSCNTL_ADDR_WIDTH … /* * CSCNTL_DATA_WIDTH value */ #define CSCNTL_DATA_WIDTH … /******************************************************* * GE Enums *******************************************************/ /* * GE1_PERFCOUNT_SELECT enum */ GE1_PERFCOUNT_SELECT; /* * GE2_DIST_PERFCOUNT_SELECT enum */ GE2_DIST_PERFCOUNT_SELECT; /* * GE2_SE_PERFCOUNT_SELECT enum */ GE2_SE_PERFCOUNT_SELECT; /* * VGT_DETECT_ONE enum */ VGT_DETECT_ONE; /* * VGT_DETECT_ZERO enum */ VGT_DETECT_ZERO; /* * VGT_DIST_MODE enum */ VGT_DIST_MODE; /* * VGT_DI_INDEX_SIZE enum */ VGT_DI_INDEX_SIZE; /* * VGT_DI_MAJOR_MODE_SELECT enum */ VGT_DI_MAJOR_MODE_SELECT; /* * VGT_DI_PRIM_TYPE enum */ VGT_DI_PRIM_TYPE; /* * VGT_DI_SOURCE_SELECT enum */ VGT_DI_SOURCE_SELECT; /* * VGT_DMA_BUF_TYPE enum */ VGT_DMA_BUF_TYPE; /* * VGT_DMA_SWAP_MODE enum */ VGT_DMA_SWAP_MODE; /* * VGT_EVENT_TYPE enum */ VGT_EVENT_TYPE; /* * VGT_GROUP_CONV_SEL enum */ VGT_GROUP_CONV_SEL; /* * VGT_GS_MODE_TYPE enum */ VGT_GS_MODE_TYPE; /* * VGT_GS_OUTPRIM_TYPE enum */ VGT_GS_OUTPRIM_TYPE; /* * VGT_INDEX_TYPE_MODE enum */ VGT_INDEX_TYPE_MODE; /* * VGT_OUTPATH_SELECT enum */ VGT_OUTPATH_SELECT; /* * VGT_OUT_PRIM_TYPE enum */ VGT_OUT_PRIM_TYPE; /* * VGT_RDREQ_POLICY enum */ VGT_RDREQ_POLICY; /* * VGT_STAGES_ES_EN enum */ VGT_STAGES_ES_EN; /* * VGT_STAGES_GS_EN enum */ VGT_STAGES_GS_EN; /* * VGT_STAGES_HS_EN enum */ VGT_STAGES_HS_EN; /* * VGT_STAGES_LS_EN enum */ VGT_STAGES_LS_EN; /* * VGT_STAGES_VS_EN enum */ VGT_STAGES_VS_EN; /* * VGT_TESS_PARTITION enum */ VGT_TESS_PARTITION; /* * VGT_TESS_TOPOLOGY enum */ VGT_TESS_TOPOLOGY; /* * VGT_TESS_TYPE enum */ VGT_TESS_TYPE; /* * WD_IA_DRAW_REG_XFER enum */ WD_IA_DRAW_REG_XFER; /* * WD_IA_DRAW_SOURCE enum */ WD_IA_DRAW_SOURCE; /* * WD_IA_DRAW_TYPE enum */ WD_IA_DRAW_TYPE; /* * GS_THREADID_SIZE value */ #define GSTHREADID_SIZE … /******************************************************* * GB Enums *******************************************************/ /* * GB_EDC_DED_MODE enum */ GB_EDC_DED_MODE; /* * VALUE_GB_TILING_CONFIG_TABLE_SIZE value */ #define GB_TILING_CONFIG_TABLE_SIZE … /* * VALUE_GB_TILING_CONFIG_MACROTABLE_SIZE value */ #define GB_TILING_CONFIG_MACROTABLE_SIZE … /******************************************************* * GLX Enums *******************************************************/ /* * CHA_PERF_SEL enum */ CHA_PERF_SEL; /* * CHCG_PERF_SEL enum */ CHCG_PERF_SEL; /* * CHC_PERF_SEL enum */ CHC_PERF_SEL; /* * GL1A_PERF_SEL enum */ GL1A_PERF_SEL; /* * GL1C_PERF_SEL enum */ GL1C_PERF_SEL; /******************************************************* * GL1H Enums *******************************************************/ /* * GL1H_REQ_PERF_SEL enum */ GL1H_REQ_PERF_SEL; /******************************************************* * TA Enums *******************************************************/ /* * TA_PERFCOUNT_SEL enum */ TA_PERFCOUNT_SEL; /* * TEX_BC_SWIZZLE enum */ TEX_BC_SWIZZLE; /* * TEX_BORDER_COLOR_TYPE enum */ TEX_BORDER_COLOR_TYPE; /* * TEX_CHROMA_KEY enum */ TEX_CHROMA_KEY; /* * TEX_CLAMP enum */ TEX_CLAMP; /* * TEX_COORD_TYPE enum */ TEX_COORD_TYPE; /* * TEX_DEPTH_COMPARE_FUNCTION enum */ TEX_DEPTH_COMPARE_FUNCTION; /* * TEX_FORMAT_COMP enum */ TEX_FORMAT_COMP; /* * TEX_MAX_ANISO_RATIO enum */ TEX_MAX_ANISO_RATIO; /* * TEX_MIP_FILTER enum */ TEX_MIP_FILTER; /* * TEX_REQUEST_SIZE enum */ TEX_REQUEST_SIZE; /* * TEX_SAMPLER_TYPE enum */ TEX_SAMPLER_TYPE; /* * TEX_XY_FILTER enum */ TEX_XY_FILTER; /* * TEX_Z_FILTER enum */ TEX_Z_FILTER; /* * TVX_TYPE enum */ TVX_TYPE; /******************************************************* * TCP Enums *******************************************************/ /* * TA_TC_ADDR_MODES enum */ TA_TC_ADDR_MODES; /* * TA_TC_REQ_MODES enum */ TA_TC_REQ_MODES; /* * TCP_CACHE_POLICIES enum */ TCP_CACHE_POLICIES; /* * TCP_CACHE_STORE_POLICIES enum */ TCP_CACHE_STORE_POLICIES; /* * TCP_DSM_DATA_SEL enum */ TCP_DSM_DATA_SEL; /* * TCP_DSM_INJECT_SEL enum */ TCP_DSM_INJECT_SEL; /* * TCP_DSM_SINGLE_WRITE enum */ TCP_DSM_SINGLE_WRITE; /* * TCP_OPCODE_TYPE enum */ TCP_OPCODE_TYPE; /* * TCP_PERFCOUNT_SELECT enum */ TCP_PERFCOUNT_SELECT; /* * TCP_WATCH_MODES enum */ TCP_WATCH_MODES; /******************************************************* * TD Enums *******************************************************/ /* * TD_PERFCOUNT_SEL enum */ TD_PERFCOUNT_SEL; /******************************************************* * GL2C Enums *******************************************************/ /* * GL2A_PERF_SEL enum */ GL2A_PERF_SEL; /* * GL2C_PERF_SEL enum */ GL2C_PERF_SEL; /******************************************************* * GRBM Enums *******************************************************/ /* * GRBM_PERF_SEL enum */ GRBM_PERF_SEL; /* * GRBM_SE0_PERF_SEL enum */ GRBM_SE0_PERF_SEL; /* * GRBM_SE1_PERF_SEL enum */ GRBM_SE1_PERF_SEL; /* * GRBM_SE2_PERF_SEL enum */ GRBM_SE2_PERF_SEL; /* * GRBM_SE3_PERF_SEL enum */ GRBM_SE3_PERF_SEL; /* * GRBM_SE4_PERF_SEL enum */ GRBM_SE4_PERF_SEL; /* * GRBM_SE5_PERF_SEL enum */ GRBM_SE5_PERF_SEL; /* * GRBM_SE6_PERF_SEL enum */ GRBM_SE6_PERF_SEL; /* * GRBM_SE7_PERF_SEL enum */ GRBM_SE7_PERF_SEL; /* * PIPE_COMPAT_LEVEL enum */ PIPE_COMPAT_LEVEL; /******************************************************* * CP Enums *******************************************************/ /* * CPC_LATENCY_STATS_SEL enum */ CPC_LATENCY_STATS_SEL; /* * CPC_PERFCOUNT_SEL enum */ CPC_PERFCOUNT_SEL; /* * CPF_LATENCY_STATS_SEL enum */ CPF_LATENCY_STATS_SEL; /* * CPF_PERFCOUNTWINDOW_SEL enum */ CPF_PERFCOUNTWINDOW_SEL; /* * CPF_PERFCOUNT_SEL enum */ CPF_PERFCOUNT_SEL; /* * CPF_SCRATCH_REG_ATOMIC_OP enum */ CPF_SCRATCH_REG_ATOMIC_OP; /* * CPG_LATENCY_STATS_SEL enum */ CPG_LATENCY_STATS_SEL; /* * CPG_PERFCOUNTWINDOW_SEL enum */ CPG_PERFCOUNTWINDOW_SEL; /* * CPG_PERFCOUNT_SEL enum */ CPG_PERFCOUNT_SEL; /* * CP_ALPHA_TAG_RAM_SEL enum */ CP_ALPHA_TAG_RAM_SEL; /* * CP_DDID_CNTL_MODE enum */ CP_DDID_CNTL_MODE; /* * CP_DDID_CNTL_SIZE enum */ CP_DDID_CNTL_SIZE; /* * CP_DDID_CNTL_VMID_SEL enum */ CP_DDID_CNTL_VMID_SEL; /* * CP_ME_ID enum */ CP_ME_ID; /* * CP_PERFMON_ENABLE_MODE enum */ CP_PERFMON_ENABLE_MODE; /* * CP_PERFMON_STATE enum */ CP_PERFMON_STATE; /* * CP_PIPE_ID enum */ CP_PIPE_ID; /* * CP_RING_ID enum */ CP_RING_ID; /* * SPM_PERFMON_STATE enum */ SPM_PERFMON_STATE; /* * SEM_RESPONSE value */ #define SEM_ECC_ERROR … #define SEM_TRANS_ERROR … #define SEM_RESP_FAILED … #define SEM_RESP_PASSED … /* * IQ_RETRY_TYPE value */ #define IQ_QUEUE_SLEEP … #define IQ_OFFLOAD_RETRY … #define IQ_SCH_WAVE_MSG … #define IQ_SEM_REARM … #define IQ_DEQUEUE_RETRY … /* * IQ_INTR_TYPE value */ #define IQ_INTR_TYPE_PQ … #define IQ_INTR_TYPE_IB … #define IQ_INTR_TYPE_MQD … /* * VMID_SIZE value */ #define VMID_SZ … /* * SRCID_SECURE value */ #define SRCID_RLC … #define SRCID_RLCV … #define SRCID_SECURE_CP … #define SRCID_NONSECURE_CP … #define SRCID_SECURE_CP_RCIU … #define SRCID_NONSECURE_CP_RCIU … /* * CONFIG_SPACE value */ #define CONFIG_SPACE_START … #define CONFIG_SPACE_END … /* * CONFIG_SPACE1 value */ #define CONFIG_SPACE1_START … #define CONFIG_SPACE1_END … /* * CONFIG_SPACE2 value */ #define CONFIG_SPACE2_START … #define CONFIG_SPACE2_END … /* * UCONFIG_SPACE value */ #define UCONFIG_SPACE_START … #define UCONFIG_SPACE_END … /* * PERSISTENT_SPACE value */ #define PERSISTENT_SPACE_START … #define PERSISTENT_SPACE_END … /* * CONTEXT_SPACE value */ #define CONTEXT_SPACE_START … #define CONTEXT_SPACE_END … /******************************************************* * SX Enums *******************************************************/ /* * SX_BLEND_OPT enum */ SX_BLEND_OPT; /* * SX_DOWNCONVERT_FORMAT enum */ SX_DOWNCONVERT_FORMAT; /* * SX_OPT_COMB_FCN enum */ SX_OPT_COMB_FCN; /* * SX_PERFCOUNTER_VALS enum */ SX_PERFCOUNTER_VALS; /******************************************************* * DB Enums *******************************************************/ /* * CompareFrag enum */ CompareFrag; /* * ConservativeZExport enum */ ConservativeZExport; /* * DFSMFlushEvents enum */ DFSMFlushEvents; /* * DbMemArbWatermarks enum */ DbMemArbWatermarks; /* * DbPRTFaultBehavior enum */ DbPRTFaultBehavior; /* * DbPSLControl enum */ DbPSLControl; /* * ForceControl enum */ ForceControl; /* * OreoMode enum */ OreoMode; /* * PerfCounter_Vals enum */ PerfCounter_Vals; /* * PixelPipeCounterId enum */ PixelPipeCounterId; /* * PixelPipeStride enum */ PixelPipeStride; /* * RingCounterControl enum */ RingCounterControl; /* * StencilOp enum */ StencilOp; /* * ZLimitSumm enum */ ZLimitSumm; /* * ZModeForce enum */ ZModeForce; /* * ZOrder enum */ ZOrder; /* * ZSamplePosition enum */ ZSamplePosition; /* * ZpassControl enum */ ZpassControl; /******************************************************* * PA Enums *******************************************************/ /* * SU_PERFCNT_SEL enum */ SU_PERFCNT_SEL; /******************************************************* * PH Enums *******************************************************/ /* * PH_PERFCNT_SEL enum */ PH_PERFCNT_SEL; /* * PhSPIstatusMode enum */ PhSPIstatusMode; /******************************************************* * RMI Enums *******************************************************/ /* * RMIPerfSel enum */ RMIPerfSel; /******************************************************* * PMM Enums *******************************************************/ /* * GCRPerfSel enum */ GCRPerfSel; /******************************************************* * UTCL1 Enums *******************************************************/ /* * UTCL1PerfSel enum */ UTCL1PerfSel; /******************************************************* * IH Enums *******************************************************/ /* * IH_CLIENT_TYPE enum */ IH_CLIENT_TYPE; /* * IH_INTERFACE_TYPE enum */ IH_INTERFACE_TYPE; /* * IH_PERF_SEL enum */ IH_PERF_SEL; /* * IH_RING_ID enum */ IH_RING_ID; /* * IH_VF_RB_SELECT enum */ IH_VF_RB_SELECT; /******************************************************* * SEM Enums *******************************************************/ /* * SEM_PERF_SEL enum */ SEM_PERF_SEL; /******************************************************* * LSDMA Enums *******************************************************/ /* * LSDMA_PERF_SEL enum */ LSDMA_PERF_SEL; /******************************************************* * SMUIO_ROM Enums *******************************************************/ /* * ROM_SIGNATURE value */ #define ROM_SIGNATURE … /******************************************************* * UVD_EFC Enums *******************************************************/ /* * EFC_SURFACE_PIXEL_FORMAT enum */ EFC_SURFACE_PIXEL_FORMAT; #endif /*_soc21_ENUM_HEADER*/
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