linux/arch/x86/include/asm/posted_intr.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _X86_POSTED_INTR_H
#define _X86_POSTED_INTR_H
#include <asm/irq_vectors.h>

#define POSTED_INTR_ON …
#define POSTED_INTR_SN …

#define PID_TABLE_ENTRY_VALID …

/* Posted-Interrupt Descriptor */
struct pi_desc { … } __aligned(…);

static inline bool pi_test_and_set_on(struct pi_desc *pi_desc)
{ … }

static inline bool pi_test_and_clear_on(struct pi_desc *pi_desc)
{ … }

static inline bool pi_test_and_clear_sn(struct pi_desc *pi_desc)
{ … }

static inline bool pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
{ … }

static inline bool pi_is_pir_empty(struct pi_desc *pi_desc)
{ … }

static inline void pi_set_sn(struct pi_desc *pi_desc)
{ … }

static inline void pi_set_on(struct pi_desc *pi_desc)
{ … }

static inline void pi_clear_on(struct pi_desc *pi_desc)
{ … }

static inline void pi_clear_sn(struct pi_desc *pi_desc)
{ … }

static inline bool pi_test_on(struct pi_desc *pi_desc)
{ … }

static inline bool pi_test_sn(struct pi_desc *pi_desc)
{ … }

/* Non-atomic helpers */
static inline void __pi_set_sn(struct pi_desc *pi_desc)
{ … }

static inline void __pi_clear_sn(struct pi_desc *pi_desc)
{ … }

#ifdef CONFIG_X86_POSTED_MSI
/*
 * Not all external vectors are subject to interrupt remapping, e.g. IOMMU's
 * own interrupts. Here we do not distinguish them since those vector bits in
 * PIR will always be zero.
 */
static inline bool pi_pending_this_cpu(unsigned int vector)
{ … }

extern void intel_posted_msi_init(void);
#else
static inline bool pi_pending_this_cpu(unsigned int vector) { return false; }

static inline void intel_posted_msi_init(void) {};
#endif /* X86_POSTED_MSI */

#endif /* _X86_POSTED_INTR_H */