/* SPDX-License-Identifier: GPL-2.0-only */ /* * Rockchip RK3308 internal audio codec driver -- register definitions * * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd All rights reserved. * Copyright (c) 2022, Vivax-Metrotech Ltd */ #ifndef __RK3308_CODEC_H__ #define __RK3308_CODEC_H__ #define RK3308_GLB_CON … /* ADC DIGITAL REGISTERS */ /* * The ADC group are 0 ~ 3, that control: * * CH0: left_0(ADC1) and right_0(ADC2) * CH1: left_1(ADC3) and right_1(ADC4) * CH2: left_2(ADC5) and right_2(ADC6) * CH3: left_3(ADC7) and right_3(ADC8) */ #define RK3308_ADC_DIG_OFFSET(ch) … #define RK3308_ADC_DIG_CON01(ch) … #define RK3308_ADC_DIG_CON02(ch) … #define RK3308_ADC_DIG_CON03(ch) … #define RK3308_ADC_DIG_CON04(ch) … #define RK3308_ADC_DIG_CON05(ch) … #define RK3308_ADC_DIG_CON06(ch) … #define RK3308_ADC_DIG_CON07(ch) … #define RK3308_ALC_L_DIG_CON00(ch) … #define RK3308_ALC_L_DIG_CON01(ch) … #define RK3308_ALC_L_DIG_CON02(ch) … #define RK3308_ALC_L_DIG_CON03(ch) … #define RK3308_ALC_L_DIG_CON04(ch) … #define RK3308_ALC_L_DIG_CON05(ch) … #define RK3308_ALC_L_DIG_CON06(ch) … #define RK3308_ALC_L_DIG_CON07(ch) … #define RK3308_ALC_L_DIG_CON08(ch) … #define RK3308_ALC_L_DIG_CON09(ch) … #define RK3308_ALC_L_DIG_CON12(ch) … #define RK3308_ALC_R_DIG_CON00(ch) … #define RK3308_ALC_R_DIG_CON01(ch) … #define RK3308_ALC_R_DIG_CON02(ch) … #define RK3308_ALC_R_DIG_CON03(ch) … #define RK3308_ALC_R_DIG_CON04(ch) … #define RK3308_ALC_R_DIG_CON05(ch) … #define RK3308_ALC_R_DIG_CON06(ch) … #define RK3308_ALC_R_DIG_CON07(ch) … #define RK3308_ALC_R_DIG_CON08(ch) … #define RK3308_ALC_R_DIG_CON09(ch) … #define RK3308_ALC_R_DIG_CON12(ch) … /* DAC DIGITAL REGISTERS */ #define RK3308_DAC_DIG_OFFSET … #define RK3308_DAC_DIG_CON01 … #define RK3308_DAC_DIG_CON02 … #define RK3308_DAC_DIG_CON03 … #define RK3308_DAC_DIG_CON04 … #define RK3308_DAC_DIG_CON05 … #define RK3308_DAC_DIG_CON10 … #define RK3308_DAC_DIG_CON11 … #define RK3308_DAC_DIG_CON13 … #define RK3308_DAC_DIG_CON14 … /* ADC ANALOG REGISTERS */ /* * The ADC group are 0 ~ 3, that control: * * CH0: left_0(ADC1) and right_0(ADC2) * CH1: left_1(ADC3) and right_1(ADC4) * CH2: left_2(ADC5) and right_2(ADC6) * CH3: left_3(ADC7) and right_3(ADC8) */ #define RK3308_ADC_ANA_OFFSET(ch) … #define RK3308_ADC_ANA_CON00(ch) … #define RK3308_ADC_ANA_CON01(ch) … #define RK3308_ADC_ANA_CON02(ch) … #define RK3308_ADC_ANA_CON03(ch) … #define RK3308_ADC_ANA_CON04(ch) … #define RK3308_ADC_ANA_CON05(ch) … #define RK3308_ADC_ANA_CON06(ch) … #define RK3308_ADC_ANA_CON07(ch) … #define RK3308_ADC_ANA_CON08(ch) … #define RK3308_ADC_ANA_CON10(ch) … #define RK3308_ADC_ANA_CON11(ch) … /* DAC ANALOG REGISTERS */ #define RK3308_DAC_ANA_OFFSET … #define RK3308_DAC_ANA_CON00 … #define RK3308_DAC_ANA_CON01 … #define RK3308_DAC_ANA_CON02 … #define RK3308_DAC_ANA_CON03 … #define RK3308_DAC_ANA_CON04 … #define RK3308_DAC_ANA_CON05 … #define RK3308_DAC_ANA_CON06 … #define RK3308_DAC_ANA_CON07 … #define RK3308_DAC_ANA_CON08 … #define RK3308_DAC_ANA_CON12 … #define RK3308_DAC_ANA_CON13 … #define RK3308_DAC_ANA_CON14 … #define RK3308_DAC_ANA_CON15 … /* * These are the bits for registers */ /* RK3308_GLB_CON - REG: 0x0000 */ #define RK3308_ADC_BIST_WORK … #define RK3308_DAC_BIST_WORK … #define RK3308_ADC_MCLK_GATING … #define RK3308_DAC_MCLK_GATING … #define RK3308_ADC_DIG_WORK … #define RK3308_DAC_DIG_WORK … #define RK3308_SYS_WORK … /* RK3308_ADC_DIG_CON01 - REG: 0x0004 */ #define RK3308_ADC_I2S_LRC_POL_REVERSAL … #define RK3308_ADC_I2S_VALID_LEN_SFT … #define RK3308_ADC_I2S_VALID_LEN_MSK … #define RK3308_ADC_I2S_VALID_LEN_32BITS … #define RK3308_ADC_I2S_VALID_LEN_24BITS … #define RK3308_ADC_I2S_VALID_LEN_20BITS … #define RK3308_ADC_I2S_VALID_LEN_16BITS … #define RK3308_ADC_I2S_MODE_SFT … #define RK3308_ADC_I2S_MODE_MSK … #define RK3308_ADC_I2S_MODE_PCM … #define RK3308_ADC_I2S_MODE_I2S … #define RK3308_ADC_I2S_MODE_LJ … #define RK3308_ADC_I2S_MODE_RJ … #define RK3308_ADC_I2S_LR_SWAP … #define RK3308_ADC_I2S_MONO … /* RK3308_ADC_DIG_CON02 - REG: 0x0008 */ #define RK3308_ADC_IO_MODE_MASTER … #define RK3308_ADC_MODE_MASTER … #define RK3308_ADC_I2S_FRAME_LEN_SFT … #define RK3308_ADC_I2S_FRAME_LEN_MSK … #define RK3308_ADC_I2S_FRAME_32BITS … #define RK3308_ADC_I2S_FRAME_24BITS … #define RK3308_ADC_I2S_FRAME_20BITS … #define RK3308_ADC_I2S_FRAME_16BITS … #define RK3308_ADC_I2S_WORK … #define RK3308_ADC_I2S_BIT_CLK_POL_REVERSAL … /* RK3308_ADC_DIG_CON03 - REG: 0x000c */ #define RK3308_ADC_L_CH_BIST_SFT … #define RK3308_ADC_L_CH_BIST_MSK … #define RK3308_ADC_L_CH_NORMAL_RIGHT … #define RK3308_ADC_L_CH_BIST_CUBE … #define RK3308_ADC_L_CH_BIST_SINE … #define RK3308_ADC_L_CH_NORMAL_LEFT … #define RK3308_ADC_R_CH_BIST_SFT … #define RK3308_ADC_R_CH_BIST_MSK … #define RK3308_ADC_R_CH_NORMAL_LEFT … #define RK3308_ADC_R_CH_BIST_CUBE … #define RK3308_ADC_R_CH_BIST_SINE … #define RK3308_ADC_R_CH_NORMAL_RIGHT … /* RK3308_ADC_DIG_CON04 - REG: 0x0010 */ #define RK3308_ADC_HPF_PATH_DIS … #define RK3308_ADC_HPF_CUTOFF_SFT … #define RK3308_ADC_HPF_CUTOFF_MSK … #define RK3308_ADC_HPF_CUTOFF_612HZ … #define RK3308_ADC_HPF_CUTOFF_245HZ … #define RK3308_ADC_HPF_CUTOFF_20HZ … /* RK3308_ADC_DIG_CON07 - REG: 0x001c */ #define RK3308_ADCL_DATA_SFT … #define RK3308_ADCR_DATA_SFT … #define RK3308_ADCL_DATA_SEL_ADCL … #define RK3308_ADCR_DATA_SEL_ADCR … /* * RK3308_ALC_L_DIG_CON00 - REG: 0x0040 + ch * 0xc0 * RK3308_ALC_R_DIG_CON00 - REG: 0x0080 + ch * 0xc0 */ #define RK3308_GAIN_ATTACK_JACK … #define RK3308_CTRL_GEN_SFT … #define RK3308_CTRL_GEN_MSK … #define RK3308_CTRL_GEN_JACK3 … #define RK3308_CTRL_GEN_JACK2 … #define RK3308_CTRL_GEN_JACK1 … #define RK3308_CTRL_GEN_NORMAL … #define RK3308_AGC_HOLD_TIME_SFT … #define RK3308_AGC_HOLD_TIME_MSK … #define RK3308_AGC_HOLD_TIME_1S … #define RK3308_AGC_HOLD_TIME_512MS … #define RK3308_AGC_HOLD_TIME_256MS … #define RK3308_AGC_HOLD_TIME_128MS … #define RK3308_AGC_HOLD_TIME_64MS … #define RK3308_AGC_HOLD_TIME_32MS … #define RK3308_AGC_HOLD_TIME_16MS … #define RK3308_AGC_HOLD_TIME_8MS … #define RK3308_AGC_HOLD_TIME_4MS … #define RK3308_AGC_HOLD_TIME_2MS … #define RK3308_AGC_HOLD_TIME_0MS … /* * RK3308_ALC_L_DIG_CON01 - REG: 0x0044 + ch * 0xc0 * RK3308_ALC_R_DIG_CON01 - REG: 0x0084 + ch * 0xc0 */ #define RK3308_AGC_DECAY_TIME_SFT … #define RK3308_AGC_ATTACK_TIME_SFT … /* * RK3308_ALC_L_DIG_CON02 - REG: 0x0048 + ch * 0xc0 * RK3308_ALC_R_DIG_CON02 - REG: 0x0088 + ch * 0xc0 */ #define RK3308_AGC_MODE_LIMITER … #define RK3308_AGC_ZERO_CRO_EN … #define RK3308_AGC_AMP_RECOVER_GAIN … #define RK3308_AGC_FAST_DEC_EN … #define RK3308_AGC_NOISE_GATE_EN … #define RK3308_AGC_NOISE_GATE_THRESH_SFT … #define RK3308_AGC_NOISE_GATE_THRESH_MSK … /* * RK3308_ALC_L_DIG_CON03 - REG: 0x004c + ch * 0xc0 * RK3308_ALC_R_DIG_CON03 - REG: 0x008c + ch * 0xc0 */ #define RK3308_AGC_PGA_ZERO_CRO_EN … #define RK3308_AGC_PGA_GAIN_MAX … #define RK3308_AGC_PGA_GAIN_MIN … #define RK3308_AGC_PGA_GAIN_SFT … /* * RK3308_ALC_L_DIG_CON04 - REG: 0x0050 + ch * 0xc0 * RK3308_ALC_R_DIG_CON04 - REG: 0x0090 + ch * 0xc0 */ #define RK3308_AGC_SLOW_CLK_EN … #define RK3308_AGC_APPROX_RATE_SFT … #define RK3308_AGC_APPROX_RATE_MSK … /* * RK3308_ALC_L_DIG_CON05 - REG: 0x0054 + ch * 0xc0 * RK3308_ALC_R_DIG_CON05 - REG: 0x0094 + ch * 0xc0 */ #define RK3308_AGC_LO_8BITS_AGC_MAX_MSK … /* * RK3308_ALC_L_DIG_CON06 - REG: 0x0058 + ch * 0xc0 * RK3308_ALC_R_DIG_CON06 - REG: 0x0098 + ch * 0xc0 */ #define RK3308_AGC_HI_8BITS_AGC_MAX_MSK … /* * RK3308_ALC_L_DIG_CON07 - REG: 0x005c + ch * 0xc0 * RK3308_ALC_R_DIG_CON07 - REG: 0x009c + ch * 0xc0 */ #define RK3308_AGC_LO_8BITS_AGC_MIN_MSK … /* * RK3308_ALC_L_DIG_CON08 - REG: 0x0060 + ch * 0xc0 * RK3308_ALC_R_DIG_CON08 - REG: 0x00a0 + ch * 0xc0 */ #define RK3308_AGC_HI_8BITS_AGC_MIN_MSK … /* * RK3308_ALC_L_DIG_CON09 - REG: 0x0064 + ch * 0xc0 * RK3308_ALC_R_DIG_CON09 - REG: 0x00a4 + ch * 0xc0 */ #define RK3308_AGC_FUNC_SEL … #define RK3308_AGC_MAX_GAIN_PGA_MAX … #define RK3308_AGC_MAX_GAIN_PGA_MIN … #define RK3308_AGC_MAX_GAIN_PGA_SFT … #define RK3308_AGC_MAX_GAIN_PGA_MSK … #define RK3308_AGC_MIN_GAIN_PGA_MAX … #define RK3308_AGC_MIN_GAIN_PGA_MIN … #define RK3308_AGC_MIN_GAIN_PGA_SFT … #define RK3308_AGC_MIN_GAIN_PGA_MSK … /* * RK3308_ALC_L_DIG_CON12 - REG: 0x0068 + ch * 0xc0 * RK3308_ALC_R_DIG_CON12 - REG: 0x00a8 + ch * 0xc0 */ #define RK3308_AGC_GAIN_MSK … /* RK3308_DAC_DIG_CON01 - REG: 0x0304 */ #define RK3308_DAC_I2S_LRC_POL_REVERSAL … #define RK3308_DAC_I2S_VALID_LEN_SFT … #define RK3308_DAC_I2S_VALID_LEN_MSK … #define RK3308_DAC_I2S_VALID_LEN_32BITS … #define RK3308_DAC_I2S_VALID_LEN_24BITS … #define RK3308_DAC_I2S_VALID_LEN_20BITS … #define RK3308_DAC_I2S_VALID_LEN_16BITS … #define RK3308_DAC_I2S_MODE_SFT … #define RK3308_DAC_I2S_MODE_MSK … #define RK3308_DAC_I2S_MODE_PCM … #define RK3308_DAC_I2S_MODE_I2S … #define RK3308_DAC_I2S_MODE_LJ … #define RK3308_DAC_I2S_MODE_RJ … #define RK3308_DAC_I2S_LR_SWAP … /* RK3308_DAC_DIG_CON02 - REG: 0x0308 */ #define RK3308BS_DAC_IO_MODE_MASTER … #define RK3308BS_DAC_MODE_MASTER … #define RK3308_DAC_IO_MODE_MASTER … #define RK3308_DAC_MODE_MASTER … #define RK3308_DAC_I2S_FRAME_LEN_SFT … #define RK3308_DAC_I2S_FRAME_LEN_MSK … #define RK3308_DAC_I2S_FRAME_32BITS … #define RK3308_DAC_I2S_FRAME_24BITS … #define RK3308_DAC_I2S_FRAME_20BITS … #define RK3308_DAC_I2S_FRAME_16BITS … #define RK3308_DAC_I2S_WORK … #define RK3308_DAC_I2S_BIT_CLK_POL_REVERSAL … /* RK3308_DAC_DIG_CON03 - REG: 0x030C */ #define RK3308_DAC_L_CH_BIST_SFT … #define RK3308_DAC_L_CH_BIST_MSK … #define RK3308_DAC_L_CH_BIST_LEFT … #define RK3308_DAC_L_CH_BIST_CUBE … #define RK3308_DAC_L_CH_BIST_SINE … #define RK3308_DAC_L_CH_BIST_RIGHT … #define RK3308_DAC_R_CH_BIST_SFT … #define RK3308_DAC_R_CH_BIST_MSK … #define RK3308_DAC_R_CH_BIST_LEFT … #define RK3308_DAC_R_CH_BIST_CUBE … #define RK3308_DAC_R_CH_BIST_SINE … #define RK3308_DAC_R_CH_BIST_RIGHT … /* RK3308_DAC_DIG_CON04 - REG: 0x0310 */ /* Versions up to B: */ #define RK3308_DAC_MODULATOR_GAIN_SFT … #define RK3308_DAC_MODULATOR_GAIN_MSK … #define RK3308_DAC_CIC_IF_GAIN_SFT … #define RK3308_DAC_CIC_IF_GAIN_MSK … /* Version C: */ #define RK3308BS_DAC_DIG_GAIN_SFT … #define RK3308BS_DAC_DIG_GAIN_MSK … #define RK3308BS_DAC_DIG_GAIN_0DB … /* RK3308BS_ADC_DIG_CON05..06 (Version C only) */ #define RK3308_ADC_DIG_VOL_CON_x_SFT … #define RK3308_ADC_DIG_VOL_CON_x_MSK … #define RK3308_ADC_DIG_VOL_CON_x_0DB … /* RK3308_DAC_DIG_CON05 - REG: 0x0314 */ #define RK3308_DAC_L_REG_CTL_INDATA … #define RK3308_DAC_R_REG_CTL_INDATA … /* RK3308_DAC_DIG_CON10 - REG: 0x0328 */ #define RK3308_DAC_DATA_HI4(x) … /* RK3308_DAC_DIG_CON11 - REG: 0x032c */ #define RK3308_DAC_DATA_LO8(x) … /* RK3308_ADC_ANA_CON00 - REG: 0x0340 */ #define RK3308_ADC_CH1_CH2_MIC_ALL_MSK … #define RK3308_ADC_CH1_CH2_MIC_ALL … #define RK3308_ADC_CH2_MIC_UNMUTE … #define RK3308_ADC_CH2_MIC_WORK … #define RK3308_ADC_CH2_MIC_EN … #define RK3308_ADC_CH2_BUF_REF_EN … #define RK3308_ADC_CH1_MIC_UNMUTE … #define RK3308_ADC_CH1_MIC_WORK … #define RK3308_ADC_CH1_MIC_EN … #define RK3308_ADC_CH1_BUF_REF_EN … /* RK3308_ADC_ANA_CON01 - REG: 0x0344 * * The PGA of MIC-INs: * - HW version A: * 0x0 - MIC1~MIC8 0 dB (recommended when ADC used as loopback) * 0x3 - MIC1~MIC8 20 dB (recommended when ADC used as MIC input) * - HW version B: * 0x0 - MIC1~MIC8 0 dB * 0x1 - MIC1~MIC8 6.6 dB * 0x2 - MIC1~MIC8 13 dB * 0x3 - MIC1~MIC8 20 dB */ #define RK3308_ADC_CH2_MIC_GAIN_MAX … #define RK3308_ADC_CH2_MIC_GAIN_MIN … #define RK3308_ADC_CH2_MIC_GAIN_SFT … #define RK3308_ADC_CH2_MIC_GAIN_MSK … #define RK3308_ADC_CH2_MIC_GAIN_20DB … #define RK3308_ADC_CH2_MIC_GAIN_13DB … #define RK3308_ADC_CH2_MIC_GAIN_6_6DB … #define RK3308_ADC_CH2_MIC_GAIN_0DB … #define RK3308_ADC_CH1_MIC_GAIN_MAX … #define RK3308_ADC_CH1_MIC_GAIN_MIN … #define RK3308_ADC_CH1_MIC_GAIN_SFT … #define RK3308_ADC_CH1_MIC_GAIN_MSK … #define RK3308_ADC_CH1_MIC_GAIN_20DB … #define RK3308_ADC_CH1_MIC_GAIN_13DB … #define RK3308_ADC_CH1_MIC_GAIN_6_6DB … #define RK3308_ADC_CH1_MIC_GAIN_0DB … /* RK3308_ADC_ANA_CON02 - REG: 0x0348 */ #define RK3308_ADC_CH2_ZEROCROSS_DET_EN … #define RK3308_ADC_CH2_ALC_WORK … #define RK3308_ADC_CH2_ALC_EN … #define RK3308_ADC_CH1_ZEROCROSS_DET_EN … #define RK3308_ADC_CH1_ALC_WORK … #define RK3308_ADC_CH1_ALC_EN … /* RK3308_ADC_ANA_CON03 - REG: 0x034c */ #define RK3308_ADC_CH1_ALC_GAIN_MAX … #define RK3308_ADC_CH1_ALC_GAIN_MIN … #define RK3308_ADC_CH1_ALC_GAIN_SFT … #define RK3308_ADC_CH1_ALC_GAIN_MSK … #define RK3308_ADC_CH1_ALC_GAIN_0DB … /* RK3308_ADC_ANA_CON04 - REG: 0x0350 */ #define RK3308_ADC_CH2_ALC_GAIN_MAX … #define RK3308_ADC_CH2_ALC_GAIN_MIN … #define RK3308_ADC_CH2_ALC_GAIN_SFT … #define RK3308_ADC_CH2_ALC_GAIN_MSK … #define RK3308_ADC_CH2_ALC_GAIN_0DB … /* RK3308_ADC_ANA_CON05 - REG: 0x0354 */ #define RK3308_ADC_CH2_ADC_WORK … #define RK3308_ADC_CH2_ADC_EN … #define RK3308_ADC_CH2_CLK_EN … #define RK3308_ADC_CH1_ADC_WORK … #define RK3308_ADC_CH1_ADC_EN … #define RK3308_ADC_CH1_CLK_EN … /* RK3308_ADC_ANA_CON06 - REG: 0x0358 */ #define RK3308_ADC_CURRENT_EN … /* RK3308_ADC_ANA_CON07 - REG: 0x035c */ /* Note: The register configuration is only valid for ADC2 */ #define RK3308_ADC_CH2_IN_SEL_SFT … #define RK3308_ADC_CH2_IN_SEL_MSK … #define RK3308_ADC_CH2_IN_LINEIN_MIC … #define RK3308_ADC_CH2_IN_LINEIN … #define RK3308_ADC_CH2_IN_MIC … #define RK3308_ADC_CH2_IN_NONE … /* Note: The register configuration is only valid for ADC1 */ #define RK3308_ADC_CH1_IN_SEL_SFT … #define RK3308_ADC_CH1_IN_SEL_MSK … #define RK3308_ADC_CH1_IN_LINEIN_MIC … #define RK3308_ADC_CH1_IN_LINEIN … #define RK3308_ADC_CH1_IN_MIC … #define RK3308_ADC_CH1_IN_NONE … #define RK3308_ADC_MIC_BIAS_BUF_EN … #define RK3308_ADC_LEVEL_RANGE_MICBIAS_MAX … #define RK3308_ADC_LEVEL_RANGE_MICBIAS_SFT … #define RK3308_ADC_LEVEL_RANGE_MICBIAS_MSK … /* RK3308_ADC_ANA_CON08 - REG: 0x0360 */ #define RK3308_ADC_MICBIAS_CURRENT_EN … /* RK3308_ADC_ANA_CON10 - REG: 0x0368 */ #define RK3308_ADC_REF_EN … #define RK3308_ADC_CURRENT_CHARGE_SFT … #define RK3308_ADC_CURRENT_CHARGE_MSK … /* RK3308_ADC_ANA_CON11 - REG: 0x036c */ #define RK3308_ADC_ALCR_CON_GAIN_PGAR_EN … #define RK3308_ADC_ALCL_CON_GAIN_PGAL_EN … /* RK3308_DAC_ANA_CON00 - REG: 0x0440 */ #define RK3308_DAC_HEADPHONE_DET_EN … #define RK3308_DAC_CURRENT_EN … /* RK3308_DAC_ANA_CON01 - REG: 0x0444 */ #define RK3308_DAC_BUF_REF_R_EN … #define RK3308_DAC_BUF_REF_L_EN … #define RK3308_DAC_HPOUT_POP_SOUND_R_SFT … #define RK3308_DAC_HPOUT_POP_SOUND_L_SFT … // unshifted values for both L and R: #define RK3308_DAC_HPOUT_POP_SOUND_x_MSK … #define RK3308_DAC_HPOUT_POP_SOUND_x_WORK … #define RK3308_DAC_HPOUT_POP_SOUND_x_INIT … /* RK3308_DAC_ANA_CON02 - REG: 0x0448 */ #define RK3308_DAC_R_DAC_WORK … #define RK3308_DAC_R_DAC_EN … #define RK3308_DAC_R_CLK_EN … #define RK3308_DAC_R_REF_EN … #define RK3308_DAC_L_DAC_WORK … #define RK3308_DAC_L_DAC_EN … #define RK3308_DAC_L_CLK_EN … #define RK3308_DAC_L_REF_EN … /* RK3308_DAC_ANA_CON03 - REG: 0x044c */ #define RK3308_DAC_R_HPOUT_WORK … #define RK3308_DAC_R_HPOUT_EN … #define RK3308_DAC_R_HPOUT_MUTE_SFT … #define RK3308_DAC_L_HPOUT_WORK … #define RK3308_DAC_L_HPOUT_EN … #define RK3308_DAC_L_HPOUT_MUTE_SFT … /* RK3308_DAC_ANA_CON04 - REG: 0x0450 */ #define RK3308_DAC_x_LINEOUT_GAIN_MAX … #define RK3308_DAC_R_LINEOUT_GAIN_SFT … #define RK3308_DAC_R_LINEOUT_GAIN_MSK … #define RK3308_DAC_R_LINEOUT_GAIN_0DB … #define RK3308_DAC_R_LINEOUT_GAIN_NDB_1_5 … #define RK3308_DAC_R_LINEOUT_GAIN_NDB_3 … #define RK3308_DAC_R_LINEOUT_GAIN_NDB_6 … #define RK3308_DAC_R_LINEOUT_MUTE_SFT … #define RK3308_DAC_R_LINEOUT_EN … #define RK3308_DAC_L_LINEOUT_GAIN_SFT … #define RK3308_DAC_L_LINEOUT_GAIN_MSK … #define RK3308_DAC_L_LINEOUT_GAIN_0DB … #define RK3308_DAC_L_LINEOUT_GAIN_NDB_1_5 … #define RK3308_DAC_L_LINEOUT_GAIN_NDB_3 … #define RK3308_DAC_L_LINEOUT_GAIN_NDB_6 … #define RK3308_DAC_L_LINEOUT_MUTE_SFT … #define RK3308_DAC_L_LINEOUT_EN … /* RK3308_DAC_ANA_CON05 - REG: 0x0454, step is 1.5db */ /* RK3308_DAC_ANA_CON06 - REG: 0x0458, step is 1.5db */ #define RK3308_DAC_x_HPOUT_GAIN_MAX … #define RK3308_DAC_x_HPOUT_GAIN_SFT … #define RK3308_DAC_x_HPOUT_GAIN_MSK … #define RK3308_DAC_x_HPOUT_GAIN_MIN … /* RK3308_DAC_ANA_CON07 - REG: 0x045c */ #define RK3308_DAC_R_HPOUT_DRV_SFT … #define RK3308_DAC_R_HPOUT_DRV_MSK … #define RK3308_DAC_L_HPOUT_DRV_SFT … #define RK3308_DAC_L_HPOUT_DRV_MSK … /* RK3308_DAC_ANA_CON08 - REG: 0x0460 */ #define RK3308_DAC_R_LINEOUT_DRV_SFT … #define RK3308_DAC_R_LINEOUT_DRV_MSK … #define RK3308_DAC_L_LINEOUT_DRV_SFT … #define RK3308_DAC_L_LINEOUT_DRV_MSK … /* RK3308_DAC_ANA_CON12 - REG: 0x0470 */ #define RK3308_DAC_R_HPMIX_SEL_SFT … #define RK3308_DAC_R_HPMIX_SEL_MSK … #define RK3308_DAC_R_HPMIX_LINEIN_I2S … #define RK3308_DAC_R_HPMIX_LINEIN … #define RK3308_DAC_R_HPMIX_I2S … #define RK3308_DAC_R_HPMIX_NONE … #define RK3308_DAC_L_HPMIX_SEL_SFT … #define RK3308_DAC_L_HPMIX_SEL_MSK … #define RK3308_DAC_L_HPMIX_LINEIN_I2S … #define RK3308_DAC_L_HPMIX_LINEIN … #define RK3308_DAC_L_HPMIX_I2S … #define RK3308_DAC_L_HPMIX_NONE … #define RK3308_DAC_x_HPMIX_GAIN_MIN … #define RK3308_DAC_x_HPMIX_GAIN_MAX … #define RK3308_DAC_R_HPMIX_GAIN_SFT … #define RK3308_DAC_R_HPMIX_GAIN_MSK … #define RK3308_DAC_R_HPMIX_GAIN_0DB … #define RK3308_DAC_R_HPMIX_GAIN_NDB_6 … #define RK3308_DAC_L_HPMIX_GAIN_SFT … #define RK3308_DAC_L_HPMIX_GAIN_MSK … #define RK3308_DAC_L_HPMIX_GAIN_0DB … #define RK3308_DAC_L_HPMIX_GAIN_NDB_6 … /* RK3308_DAC_ANA_CON13 - REG: 0x0474 */ #define RK3308_DAC_R_HPMIX_UNMUTE … #define RK3308_DAC_R_HPMIX_WORK … #define RK3308_DAC_R_HPMIX_EN … #define RK3308_DAC_L_HPMIX_UNMUTE … #define RK3308_DAC_L_HPMIX_WORK … #define RK3308_DAC_L_HPMIX_EN … /* RK3308_DAC_ANA_CON14 - REG: 0x0478 */ #define RK3308_DAC_VCM_LINEOUT_EN … #define RK3308_DAC_CURRENT_CHARGE_SFT … #define RK3308_DAC_CURRENT_CHARGE_MSK … /* RK3308_DAC_ANA_CON15 - REG: 0x047C */ #define RK3308_DAC_LINEOUT_POP_SOUND_R_SFT … #define RK3308_DAC_LINEOUT_POP_SOUND_R_MSK … #define RK3308_DAC_R_SEL_DC_FROM_INTERNAL … #define RK3308_DAC_R_SEL_DC_FROM_VCM … #define RK3308_DAC_R_SEL_LINEOUT_FROM_INTERNAL … #define RK3308_DAC_LINEOUT_POP_SOUND_L_SFT … #define RK3308_DAC_LINEOUT_POP_SOUND_L_MSK … #define RK3308_DAC_L_SEL_DC_FROM_INTERNAL … #define RK3308_DAC_L_SEL_DC_FROM_VCM … #define RK3308_DAC_L_SEL_LINEOUT_FROM_INTERNAL … #endif /* __RK3308_CODEC_H__ */
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