/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include <linux/mmu_context.h> #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" #include "oss/osssys_6_0_0_offset.h" #include "oss/osssys_6_0_0_sh_mask.h" #include "soc15_common.h" #include "soc15d.h" #include "v11_structs.h" #include "soc21.h" #include <uapi/linux/kfd_ioctl.h> enum hqd_dequeue_request_type { … }; static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, uint32_t queue, uint32_t vmid) { … } static void unlock_srbm(struct amdgpu_device *adev) { … } static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) { … } static uint64_t get_queue_mask(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id) { … } static void release_queue(struct amdgpu_device *adev) { … } static void program_sh_mem_settings_v11(struct amdgpu_device *adev, uint32_t vmid, uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases, uint32_t inst) { … } static int set_pasid_vmid_mapping_v11(struct amdgpu_device *adev, unsigned int pasid, unsigned int vmid, uint32_t inst) { … } static int init_interrupts_v11(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t inst) { … } static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) { … } static inline struct v11_compute_mqd *get_mqd(void *mqd) { … } static inline struct v11_sdma_mqd *get_sdma_mqd(void *mqd) { … } static int hqd_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t __user *wptr, uint32_t wptr_shift, uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) { … } static int hiq_mqd_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id, uint32_t queue_id, uint32_t doorbell_off, uint32_t inst) { … } static int hqd_dump_v11(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) { … } static int hqd_sdma_load_v11(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) { … } static int hqd_sdma_dump_v11(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) { … } static bool hqd_is_occupied_v11(struct amdgpu_device *adev, uint64_t queue_address, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) { … } static bool hqd_sdma_is_occupied_v11(struct amdgpu_device *adev, void *mqd) { … } static int hqd_destroy_v11(struct amdgpu_device *adev, void *mqd, enum kfd_preempt_type reset_type, unsigned int utimeout, uint32_t pipe_id, uint32_t queue_id, uint32_t inst) { … } static int hqd_sdma_destroy_v11(struct amdgpu_device *adev, void *mqd, unsigned int utimeout) { … } static int wave_control_execute_v11(struct amdgpu_device *adev, uint32_t gfx_index_val, uint32_t sq_cmd, uint32_t inst) { … } static void set_vm_context_page_table_base_v11(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base) { … } /* * Returns TRAP_EN, EXCP_EN and EXCP_REPLACE. * * restore_dbg_registers is ignored here but is a general interface requirement * for devices that support GFXOFF and where the RLC save/restore list * does not support hw registers for debugging i.e. the driver has to manually * initialize the debug mode registers after it has disabled GFX off during the * debug session. */ static uint32_t kgd_gfx_v11_enable_debug_trap(struct amdgpu_device *adev, bool restore_dbg_registers, uint32_t vmid) { … } /* Returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ static uint32_t kgd_gfx_v11_disable_debug_trap(struct amdgpu_device *adev, bool keep_trap_enabled, uint32_t vmid) { … } static int kgd_gfx_v11_validate_trap_override_request(struct amdgpu_device *adev, uint32_t trap_override, uint32_t *trap_mask_supported) { … } static uint32_t trap_mask_map_sw_to_hw(uint32_t mask) { … } static uint32_t trap_mask_map_hw_to_sw(uint32_t mask) { … } /* Returns TRAP_EN, EXCP_EN and EXCP_REPLACE. */ static uint32_t kgd_gfx_v11_set_wave_launch_trap_override(struct amdgpu_device *adev, uint32_t vmid, uint32_t trap_override, uint32_t trap_mask_bits, uint32_t trap_mask_request, uint32_t *trap_mask_prev, uint32_t kfd_dbg_trap_cntl_prev) { … } static uint32_t kgd_gfx_v11_set_wave_launch_mode(struct amdgpu_device *adev, uint8_t wave_launch_mode, uint32_t vmid) { … } #define TCP_WATCH_STRIDE … static uint32_t kgd_gfx_v11_set_address_watch(struct amdgpu_device *adev, uint64_t watch_address, uint32_t watch_address_mask, uint32_t watch_id, uint32_t watch_mode, uint32_t debug_vmid, uint32_t inst) { … } static uint32_t kgd_gfx_v11_clear_address_watch(struct amdgpu_device *adev, uint32_t watch_id) { … } const struct kfd2kgd_calls gfx_v11_kfd2kgd = …;
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