#ifndef __SMU_V11_0_H__
#define __SMU_V11_0_H__
#include "amdgpu_smu.h"
#define SMU11_DRIVER_IF_VERSION_INV …
#define SMU11_DRIVER_IF_VERSION_ARCT …
#define SMU11_DRIVER_IF_VERSION_NV10 …
#define SMU11_DRIVER_IF_VERSION_NV12 …
#define SMU11_DRIVER_IF_VERSION_NV14 …
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid …
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder …
#define SMU11_DRIVER_IF_VERSION_VANGOGH …
#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish …
#define SMU11_DRIVER_IF_VERSION_Beige_Goby …
#define SMU11_DRIVER_IF_VERSION_Cyan_Skillfish …
#define MP0_Public …
#define MP0_SRAM …
#define MP1_Public …
#define MP1_SRAM …
#define smnMP1_FIRMWARE_FLAGS …
#define smnMP0_FW_INTF …
#define smnMP1_PUB_CTRL …
#define TEMP_RANGE_MIN …
#define TEMP_RANGE_MAX …
#define SMU11_TOOL_SIZE …
#define MAX_DPM_LEVELS …
#define MAX_PCIE_CONF …
#define CTF_OFFSET_EDGE …
#define CTF_OFFSET_HOTSPOT …
#define CTF_OFFSET_MEM …
#define LINK_WIDTH_MAX …
#define LINK_SPEED_MAX …
static const __maybe_unused uint16_t link_width[] = …;
static const
struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = …;
struct smu_11_0_max_sustainable_clocks { … };
struct smu_11_0_dpm_clk_level { … };
struct smu_11_0_dpm_table { … };
struct smu_11_0_pcie_table { … };
struct smu_11_0_dpm_tables { … };
struct smu_11_0_dpm_context { … };
enum smu_11_0_power_state { … };
struct smu_11_0_power_context { … };
struct smu_11_5_power_context { … };
#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
int smu_v11_0_init_microcode(struct smu_context *smu);
void smu_v11_0_fini_microcode(struct smu_context *smu);
int smu_v11_0_load_microcode(struct smu_context *smu);
int smu_v11_0_init_smc_tables(struct smu_context *smu);
int smu_v11_0_fini_smc_tables(struct smu_context *smu);
int smu_v11_0_init_power(struct smu_context *smu);
int smu_v11_0_fini_power(struct smu_context *smu);
int smu_v11_0_check_fw_status(struct smu_context *smu);
int smu_v11_0_setup_pptable(struct smu_context *smu);
int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
int smu_v11_0_check_fw_version(struct smu_context *smu);
int smu_v11_0_set_driver_table_location(struct smu_context *smu);
int smu_v11_0_set_tool_table_location(struct smu_context *smu);
int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
int smu_v11_0_system_features_control(struct smu_context *smu,
bool en);
int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
int smu_v11_0_set_allowed_mask(struct smu_context *smu);
int smu_v11_0_notify_display_change(struct smu_context *smu);
int smu_v11_0_get_current_power_limit(struct smu_context *smu,
uint32_t *power_limit);
int smu_v11_0_set_power_limit(struct smu_context *smu,
enum smu_ppt_limit_type limit_type,
uint32_t limit);
int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
int
smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
struct pp_display_clock_request
*clock_req);
uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context *smu);
int
smu_v11_0_set_fan_control_mode(struct smu_context *smu,
uint32_t mode);
int smu_v11_0_set_fan_speed_pwm(struct smu_context *smu,
uint32_t speed);
int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
uint32_t speed);
int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
uint32_t *speed);
int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
uint32_t *speed);
int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
uint32_t pstate);
int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
int smu_v11_0_register_irq_handler(struct smu_context *smu);
int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
struct pp_smu_nv_clock_table *max_clocks);
int smu_v11_0_get_bamaco_support(struct smu_context *smu);
enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
int smu_v11_0_baco_enter(struct smu_context *smu);
int smu_v11_0_baco_exit(struct smu_context *smu);
int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
enum smu_baco_seq baco_seq);
int smu_v11_0_mode1_reset(struct smu_context *smu);
int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max);
int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
uint32_t max);
int smu_v11_0_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level);
int smu_v11_0_set_power_source(struct smu_context *smu,
enum smu_power_src_type power_src);
int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
enum smu_clk_type clk_type,
uint16_t level,
uint32_t *value);
int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value);
int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
enum smu_clk_type clk_type,
struct smu_11_0_dpm_table *single_dpm_table);
int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min_value,
uint32_t *max_value);
int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);
uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);
uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
bool enablement);
int smu_v11_0_deep_sleep_control(struct smu_context *smu,
bool enablement);
void smu_v11_0_interrupt_work(struct smu_context *smu);
int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable);
int smu_v11_0_restore_user_od_settings(struct smu_context *smu);
void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu);
#endif
#endif