/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ #define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ // *** IMPORTANT *** // SMU TEAM: Always increment the interface version if // any structure is changed in this file #define SMU11_DRIVER_IF_VERSION … #define PPTABLE_Sienna_Cichlid_SMU_VERSION … #define NUM_GFXCLK_DPM_LEVELS … #define NUM_SMNCLK_DPM_LEVELS … #define NUM_SOCCLK_DPM_LEVELS … #define NUM_MP0CLK_DPM_LEVELS … #define NUM_DCLK_DPM_LEVELS … #define NUM_VCLK_DPM_LEVELS … #define NUM_DCEFCLK_DPM_LEVELS … #define NUM_PHYCLK_DPM_LEVELS … #define NUM_DISPCLK_DPM_LEVELS … #define NUM_PIXCLK_DPM_LEVELS … #define NUM_DTBCLK_DPM_LEVELS … #define NUM_UCLK_DPM_LEVELS … #define NUM_MP1CLK_DPM_LEVELS … #define NUM_LINK_LEVELS … #define NUM_FCLK_DPM_LEVELS … #define NUM_XGMI_LEVELS … #define NUM_XGMI_PSTATE_LEVELS … #define NUM_OD_FAN_MAX_POINTS … #define MAX_GFXCLK_DPM_LEVEL … #define MAX_SMNCLK_DPM_LEVEL … #define MAX_SOCCLK_DPM_LEVEL … #define MAX_MP0CLK_DPM_LEVEL … #define MAX_DCLK_DPM_LEVEL … #define MAX_VCLK_DPM_LEVEL … #define MAX_DCEFCLK_DPM_LEVEL … #define MAX_DISPCLK_DPM_LEVEL … #define MAX_PIXCLK_DPM_LEVEL … #define MAX_PHYCLK_DPM_LEVEL … #define MAX_DTBCLK_DPM_LEVEL … #define MAX_UCLK_DPM_LEVEL … #define MAX_MP1CLK_DPM_LEVEL … #define MAX_LINK_LEVEL … #define MAX_FCLK_DPM_LEVEL … //Gemini Modes #define PPSMC_GeminiModeNone … #define PPSMC_GeminiModeMaster … #define PPSMC_GeminiModeSlave … // Feature Control Defines // DPM #define FEATURE_DPM_PREFETCHER_BIT … #define FEATURE_DPM_GFXCLK_BIT … #define FEATURE_DPM_GFX_GPO_BIT … #define FEATURE_DPM_UCLK_BIT … #define FEATURE_DPM_FCLK_BIT … #define FEATURE_DPM_SOCCLK_BIT … #define FEATURE_DPM_MP0CLK_BIT … #define FEATURE_DPM_LINK_BIT … #define FEATURE_DPM_DCEFCLK_BIT … #define FEATURE_DPM_XGMI_BIT … #define FEATURE_MEM_VDDCI_SCALING_BIT … #define FEATURE_MEM_MVDD_SCALING_BIT … //Idle #define FEATURE_DS_GFXCLK_BIT … #define FEATURE_DS_SOCCLK_BIT … #define FEATURE_DS_FCLK_BIT … #define FEATURE_DS_LCLK_BIT … #define FEATURE_DS_DCEFCLK_BIT … #define FEATURE_DS_UCLK_BIT … #define FEATURE_GFX_ULV_BIT … #define FEATURE_FW_DSTATE_BIT … #define FEATURE_GFXOFF_BIT … #define FEATURE_BACO_BIT … #define FEATURE_MM_DPM_PG_BIT … #define FEATURE_SPARE_23_BIT … //Throttler/Response #define FEATURE_PPT_BIT … #define FEATURE_TDC_BIT … #define FEATURE_APCC_PLUS_BIT … #define FEATURE_GTHR_BIT … #define FEATURE_ACDC_BIT … #define FEATURE_VR0HOT_BIT … #define FEATURE_VR1HOT_BIT … #define FEATURE_FW_CTF_BIT … #define FEATURE_FAN_CONTROL_BIT … #define FEATURE_THERMAL_BIT … #define FEATURE_GFX_DCS_BIT … //VF #define FEATURE_RM_BIT … #define FEATURE_LED_DISPLAY_BIT … //Other #define FEATURE_GFX_SS_BIT … #define FEATURE_OUT_OF_BAND_MONITOR_BIT … #define FEATURE_TEMP_DEPENDENT_VMIN_BIT … #define FEATURE_MMHUB_PG_BIT … #define FEATURE_ATHUB_PG_BIT … #define FEATURE_APCC_DFLL_BIT … #define FEATURE_DF_SUPERV_BIT … #define FEATURE_RSMU_SMN_CG_BIT … #define FEATURE_DF_CSTATE_BIT … #define FEATURE_2_STEP_PSTATE_BIT … #define FEATURE_SMNCLK_DPM_BIT … #define FEATURE_PERLINK_GMIDOWN_BIT … #define FEATURE_GFX_EDC_BIT … #define FEATURE_GFX_PER_PART_VMIN_BIT … #define FEATURE_SMART_SHIFT_BIT … #define FEATURE_APT_BIT … #define FEATURE_SPARE_53_BIT … #define FEATURE_SPARE_54_BIT … #define FEATURE_SPARE_55_BIT … #define FEATURE_SPARE_56_BIT … #define FEATURE_SPARE_57_BIT … #define FEATURE_SPARE_58_BIT … #define FEATURE_SPARE_59_BIT … #define FEATURE_SPARE_60_BIT … #define FEATURE_SPARE_61_BIT … #define FEATURE_SPARE_62_BIT … #define FEATURE_SPARE_63_BIT … #define NUM_FEATURES … //For use with feature control messages FEATURE_PWR_DOMAIN_e; // Debug Overrides Bitmask #define DPM_OVERRIDE_DISABLE_FCLK_PID … #define DPM_OVERRIDE_DISABLE_UCLK_PID … #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK … #define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_FCLK … #define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_FCLK … #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK … #define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK … #define DPM_OVERRIDE_DISABLE_VOLT_LINK_DCE_FCLK … #define DPM_OVERRIDE_DISABLE_VOLT_LINK_MP0_SOCCLK … #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN … #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ … #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK … #define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER … #define DPM_OVERRIDE_DISABLE_VCN_PG … #define DPM_OVERRIDE_DISABLE_FMAX_VMAX … #define DPM_OVERRIDE_ENABLE_eGPU_USB_WA … // VR Mapping Bit Defines #define VR_MAPPING_VR_SELECT_MASK … #define VR_MAPPING_VR_SELECT_SHIFT … #define VR_MAPPING_PLANE_SELECT_MASK … #define VR_MAPPING_PLANE_SELECT_SHIFT … // PSI Bit Defines #define PSI_SEL_VR0_PLANE0_PSI0 … #define PSI_SEL_VR0_PLANE0_PSI1 … #define PSI_SEL_VR0_PLANE1_PSI0 … #define PSI_SEL_VR0_PLANE1_PSI1 … #define PSI_SEL_VR1_PLANE0_PSI0 … #define PSI_SEL_VR1_PLANE0_PSI1 … #define PSI_SEL_VR1_PLANE1_PSI0 … #define PSI_SEL_VR1_PLANE1_PSI1 … // Throttler Control/Status Bits #define THROTTLER_PADDING_BIT … #define THROTTLER_TEMP_EDGE_BIT … #define THROTTLER_TEMP_HOTSPOT_BIT … #define THROTTLER_TEMP_MEM_BIT … #define THROTTLER_TEMP_VR_GFX_BIT … #define THROTTLER_TEMP_VR_MEM0_BIT … #define THROTTLER_TEMP_VR_MEM1_BIT … #define THROTTLER_TEMP_VR_SOC_BIT … #define THROTTLER_TEMP_LIQUID0_BIT … #define THROTTLER_TEMP_LIQUID1_BIT … #define THROTTLER_TEMP_PLX_BIT … #define THROTTLER_TDC_GFX_BIT … #define THROTTLER_TDC_SOC_BIT … #define THROTTLER_PPT0_BIT … #define THROTTLER_PPT1_BIT … #define THROTTLER_PPT2_BIT … #define THROTTLER_PPT3_BIT … #define THROTTLER_FIT_BIT … #define THROTTLER_PPM_BIT … #define THROTTLER_APCC_BIT … #define THROTTLER_COUNT … // FW DState Features Control Bits // FW DState Features Control Bits #define FW_DSTATE_SOC_ULV_BIT … #define FW_DSTATE_G6_HSR_BIT … #define FW_DSTATE_G6_PHY_VDDCI_OFF_BIT … #define FW_DSTATE_MP0_DS_BIT … #define FW_DSTATE_SMN_DS_BIT … #define FW_DSTATE_MP1_DS_BIT … #define FW_DSTATE_MP1_WHISPER_MODE_BIT … #define FW_DSTATE_SOC_LIV_MIN_BIT … #define FW_DSTATE_SOC_PLL_PWRDN_BIT … #define FW_DSTATE_MEM_PLL_PWRDN_BIT … #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT … #define FW_DSTATE_MEM_PSI_BIT … #define FW_DSTATE_HSR_NON_STROBE_BIT … #define FW_DSTATE_MP0_ENTER_WFI_BIT … #define FW_DSTATE_SOC_ULV_MASK … #define FW_DSTATE_G6_HSR_MASK … #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK … #define FW_DSTATE_MP1_DS_MASK … #define FW_DSTATE_MP0_DS_MASK … #define FW_DSTATE_SMN_DS_MASK … #define FW_DSTATE_MP1_WHISPER_MODE_MASK … #define FW_DSTATE_SOC_LIV_MIN_MASK … #define FW_DSTATE_SOC_PLL_PWRDN_MASK … #define FW_DSTATE_MEM_PLL_PWRDN_MASK … #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_MASK … #define FW_DSTATE_MEM_PSI_MASK … #define FW_DSTATE_HSR_NON_STROBE_MASK … #define FW_DSTATE_MP0_ENTER_WFI_MASK … // GFX GPO Feature Contains PACE and DEM sub features #define GFX_GPO_PACE_BIT … #define GFX_GPO_DEM_BIT … #define GFX_GPO_PACE_MASK … #define GFX_GPO_DEM_MASK … #define GPO_UPDATE_REQ_UCLKDPM_MASK … #define GPO_UPDATE_REQ_FCLKDPM_MASK … #define GPO_UPDATE_REQ_MALLHIT_MASK … //LED Display Mask & Control Bits #define LED_DISPLAY_GFX_DPM_BIT … #define LED_DISPLAY_PCIE_BIT … #define LED_DISPLAY_ERROR_BIT … //RLC Pace Table total number of levels #define RLC_PACE_TABLE_NUM_LEVELS … #define SIENNA_CICHLID_UMC_CHANNEL_NUM … EccInfo_t; EccInfoTable_t; DRAM_BIT_WIDTH_TYPE_e; //I2C Interface #define NUM_I2C_CONTROLLERS … #define I2C_CONTROLLER_ENABLED … #define I2C_CONTROLLER_DISABLED … #define MAX_SW_I2C_COMMANDS … I2cControllerPort_e; I2cControllerName_e; I2cControllerThrottler_e; I2cControllerProtocol_e; I2cControllerConfig_t; I2cPort_e; I2cSpeed_e; I2cCmdType_e; FanMode_e; #define CMDCONFIG_STOP_BIT … #define CMDCONFIG_RESTART_BIT … #define CMDCONFIG_READWRITE_BIT … #define CMDCONFIG_STOP_MASK … #define CMDCONFIG_RESTART_MASK … #define CMDCONFIG_READWRITE_MASK … SwI2cCmd_t; //SW I2C Command Table SwI2cRequest_t; // SW I2C Request Table SwI2cRequestExternal_t; //D3HOT sequences D3HOTSequence_e; //THis is aligned with RSMU PGFSM Register Mapping PowerGatingMode_e; //This is aligned with RSMU PGFSM Register Mapping PowerGatingSettings_e; QuadraticInt_t; QuadraticFixedPoint_t; LinearInt_t; DroopInt_t; //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS … DfllDroopModelSelect_e; PiecewiseLinearDroopInt_t; GFXCLK_SOURCE_e; //Only Clks that have DPM descriptors are listed here PPCLK_e; VOLTAGE_MODE_e; AVFS_VOLTAGE_TYPE_e; UCLK_DIV_e; GpioIntPolarity_e; PwrConfig_e; XGMI_LINK_RATE_e; XGMI_LINK_WIDTH_e; DpmDescriptor_t; PPT_THROTTLER_e; TEMP_e; TDC_THROTTLER_e; CUSTOMER_VARIANT_e; // Used for 2-step UCLK DPM change workaround UclkDpmChangeRange_t; #pragma pack(push, 1) PPTable_t; #pragma pack(pop) PPTable_beige_goby_t; DriverSmuConfig_t; DriverSmuConfigExternal_t; OverDriveTable_t; OverDriveTableExternal_t; SmuMetrics_t; SmuMetrics_V2_t; SmuMetrics_V3_t; SmuMetrics_V4_t; SmuMetricsExternal_t; WatermarkRowGeneric_t; #define NUM_WM_RANGES … WM_CLOCK_e; WATERMARKS_FLAGS_e; Watermarks_t; WatermarksExternal_t; AvfsDebugTable_t; AvfsDebugTableExternal_t; AvfsFuseOverride_t; AvfsFuseOverrideExternal_t; DpmActivityMonitorCoeffInt_t; DpmActivityMonitorCoeffIntExternal_t; // Workload bits #define WORKLOAD_PPLIB_DEFAULT_BIT … #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT … #define WORKLOAD_PPLIB_POWER_SAVING_BIT … #define WORKLOAD_PPLIB_VIDEO_BIT … #define WORKLOAD_PPLIB_VR_BIT … #define WORKLOAD_PPLIB_COMPUTE_BIT … #define WORKLOAD_PPLIB_CUSTOM_BIT … #define WORKLOAD_PPLIB_W3D_BIT … #define WORKLOAD_PPLIB_COUNT … // These defines are used with the following messages: // SMC_MSG_TransferTableDram2Smu // SMC_MSG_TransferTableSmu2Dram // Table transfer status #define TABLE_TRANSFER_OK … #define TABLE_TRANSFER_FAILED … // Table types #define TABLE_PPTABLE … #define TABLE_WATERMARKS … #define TABLE_AVFS_PSM_DEBUG … #define TABLE_AVFS_FUSE_OVERRIDE … #define TABLE_PMSTATUSLOG … #define TABLE_SMU_METRICS … #define TABLE_DRIVER_SMU_CONFIG … #define TABLE_ACTIVITY_MONITOR_COEFF … #define TABLE_OVERDRIVE … #define TABLE_I2C_COMMANDS … #define TABLE_PACE … #define TABLE_ECCINFO … #define TABLE_COUNT … RlcPaceFlopsPerByteOverride_t; RlcPaceFlopsPerByteOverrideExternal_t; // These defines are used with the SMC_MSG_SetUclkFastSwitch message. #define UCLK_SWITCH_SLOW … #define UCLK_SWITCH_FAST … #define UCLK_SWITCH_DUMMY … #endif
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