linux/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

/*
 * Copyright 2019 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#define SWSMU_CODE_LAYER_L2

#include <linux/firmware.h>
#include <linux/pci.h>
#include <linux/i2c.h>
#include "amdgpu.h"
#include "amdgpu_dpm.h"
#include "amdgpu_smu.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "amdgpu_atombios.h"
#include "smu_v11_0.h"
#include "smu11_driver_if_sienna_cichlid.h"
#include "soc15_common.h"
#include "atom.h"
#include "sienna_cichlid_ppt.h"
#include "smu_v11_0_7_pptable.h"
#include "smu_v11_0_7_ppsmc.h"
#include "nbio/nbio_2_3_offset.h"
#include "nbio/nbio_2_3_sh_mask.h"
#include "thm/thm_11_0_2_offset.h"
#include "thm/thm_11_0_2_sh_mask.h"
#include "mp/mp_11_0_offset.h"
#include "mp/mp_11_0_sh_mask.h"

#include "asic_reg/mp/mp_11_0_sh_mask.h"
#include "amdgpu_ras.h"
#include "smu_cmn.h"

/*
 * DO NOT use these for err/warn/info/debug messages.
 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
 * They are more MGPU friendly.
 */
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug

#define FEATURE_MASK(feature) …
#define SMC_DPM_FEATURE …

#define SMU_11_0_7_GFX_BUSY_THRESHOLD …

#define GET_PPTABLE_MEMBER(field, member) …

/* STB FIFO depth is in 64bit units */
#define SIENNA_CICHLID_STB_DEPTH_UNIT_BYTES …

/*
 * SMU support ECCTABLE since version 58.70.0,
 * use this to check whether ECCTABLE feature is supported.
 */
#define SUPPORT_ECCTABLE_SMU_VERSION …

static int get_table_size(struct smu_context *smu)
{ … }

static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = …;

static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = …;

static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = …;

static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = …;

static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = …;

static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = …;

static const uint8_t sienna_cichlid_throttler_map[] = …;

static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
				  uint32_t *feature_mask, uint32_t num)
{ … }

static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
{ … }

static void sienna_cichlid_check_fan_support(struct smu_context *smu)
{ … }

static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
{ … }

static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
{ … }

static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
{ … }

static int sienna_cichlid_patch_pptable_quirk(struct smu_context *smu)
{ … }

static int sienna_cichlid_setup_pptable(struct smu_context *smu)
{ … }

static int sienna_cichlid_tables_init(struct smu_context *smu)
{ … }

static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
							   bool use_metrics_v3,
							   bool use_metrics_v2)
{ … }

static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
						   enum SMU_11_0_7_ODFEATURE_CAP cap)
{ … }

static int sienna_cichlid_get_power_limit(struct smu_context *smu,
					  uint32_t *current_power_limit,
					  uint32_t *default_power_limit,
					  uint32_t *max_power_limit,
					  uint32_t *min_power_limit)
{ … }

static void sienna_cichlid_get_smartshift_power_percentage(struct smu_context *smu,
					uint32_t *apu_percent,
					uint32_t *dgpu_percent)
{ … }

static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
					       MetricsMember_t member,
					       uint32_t *value)
{ … }

static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
{ … }

static void sienna_cichlid_stb_init(struct smu_context *smu);

static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
{ … }

static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
{ … }

static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
{ … }

static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
{ … }

static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
				       enum smu_clk_type clk_type,
				       uint32_t *value)
{ … }

static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
{ … }

static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
						enum SMU_11_0_7_ODSETTING_ID setting,
						uint32_t *min, uint32_t *max)
{ … }

static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
			enum smu_clk_type clk_type, char *buf)
{ … }

static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
				   enum smu_clk_type clk_type, uint32_t mask)
{ … }

static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
{ … }

static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
{ … }

static int sienna_cichlid_display_config_changed(struct smu_context *smu)
{ … }

static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
{ … }

static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
					    uint32_t *speed)
{ … }

static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
{ … }

static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
{ … }

static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
{ … }

static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
{ … }

static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
					       struct pp_smu_wm_range_sets *clock_ranges)
{ … }

static int sienna_cichlid_read_sensor(struct smu_context *smu,
				 enum amd_pp_sensors sensor,
				 void *data, uint32_t *size)
{ … }

static void sienna_cichlid_get_unique_id(struct smu_context *smu)
{ … }

static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
{ … }

static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
						struct smu_temperature_range *range)
{ … }

static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
						bool disable_memory_clock_switch)
{ … }

static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
						 uint8_t pcie_gen_cap,
						 uint8_t pcie_width_cap)
{ … }

static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
				enum smu_clk_type clk_type,
				uint32_t *min, uint32_t *max)
{ … }

static void sienna_cichlid_dump_od_table(struct smu_context *smu,
					 OverDriveTable_t *od_table)
{ … }

static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
{ … }

static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
						 struct smu_11_0_7_overdrive_table *od_table,
						 enum SMU_11_0_7_ODSETTING_ID setting,
						 uint32_t value)
{ … }

static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
					    enum PP_OD_DPM_TABLE_COMMAND type,
					    long input[], uint32_t size)
{ … }

static int sienna_cichlid_restore_user_od_settings(struct smu_context *smu)
{ … }

static int sienna_cichlid_run_btc(struct smu_context *smu)
{ … }

static int sienna_cichlid_baco_enter(struct smu_context *smu)
{ … }

static int sienna_cichlid_baco_exit(struct smu_context *smu)
{ … }

static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
{ … }

static void beige_goby_dump_pptable(struct smu_context *smu)
{ … }

static void sienna_cichlid_dump_pptable(struct smu_context *smu)
{ … }

static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
				   struct i2c_msg *msg, int num_msgs)
{ … }

static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
{ … }


static const struct i2c_algorithm sienna_cichlid_i2c_algo = …;

static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = …;

static int sienna_cichlid_i2c_control_init(struct smu_context *smu)
{ … }

static void sienna_cichlid_i2c_control_fini(struct smu_context *smu)
{ … }

static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
					      void **table)
{ … }

static int sienna_cichlid_check_ecc_table_support(struct smu_context *smu)
{ … }

static ssize_t sienna_cichlid_get_ecc_info(struct smu_context *smu,
					void *table)
{ … }
static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
{ … }

static int sienna_cichlid_gpo_control(struct smu_context *smu,
				      bool enablement)
{ … }

static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
{ … }

static int sienna_cichlid_system_features_control(struct smu_context *smu,
						  bool en)
{ … }

static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
					enum pp_mp1_state mp1_state)
{ … }

static void sienna_cichlid_stb_init(struct smu_context *smu)
{ … }

static int sienna_cichlid_get_default_config_table_settings(struct smu_context *smu,
							    struct config_table_setting *table)
{ … }

static int sienna_cichlid_set_config_table(struct smu_context *smu,
					   struct config_table_setting *table)
{ … }

static int sienna_cichlid_stb_get_data_direct(struct smu_context *smu,
					      void *buf,
					      uint32_t size)
{ … }

static bool sienna_cichlid_is_mode2_reset_supported(struct smu_context *smu)
{ … }

static int sienna_cichlid_mode2_reset(struct smu_context *smu)
{ … }

static const struct pptable_funcs sienna_cichlid_ppt_funcs = …;

void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
{ … }