/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #define SWSMU_CODE_LAYER_L3 #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_smu.h" #include "atomfirmware.h" #include "amdgpu_atomfirmware.h" #include "amdgpu_atombios.h" #include "smu_v12_0.h" #include "soc15_common.h" #include "atom.h" #include "smu_cmn.h" #include "asic_reg/mp/mp_12_0_0_offset.h" #include "asic_reg/mp/mp_12_0_0_sh_mask.h" #include "asic_reg/smuio/smuio_12_0_0_offset.h" #include "asic_reg/smuio/smuio_12_0_0_sh_mask.h" /* * DO NOT use these for err/warn/info/debug messages. * Use dev_err, dev_warn, dev_info and dev_dbg instead. * They are more MGPU friendly. */ #undef pr_err #undef pr_warn #undef pr_info #undef pr_debug // because some SMU12 based ASICs use older ip offset tables // we should undefine this register from the smuio12 header // to prevent confusion down the road #undef mmPWR_MISC_CNTL_STATUS #define smnMP1_FIRMWARE_FLAGS … int smu_v12_0_check_fw_status(struct smu_context *smu) { … } int smu_v12_0_check_fw_version(struct smu_context *smu) { … } int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate) { … } int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable) { … } /** * smu_v12_0_get_gfxoff_status - get gfxoff status * * @smu: amdgpu_device pointer * * This function will be used to get gfxoff status * * Returns 0=GFXOFF(default). * Returns 1=Transition out of GFX State. * Returns 2=Not in GFXOFF. * Returns 3=Transition into GFXOFF. */ uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu) { … } int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable) { … } int smu_v12_0_fini_smc_tables(struct smu_context *smu) { … } int smu_v12_0_set_default_dpm_tables(struct smu_context *smu) { … } int smu_v12_0_mode2_reset(struct smu_context *smu) { … } int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max) { … } int smu_v12_0_set_driver_table_location(struct smu_context *smu) { … } static int smu_v12_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, uint8_t clk_id, uint8_t syspll_id, uint32_t *clk_freq) { … } int smu_v12_0_get_vbios_bootup_values(struct smu_context *smu) { … }