/* * Copyright 2021 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #define SWSMU_CODE_LAYER_L2 #include <linux/firmware.h> #include <linux/pci.h> #include <linux/i2c.h> #include "amdgpu.h" #include "amdgpu_smu.h" #include "atomfirmware.h" #include "amdgpu_atomfirmware.h" #include "amdgpu_atombios.h" #include "smu_v13_0.h" #include "smu13_driver_if_v13_0_0.h" #include "soc15_common.h" #include "atom.h" #include "smu_v13_0_0_ppt.h" #include "smu_v13_0_0_pptable.h" #include "smu_v13_0_0_ppsmc.h" #include "nbio/nbio_4_3_0_offset.h" #include "nbio/nbio_4_3_0_sh_mask.h" #include "mp/mp_13_0_0_offset.h" #include "mp/mp_13_0_0_sh_mask.h" #include "asic_reg/mp/mp_13_0_0_sh_mask.h" #include "smu_cmn.h" #include "amdgpu_ras.h" /* * DO NOT use these for err/warn/info/debug messages. * Use dev_err, dev_warn, dev_info and dev_dbg instead. * They are more MGPU friendly. */ #undef pr_err #undef pr_warn #undef pr_info #undef pr_debug #define to_amdgpu_device(x) … #define FEATURE_MASK(feature) … #define SMC_DPM_FEATURE … #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE … #define mmMP1_SMN_C2PMSG_66 … #define mmMP1_SMN_C2PMSG_66_BASE_IDX … #define mmMP1_SMN_C2PMSG_82 … #define mmMP1_SMN_C2PMSG_82_BASE_IDX … #define mmMP1_SMN_C2PMSG_90 … #define mmMP1_SMN_C2PMSG_90_BASE_IDX … #define mmMP1_SMN_C2PMSG_75 … #define mmMP1_SMN_C2PMSG_75_BASE_IDX … #define mmMP1_SMN_C2PMSG_53 … #define mmMP1_SMN_C2PMSG_53_BASE_IDX … #define mmMP1_SMN_C2PMSG_54 … #define mmMP1_SMN_C2PMSG_54_BASE_IDX … #define DEBUGSMC_MSG_Mode1Reset … /* * SMU_v13_0_10 supports ECCTABLE since version 80.34.0, * use this to check ECCTABLE feature whether support */ #define SUPPORT_ECCTABLE_SMU_13_0_10_VERSION … #define PP_OD_FEATURE_GFXCLK_FMIN … #define PP_OD_FEATURE_GFXCLK_FMAX … #define PP_OD_FEATURE_UCLK_FMIN … #define PP_OD_FEATURE_UCLK_FMAX … #define PP_OD_FEATURE_GFX_VF_CURVE … #define PP_OD_FEATURE_FAN_CURVE_TEMP … #define PP_OD_FEATURE_FAN_CURVE_PWM … #define PP_OD_FEATURE_FAN_ACOUSTIC_LIMIT … #define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET … #define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE … #define PP_OD_FEATURE_FAN_MINIMUM_PWM … #define LINK_SPEED_MAX … static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = …; static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = …; static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = …; static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = …; static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = …; static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = …; static const uint8_t smu_v13_0_0_throttler_map[] = …; static int smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) { … } static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu) { … } static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu) { … } #ifndef atom_smc_dpm_info_table_13_0_0 struct atom_smc_dpm_info_table_13_0_0 { … }; #endif static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu) { … } static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu, void **table, uint32_t *size) { … } static int smu_v13_0_0_setup_pptable(struct smu_context *smu) { … } static int smu_v13_0_0_tables_init(struct smu_context *smu) { … } static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu) { … } static int smu_v13_0_0_init_smc_tables(struct smu_context *smu) { … } static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu) { … } static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu) { … } static void smu_v13_0_0_dump_pptable(struct smu_context *smu) { … } static int smu_v13_0_0_system_features_control(struct smu_context *smu, bool en) { … } static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics) { … } #define SMU_13_0_0_BUSY_THRESHOLD … static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu, MetricsMember_t member, uint32_t *value) { … } static int smu_v13_0_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max) { … } static int smu_v13_0_0_read_sensor(struct smu_context *smu, enum amd_pp_sensors sensor, void *data, uint32_t *size) { … } static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *value) { … } static bool smu_v13_0_0_is_od_feature_supported(struct smu_context *smu, int od_feature_bit) { … } static void smu_v13_0_0_get_od_setting_limits(struct smu_context *smu, int od_feature_bit, int32_t *min, int32_t *max) { … } static void smu_v13_0_0_dump_od_table(struct smu_context *smu, OverDriveTableExternal_t *od_table) { … } static int smu_v13_0_0_get_overdrive_table(struct smu_context *smu, OverDriveTableExternal_t *od_table) { … } static int smu_v13_0_0_upload_overdrive_table(struct smu_context *smu, OverDriveTableExternal_t *od_table) { … } static int smu_v13_0_0_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf) { … } static int smu_v13_0_0_od_restore_table_single(struct smu_context *smu, long input) { … } static int smu_v13_0_0_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size) { … } static int smu_v13_0_0_force_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask) { … } static const struct smu_temperature_range smu13_thermal_policy[] = …; static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu, struct smu_temperature_range *range) { … } static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu, void **table) { … } static void smu_v13_0_0_set_supported_od_feature_mask(struct smu_context *smu) { … } static int smu_v13_0_0_set_default_od_settings(struct smu_context *smu) { … } static int smu_v13_0_0_restore_user_od_settings(struct smu_context *smu) { … } static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu) { … } static void smu_v13_0_0_get_unique_id(struct smu_context *smu) { … } static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu, uint32_t *speed) { … } static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed) { … } static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu) { … } static int smu_v13_0_0_get_power_limit(struct smu_context *smu, uint32_t *current_power_limit, uint32_t *default_power_limit, uint32_t *max_power_limit, uint32_t *min_power_limit) { … } static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu, char *buf) { … } static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) { … } static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) { … } static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msg, int num_msgs) { … } static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap) { … } static const struct i2c_algorithm smu_v13_0_0_i2c_algo = …; static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = …; static int smu_v13_0_0_i2c_control_init(struct smu_context *smu) { … } static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu) { … } static int smu_v13_0_0_set_mp1_state(struct smu_context *smu, enum pp_mp1_state mp1_state) { … } static int smu_v13_0_0_set_df_cstate(struct smu_context *smu, enum pp_df_cstate state) { … } static void smu_v13_0_0_set_mode1_reset_param(struct smu_context *smu, uint32_t supported_version, uint32_t *param) { … } static int smu_v13_0_0_mode1_reset(struct smu_context *smu) { … } static int smu_v13_0_0_mode2_reset(struct smu_context *smu) { … } static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu) { … } static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu) { … } static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu, uint32_t size) { … } static int smu_v13_0_0_send_bad_mem_channel_flag(struct smu_context *smu, uint32_t size) { … } static int smu_v13_0_0_check_ecc_table_support(struct smu_context *smu) { … } static ssize_t smu_v13_0_0_get_ecc_info(struct smu_context *smu, void *table) { … } static bool smu_v13_0_0_wbrf_support_check(struct smu_context *smu) { … } static int smu_v13_0_0_set_power_limit(struct smu_context *smu, enum smu_ppt_limit_type limit_type, uint32_t limit) { … } static const struct pptable_funcs smu_v13_0_0_ppt_funcs = …; void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) { … }
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