/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef SMU13_DRIVER_IF_SMU_13_0_7_H #define SMU13_DRIVER_IF_SMU_13_0_7_H // *** IMPORTANT *** // PMFW TEAM: Always increment the interface version on any change to this file #define SMU13_0_7_DRIVER_IF_VERSION … //Increment this version if SkuTable_t or BoardTable_t change #define PPTABLE_VERSION … #define NUM_GFXCLK_DPM_LEVELS … #define NUM_SOCCLK_DPM_LEVELS … #define NUM_MP0CLK_DPM_LEVELS … #define NUM_DCLK_DPM_LEVELS … #define NUM_VCLK_DPM_LEVELS … #define NUM_DISPCLK_DPM_LEVELS … #define NUM_DPPCLK_DPM_LEVELS … #define NUM_DPREFCLK_DPM_LEVELS … #define NUM_DCFCLK_DPM_LEVELS … #define NUM_DTBCLK_DPM_LEVELS … #define NUM_UCLK_DPM_LEVELS … #define NUM_LINK_LEVELS … #define NUM_FCLK_DPM_LEVELS … #define NUM_OD_FAN_MAX_POINTS … // Feature Control Defines #define FEATURE_FW_DATA_READ_BIT … #define FEATURE_DPM_GFXCLK_BIT … #define FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT … #define FEATURE_DPM_UCLK_BIT … #define FEATURE_DPM_FCLK_BIT … #define FEATURE_DPM_SOCCLK_BIT … #define FEATURE_DPM_MP0CLK_BIT … #define FEATURE_DPM_LINK_BIT … #define FEATURE_DPM_DCN_BIT … #define FEATURE_VMEMP_SCALING_BIT … #define FEATURE_VDDIO_MEM_SCALING_BIT … #define FEATURE_DS_GFXCLK_BIT … #define FEATURE_DS_SOCCLK_BIT … #define FEATURE_DS_FCLK_BIT … #define FEATURE_DS_LCLK_BIT … #define FEATURE_DS_DCFCLK_BIT … #define FEATURE_DS_UCLK_BIT … #define FEATURE_GFX_ULV_BIT … #define FEATURE_FW_DSTATE_BIT … #define FEATURE_GFXOFF_BIT … #define FEATURE_BACO_BIT … #define FEATURE_MM_DPM_BIT … #define FEATURE_SOC_MPCLK_DS_BIT … #define FEATURE_BACO_MPCLK_DS_BIT … #define FEATURE_THROTTLERS_BIT … #define FEATURE_SMARTSHIFT_BIT … #define FEATURE_GTHR_BIT … #define FEATURE_ACDC_BIT … #define FEATURE_VR0HOT_BIT … #define FEATURE_FW_CTF_BIT … #define FEATURE_FAN_CONTROL_BIT … #define FEATURE_GFX_DCS_BIT … #define FEATURE_GFX_READ_MARGIN_BIT … #define FEATURE_LED_DISPLAY_BIT … #define FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT … #define FEATURE_OUT_OF_BAND_MONITOR_BIT … #define FEATURE_OPTIMIZED_VMIN_BIT … #define FEATURE_GFX_IMU_BIT … #define FEATURE_BOOT_TIME_CAL_BIT … #define FEATURE_GFX_PCC_DFLL_BIT … #define FEATURE_SOC_CG_BIT … #define FEATURE_DF_CSTATE_BIT … #define FEATURE_GFX_EDC_BIT … #define FEATURE_BOOT_POWER_OPT_BIT … #define FEATURE_CLOCK_POWER_DOWN_BYPASS_BIT … #define FEATURE_DS_VCN_BIT … #define FEATURE_BACO_CG_BIT … #define FEATURE_MEM_TEMP_READ_BIT … #define FEATURE_ATHUB_MMHUB_PG_BIT … #define FEATURE_SOC_PCC_BIT … #define FEATURE_EDC_PWRBRK_BIT … #define FEATURE_SPARE_51_BIT … #define FEATURE_SPARE_52_BIT … #define FEATURE_SPARE_53_BIT … #define FEATURE_SPARE_54_BIT … #define FEATURE_SPARE_55_BIT … #define FEATURE_SPARE_56_BIT … #define FEATURE_SPARE_57_BIT … #define FEATURE_SPARE_58_BIT … #define FEATURE_SPARE_59_BIT … #define FEATURE_SPARE_60_BIT … #define FEATURE_SPARE_61_BIT … #define FEATURE_SPARE_62_BIT … #define FEATURE_SPARE_63_BIT … #define NUM_FEATURES … #define ALLOWED_FEATURE_CTRL_DEFAULT … #define ALLOWED_FEATURE_CTRL_SCPM … //For use with feature control messages FEATURE_PWR_DOMAIN_e; // Debug Overrides Bitmask #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK … #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK … #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK … #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK … #define DEBUG_OVERRIDE_DISABLE_FAST_FCLK_TIMER … #define DEBUG_OVERRIDE_DISABLE_VCN_PG … #define DEBUG_OVERRIDE_DISABLE_FMAX_VMAX … #define DEBUG_OVERRIDE_DISABLE_IMU_FW_CHECKS … #define DEBUG_OVERRIDE_DISABLE_D0i2_REENTRY_HSR_TIMER_CHECK … #define DEBUG_OVERRIDE_DISABLE_DFLL … #define DEBUG_OVERRIDE_ENABLE_RLC_VF_BRINGUP_MODE … #define DEBUG_OVERRIDE_DFLL_MASTER_MODE … #define DEBUG_OVERRIDE_ENABLE_PROFILING_MODE … // VR Mapping Bit Defines #define VR_MAPPING_VR_SELECT_MASK … #define VR_MAPPING_VR_SELECT_SHIFT … #define VR_MAPPING_PLANE_SELECT_MASK … #define VR_MAPPING_PLANE_SELECT_SHIFT … // PSI Bit Defines #define PSI_SEL_VR0_PLANE0_PSI0 … #define PSI_SEL_VR0_PLANE0_PSI1 … #define PSI_SEL_VR0_PLANE1_PSI0 … #define PSI_SEL_VR0_PLANE1_PSI1 … #define PSI_SEL_VR1_PLANE0_PSI0 … #define PSI_SEL_VR1_PLANE0_PSI1 … #define PSI_SEL_VR1_PLANE1_PSI0 … #define PSI_SEL_VR1_PLANE1_PSI1 … SVI_PSI_e; // Throttler Control/Status Bits #define THROTTLER_TEMP_EDGE_BIT … #define THROTTLER_TEMP_HOTSPOT_BIT … #define THROTTLER_TEMP_HOTSPOT_G_BIT … #define THROTTLER_TEMP_HOTSPOT_M_BIT … #define THROTTLER_TEMP_MEM_BIT … #define THROTTLER_TEMP_VR_GFX_BIT … #define THROTTLER_TEMP_VR_MEM0_BIT … #define THROTTLER_TEMP_VR_MEM1_BIT … #define THROTTLER_TEMP_VR_SOC_BIT … #define THROTTLER_TEMP_VR_U_BIT … #define THROTTLER_TEMP_LIQUID0_BIT … #define THROTTLER_TEMP_LIQUID1_BIT … #define THROTTLER_TEMP_PLX_BIT … #define THROTTLER_TDC_GFX_BIT … #define THROTTLER_TDC_SOC_BIT … #define THROTTLER_TDC_U_BIT … #define THROTTLER_PPT0_BIT … #define THROTTLER_PPT1_BIT … #define THROTTLER_PPT2_BIT … #define THROTTLER_PPT3_BIT … #define THROTTLER_FIT_BIT … #define THROTTLER_GFX_APCC_PLUS_BIT … #define THROTTLER_COUNT … // FW DState Features Control Bits #define FW_DSTATE_SOC_ULV_BIT … #define FW_DSTATE_G6_HSR_BIT … #define FW_DSTATE_G6_PHY_VMEMP_OFF_BIT … #define FW_DSTATE_SMN_DS_BIT … #define FW_DSTATE_MP1_WHISPER_MODE_BIT … #define FW_DSTATE_SOC_LIV_MIN_BIT … #define FW_DSTATE_SOC_PLL_PWRDN_BIT … #define FW_DSTATE_MEM_PLL_PWRDN_BIT … #define FW_DSTATE_MALL_ALLOC_BIT … #define FW_DSTATE_MEM_PSI_BIT … #define FW_DSTATE_HSR_NON_STROBE_BIT … #define FW_DSTATE_MP0_ENTER_WFI_BIT … #define FW_DSTATE_U_ULV_BIT … #define FW_DSTATE_MALL_FLUSH_BIT … #define FW_DSTATE_SOC_PSI_BIT … #define FW_DSTATE_U_PSI_BIT … #define FW_DSTATE_UCP_DS_BIT … #define FW_DSTATE_CSRCLK_DS_BIT … #define FW_DSTATE_MMHUB_INTERLOCK_BIT … #define FW_DSTATE_D0i3_2_QUIET_FW_BIT … #define FW_DSTATE_CLDO_PRG_BIT … #define FW_DSTATE_DF_PLL_PWRDN_BIT … #define FW_DSTATE_U_LOW_PWR_MODE_EN_BIT … #define FW_DSTATE_GFX_PSI6_BIT … #define FW_DSTATE_GFX_VR_PWR_STAGE_BIT … //LED Display Mask & Control Bits #define LED_DISPLAY_GFX_DPM_BIT … #define LED_DISPLAY_PCIE_BIT … #define LED_DISPLAY_ERROR_BIT … #define MEM_TEMP_READ_OUT_OF_BAND_BIT … #define MEM_TEMP_READ_IN_BAND_REFRESH_BIT … #define MEM_TEMP_READ_IN_BAND_DUMMY_PSTATE_BIT … SMARTSHIFT_VERSION_e; FOPT_CALC_e; DRAM_BIT_WIDTH_TYPE_e; //I2C Interface #define NUM_I2C_CONTROLLERS … #define I2C_CONTROLLER_ENABLED … #define I2C_CONTROLLER_DISABLED … #define MAX_SW_I2C_COMMANDS … I2cControllerPort_e; I2cControllerName_e; I2cControllerThrottler_e; I2cControllerProtocol_e; I2cControllerConfig_t; I2cPort_e; I2cSpeed_e; I2cCmdType_e; #define CMDCONFIG_STOP_BIT … #define CMDCONFIG_RESTART_BIT … #define CMDCONFIG_READWRITE_BIT … #define CMDCONFIG_STOP_MASK … #define CMDCONFIG_RESTART_MASK … #define CMDCONFIG_READWRITE_MASK … SwI2cCmd_t; //SW I2C Command Table SwI2cRequest_t; // SW I2C Request Table SwI2cRequestExternal_t; EccInfo_t; EccInfoTable_t; //D3HOT sequences D3HOTSequence_e; //This is aligned with RSMU PGFSM Register Mapping PowerGatingMode_e; //This is aligned with RSMU PGFSM Register Mapping PowerGatingSettings_e; QuadraticInt_t; LinearInt_t; DroopInt_t; DCS_ARCH_e; //Only Clks that have DPM descriptors are listed here PPCLK_e; VOLTAGE_MODE_e; AVFS_VOLTAGE_TYPE_e; AVFS_TEMP_e; AVFS_D_e; UCLK_DIV_e; GpioIntPolarity_e; PwrConfig_e; DpmDescriptor_t; PPT_THROTTLER_e; TEMP_e; TDC_THROTTLER_e; SVI_PLANE_e; PMFW_VOLT_PLANE_e; CUSTOMER_VARIANT_e; POWER_SOURCE_e; MEM_VENDOR_e; PP_GRTAVFS_HW_FUSE_e; PP_GRTAVFS_FW_COMMON_FUSE_e; PP_GRTAVFS_FW_SEP_FUSE_e; #define PP_NUM_RTAVFS_PWL_ZONES … // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 // Slope Q1.7, Offset Q1.2 SviTelemetryScale_t; #define PP_NUM_OD_VF_CURVE_POINTS … #define PP_OD_FEATURE_GFX_VF_CURVE_BIT … #define PP_OD_FEATURE_PPT_BIT … #define PP_OD_FEATURE_FAN_CURVE_BIT … #define PP_OD_FEATURE_GFXCLK_BIT … #define PP_OD_FEATURE_UCLK_BIT … #define PP_OD_FEATURE_ZERO_FAN_BIT … #define PP_OD_FEATURE_TEMPERATURE_BIT … #define PP_OD_FEATURE_COUNT … PP_OD_POWER_FEATURE_e; FanMode_e; OverDriveTable_t; OverDriveTableExternal_t; OverDriveLimits_t; BOARD_GPIO_TYPE_e; #define INVALID_BOARD_GPIO … BootValues_t; MsgLimits_t; DriverReportedClocks_t; AvfsDcBtcParams_t; AvfsFuseOverride_t; SkuTable_t; BoardTable_t; #pragma pack(push, 1) PPTable_t; #pragma pack(pop) DriverSmuConfig_t; DriverSmuConfigExternal_t; DriverInfoTable_t; SmuMetrics_t; SmuMetricsExternal_t; WatermarkRowGeneric_t; #define NUM_WM_RANGES … WATERMARKS_FLAGS_e; Watermarks_t; WatermarksExternal_t; AvfsDebugTable_t; AvfsDebugTableExternal_t; DpmActivityMonitorCoeffInt_t; DpmActivityMonitorCoeffIntExternal_t; // Workload bits #define WORKLOAD_PPLIB_DEFAULT_BIT … #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT … #define WORKLOAD_PPLIB_POWER_SAVING_BIT … #define WORKLOAD_PPLIB_VIDEO_BIT … #define WORKLOAD_PPLIB_VR_BIT … #define WORKLOAD_PPLIB_COMPUTE_BIT … #define WORKLOAD_PPLIB_CUSTOM_BIT … #define WORKLOAD_PPLIB_WINDOW_3D_BIT … #define WORKLOAD_PPLIB_COUNT … // These defines are used with the following messages: // SMC_MSG_TransferTableDram2Smu // SMC_MSG_TransferTableSmu2Dram // Table transfer status #define TABLE_TRANSFER_OK … #define TABLE_TRANSFER_FAILED … #define TABLE_TRANSFER_PENDING … // Table types #define TABLE_PPTABLE … #define TABLE_COMBO_PPTABLE … #define TABLE_WATERMARKS … #define TABLE_AVFS_PSM_DEBUG … #define TABLE_PMSTATUSLOG … #define TABLE_SMU_METRICS … #define TABLE_DRIVER_SMU_CONFIG … #define TABLE_ACTIVITY_MONITOR_COEFF … #define TABLE_OVERDRIVE … #define TABLE_I2C_COMMANDS … #define TABLE_DRIVER_INFO … #define TABLE_ECCINFO … #define TABLE_WIFIBAND … #define TABLE_COUNT … //IH Interupt ID #define IH_INTERRUPT_ID_TO_DRIVER … #define IH_INTERRUPT_CONTEXT_ID_BACO … #define IH_INTERRUPT_CONTEXT_ID_AC … #define IH_INTERRUPT_CONTEXT_ID_DC … #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 … #define IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 … #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING … #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL … #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY … #endif
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