/* * Copyright 2022 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef __SMU13_DRIVER_IF_V13_0_4_H__ #define __SMU13_DRIVER_IF_V13_0_4_H__ // *** IMPORTANT *** // SMU TEAM: Always increment the interface version if // any structure is changed in this file #define SMU13_0_4_DRIVER_IF_VERSION … FloatInIntFormat_t; DSPCLK_e; DisplayClockTable_t; WatermarkRowGeneric_t; #define NUM_WM_RANGES … #define WM_PSTATE_CHG … #define WM_RETRAINING … WM_CLOCK_e; Watermarks_t; CUSTOM_DPM_SETTING_e; DpmActivityMonitorCoeffExt_t; CustomDpmSettings_t; #define NUM_DCFCLK_DPM_LEVELS … #define NUM_DISPCLK_DPM_LEVELS … #define NUM_DPPCLK_DPM_LEVELS … #define NUM_SOCCLK_DPM_LEVELS … #define NUM_VCN_DPM_LEVELS … #define NUM_SOC_VOLTAGE_LEVELS … #define NUM_DF_PSTATE_LEVELS … DfPstateTable_t; //Freq in MHz //Voltage in milli volts with 2 fractional bits DpmClocks_t; // Throttler Status Bitmask #define THROTTLER_STATUS_BIT_SPL … #define THROTTLER_STATUS_BIT_FPPT … #define THROTTLER_STATUS_BIT_SPPT … #define THROTTLER_STATUS_BIT_SPPT_APU … #define THROTTLER_STATUS_BIT_THM_CORE … #define THROTTLER_STATUS_BIT_THM_GFX … #define THROTTLER_STATUS_BIT_THM_SOC … #define THROTTLER_STATUS_BIT_TDC_VDD … #define THROTTLER_STATUS_BIT_TDC_SOC … #define THROTTLER_STATUS_BIT_PROCHOT_CPU … #define THROTTLER_STATUS_BIT_PROCHOT_GFX … #define THROTTLER_STATUS_BIT_EDC_CPU … #define THROTTLER_STATUS_BIT_EDC_GFX … SmuMetrics_t; PmfInfo_t; //ISP tile definitions TILE_NUM_e; // Tile Selection (Based on arguments) #define TILE_SEL_ISPX … #define TILE_SEL_ISPM … #define TILE_SEL_ISPC … #define TILE_SEL_ISPPRE … #define TILE_SEL_ISPPOST0 … #define TILE_SEL_ISPPOST1 … // Mask for ISP tiles in PGFSM PWR Status Registers //Bit[1:0] maps to ISPX, (ISPX) //Bit[3:2] maps to ISPM, (ISPM) //Bit[5:4] maps to ISPCORE, (ISPCORE) //Bit[7:6] maps to ISPPRE, (ISPPRE) //Bit[9:8] maps to POST, (ISPPOST #define TILE_ISPX_MASK … #define TILE_ISPM_MASK … #define TILE_ISPC_MASK … #define TILE_ISPPRE_MASK … #define TILE_ISPPOST0_MASK … #define TILE_ISPPOST1_MASK … // Workload bits #define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT … #define WORKLOAD_PPLIB_VIDEO_BIT … #define WORKLOAD_PPLIB_VR_BIT … #define WORKLOAD_PPLIB_COMPUTE_BIT … #define WORKLOAD_PPLIB_CUSTOM_BIT … #define WORKLOAD_PPLIB_COUNT … #define TABLE_BIOS_IF … #define TABLE_WATERMARKS … #define TABLE_CUSTOM_DPM … #define TABLE_SPARE1 … #define TABLE_DPMCLOCKS … #define TABLE_MOMENTARY_PM … #define TABLE_MODERN_STDBY … #define TABLE_SMU_METRICS … #define TABLE_INFRASTRUCTURE_LIMITS … #define TABLE_COUNT … #endif
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