#include "smu_types.h"
#define SWSMU_CODE_LAYER_L2
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_v13_0.h"
#include "smu13_driver_if_v13_0_4.h"
#include "smu_v13_0_4_ppt.h"
#include "smu_v13_0_4_ppsmc.h"
#include "smu_v13_0_4_pmfw.h"
#include "smu_cmn.h"
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug
#define mmMP1_SMN_C2PMSG_66 …
#define mmMP1_SMN_C2PMSG_66_BASE_IDX …
#define mmMP1_SMN_C2PMSG_82 …
#define mmMP1_SMN_C2PMSG_82_BASE_IDX …
#define mmMP1_SMN_C2PMSG_90 …
#define mmMP1_SMN_C2PMSG_90_BASE_IDX …
#define FEATURE_MASK(feature) …
#define SMU_13_0_4_UMD_PSTATE_GFXCLK …
#define SMU_13_0_4_UMD_PSTATE_SOCCLK …
#define SMU_13_0_4_UMD_PSTATE_FCLK …
#define SMC_DPM_FEATURE …
static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = …;
static struct cmn2asic_mapping smu_v13_0_4_feature_mask_map[SMU_FEATURE_COUNT] = …;
static struct cmn2asic_mapping smu_v13_0_4_table_map[SMU_TABLE_COUNT] = …;
static int smu_v13_0_4_init_smc_tables(struct smu_context *smu)
{ … }
static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu)
{ … }
static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
{ … }
static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
{ … }
static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu,
void **table)
{ … }
static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu,
MetricsMember_t member,
uint32_t *value)
{ … }
static int smu_v13_0_4_get_current_clk_freq(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value)
{ … }
static int smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t dpm_level,
uint32_t *freq)
{ … }
static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *count)
{ … }
static int smu_v13_0_4_print_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type, char *buf)
{ … }
static int smu_v13_0_4_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
{ … }
static int smu_v13_0_4_set_watermarks_table(struct smu_context *smu,
struct pp_smu_wm_range_sets *clock_ranges)
{ … }
static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu,
enum smu_clk_type clk_type)
{ … }
static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min,
uint32_t *max)
{ … }
static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
uint32_t max)
{ … }
static int smu_v13_0_4_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask)
{ … }
static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum smu_clk_type clk_type,
uint32_t *min_clk,
uint32_t *max_clk)
{ … }
static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{ … }
static int smu_v13_0_4_mode2_reset(struct smu_context *smu)
{ … }
static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
{ … }
static const struct pptable_funcs smu_v13_0_4_ppt_funcs = …;
static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu)
{ … }
void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
{ … }