#ifndef __SMU_V14_0_H__
#define __SMU_V14_0_H__
#include "amdgpu_smu.h"
#define SMU14_DRIVER_IF_VERSION_INV …
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 …
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 …
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 …
#define FEATURE_MASK(feature) …
#define MP0_Public …
#define MP0_SRAM …
#define MP1_Public …
#define MP1_SRAM …
#define smnMP1_FIRMWARE_FLAGS_14_0_0 …
#define smnMP1_FIRMWARE_FLAGS …
#define smnMP1_PUB_CTRL …
#define MAX_DPM_LEVELS …
#define MAX_PCIE_CONF …
#define SMU14_TOOL_SIZE …
#define CTF_OFFSET_EDGE …
#define CTF_OFFSET_HOTSPOT …
#define CTF_OFFSET_MEM …
extern const int decoded_link_speed[5];
extern const int decoded_link_width[7];
#define DECODE_GEN_SPEED(gen_speed_idx) …
#define DECODE_LANE_WIDTH(lane_width_idx) …
struct smu_14_0_max_sustainable_clocks { … };
struct smu_14_0_dpm_clk_level { … };
struct smu_14_0_dpm_table { … };
struct smu_14_0_pcie_table { … };
struct smu_14_0_dpm_tables { … };
struct smu_14_0_dpm_context { … };
enum smu_14_0_power_state { … };
struct smu_14_0_power_context { … };
#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
int smu_v14_0_init_microcode(struct smu_context *smu);
void smu_v14_0_fini_microcode(struct smu_context *smu);
int smu_v14_0_load_microcode(struct smu_context *smu);
int smu_v14_0_init_smc_tables(struct smu_context *smu);
int smu_v14_0_fini_smc_tables(struct smu_context *smu);
int smu_v14_0_init_power(struct smu_context *smu);
int smu_v14_0_fini_power(struct smu_context *smu);
int smu_v14_0_check_fw_status(struct smu_context *smu);
int smu_v14_0_setup_pptable(struct smu_context *smu);
int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu);
int smu_v14_0_check_fw_version(struct smu_context *smu);
int smu_v14_0_set_driver_table_location(struct smu_context *smu);
int smu_v14_0_set_tool_table_location(struct smu_context *smu);
int smu_v14_0_notify_memory_pool_location(struct smu_context *smu);
int smu_v14_0_system_features_control(struct smu_context *smu,
bool en);
int smu_v14_0_set_allowed_mask(struct smu_context *smu);
int smu_v14_0_notify_display_change(struct smu_context *smu);
int smu_v14_0_get_current_power_limit(struct smu_context *smu,
uint32_t *power_limit);
int smu_v14_0_set_power_limit(struct smu_context *smu,
enum smu_ppt_limit_type limit_type,
uint32_t limit);
int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable);
int smu_v14_0_register_irq_handler(struct smu_context *smu);
int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
enum smu_baco_seq baco_seq);
int smu_v14_0_get_bamaco_support(struct smu_context *smu);
enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu);
int smu_v14_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
int smu_v14_0_baco_enter(struct smu_context *smu);
int smu_v14_0_baco_exit(struct smu_context *smu);
int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max);
int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
uint32_t max);
int smu_v14_0_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level);
int smu_v14_0_set_power_source(struct smu_context *smu,
enum smu_power_src_type power_src);
int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
enum smu_clk_type clk_type,
struct smu_14_0_dpm_table *single_dpm_table);
int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
bool enablement);
int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg);
int smu_v14_0_set_vcn_enable(struct smu_context *smu,
bool enable);
int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
bool enable);
int smu_v14_0_init_pptable_microcode(struct smu_context *smu);
int smu_v14_0_run_btc(struct smu_context *smu);
int smu_v14_0_gpo_control(struct smu_context *smu,
bool enablement);
int smu_v14_0_deep_sleep_control(struct smu_context *smu,
bool enablement);
int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu);
int smu_v14_0_set_default_dpm_tables(struct smu_context *smu);
int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
void **table,
uint32_t *size,
uint32_t pptable_id);
int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long input[], uint32_t size);
void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu);
int smu_v14_0_enable_thermal_alert(struct smu_context *smu);
int smu_v14_0_disable_thermal_alert(struct smu_context *smu);
#endif
#endif