linux/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_0_ppt.c

/*
 * Copyright 2023 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#include "smu_types.h"
#define SWSMU_CODE_LAYER_L2

#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_v14_0.h"
#include "smu14_driver_if_v14_0_0.h"
#include "smu_v14_0_0_ppt.h"
#include "smu_v14_0_0_ppsmc.h"
#include "smu_v14_0_0_pmfw.h"
#include "smu_cmn.h"

/*
 * DO NOT use these for err/warn/info/debug messages.
 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
 * They are more MGPU friendly.
 */
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug

#define mmMP1_SMN_C2PMSG_66
#define mmMP1_SMN_C2PMSG_66_BASE_IDX

#define mmMP1_SMN_C2PMSG_82
#define mmMP1_SMN_C2PMSG_82_BASE_IDX

#define mmMP1_SMN_C2PMSG_90
#define mmMP1_SMN_C2PMSG_90_BASE_IDX

/* MALLPowerController message arguments (Defines for the Cache mode control) */
#define SMU_MALL_PMFW_CONTROL
#define SMU_MALL_DRIVER_CONTROL

/*
 * MALLPowerState message arguments
 * (Defines for the Allocate/Release Cache mode if in driver mode)
 */
#define SMU_MALL_EXIT_PG
#define SMU_MALL_ENTER_PG

#define SMU_MALL_PG_CONFIG_DEFAULT

#define SMU_14_0_0_UMD_PSTATE_GFXCLK
#define SMU_14_0_0_UMD_PSTATE_SOCCLK
#define SMU_14_0_0_UMD_PSTATE_FCLK

#define SMU_14_0_4_UMD_PSTATE_GFXCLK
#define SMU_14_0_4_UMD_PSTATE_SOCCLK

#define FEATURE_MASK(feature)
#define SMC_DPM_FEATURE

enum smu_mall_pg_config {};

static struct cmn2asic_msg_mapping smu_v14_0_0_message_map[SMU_MSG_MAX_COUNT] =;

static struct cmn2asic_mapping smu_v14_0_0_feature_mask_map[SMU_FEATURE_COUNT] =;

static struct cmn2asic_mapping smu_v14_0_0_table_map[SMU_TABLE_COUNT] =;

static int smu_v14_0_0_init_smc_tables(struct smu_context *smu)
{}

static int smu_v14_0_0_fini_smc_tables(struct smu_context *smu)
{}

static int smu_v14_0_0_system_features_control(struct smu_context *smu, bool en)
{}

static int smu_v14_0_0_get_smu_metrics_data(struct smu_context *smu,
					    MetricsMember_t member,
					    uint32_t *value)
{}

static int smu_v14_0_0_read_sensor(struct smu_context *smu,
				   enum amd_pp_sensors sensor,
				   void *data, uint32_t *size)
{}

static bool smu_v14_0_0_is_dpm_running(struct smu_context *smu)
{}

static int smu_v14_0_0_set_watermarks_table(struct smu_context *smu,
					    struct pp_smu_wm_range_sets *clock_ranges)
{}

static ssize_t smu_v14_0_0_get_gpu_metrics(struct smu_context *smu,
						void **table)
{}

static int smu_v14_0_0_mode2_reset(struct smu_context *smu)
{}

static int smu_v14_0_1_get_dpm_freq_by_index(struct smu_context *smu,
						enum smu_clk_type clk_type,
						uint32_t dpm_level,
						uint32_t *freq)
{}

static int smu_v14_0_0_get_dpm_freq_by_index(struct smu_context *smu,
						enum smu_clk_type clk_type,
						uint32_t dpm_level,
						uint32_t *freq)
{}

static int smu_v14_0_common_get_dpm_freq_by_index(struct smu_context *smu,
						enum smu_clk_type clk_type,
						uint32_t dpm_level,
						uint32_t *freq)
{}

static bool smu_v14_0_0_clk_dpm_is_enabled(struct smu_context *smu,
						enum smu_clk_type clk_type)
{}

static int smu_v14_0_1_get_dpm_ultimate_freq(struct smu_context *smu,
							enum smu_clk_type clk_type,
							uint32_t *min,
							uint32_t *max)
{}

static int smu_v14_0_0_get_dpm_ultimate_freq(struct smu_context *smu,
							enum smu_clk_type clk_type,
							uint32_t *min,
							uint32_t *max)
{}

static int smu_v14_0_common_get_dpm_ultimate_freq(struct smu_context *smu,
							enum smu_clk_type clk_type,
							uint32_t *min,
							uint32_t *max)
{}

static int smu_v14_0_0_get_current_clk_freq(struct smu_context *smu,
					    enum smu_clk_type clk_type,
					    uint32_t *value)
{}

static int smu_v14_0_1_get_dpm_level_count(struct smu_context *smu,
					   enum smu_clk_type clk_type,
					   uint32_t *count)
{}

static int smu_v14_0_0_get_dpm_level_count(struct smu_context *smu,
					   enum smu_clk_type clk_type,
					   uint32_t *count)
{}

static int smu_v14_0_common_get_dpm_level_count(struct smu_context *smu,
					   enum smu_clk_type clk_type,
					   uint32_t *count)
{}

static int smu_v14_0_0_print_clk_levels(struct smu_context *smu,
					enum smu_clk_type clk_type, char *buf)
{}

static int smu_v14_0_0_set_soft_freq_limited_range(struct smu_context *smu,
						   enum smu_clk_type clk_type,
						   uint32_t min,
						   uint32_t max)
{}

static int smu_v14_0_0_force_clk_levels(struct smu_context *smu,
					enum smu_clk_type clk_type,
					uint32_t mask)
{}

static int smu_v14_0_common_get_dpm_profile_freq(struct smu_context *smu,
					enum amd_dpm_forced_level level,
					enum smu_clk_type clk_type,
					uint32_t *min_clk,
					uint32_t *max_clk)
{}

static int smu_v14_0_common_set_performance_level(struct smu_context *smu,
					     enum amd_dpm_forced_level level)
{}

static int smu_v14_0_1_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
{}

static int smu_v14_0_0_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
{}

static int smu_v14_0_common_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
{}

static int smu_v14_0_0_set_vpe_enable(struct smu_context *smu,
				      bool enable)
{}

static int smu_v14_0_0_set_umsch_mm_enable(struct smu_context *smu,
			      bool enable)
{}

static int smu_14_0_1_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
{}

static int smu_14_0_0_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
{}

static int smu_v14_0_common_get_dpm_table(struct smu_context *smu, struct dpm_clocks *clock_table)
{}

static int smu_v14_0_1_init_mall_power_gating(struct smu_context *smu, enum smu_mall_pg_config pg_config)
{}

static int smu_v14_0_common_set_mall_enable(struct smu_context *smu)
{}

static const struct pptable_funcs smu_v14_0_0_ppt_funcs =;

static void smu_v14_0_0_set_smu_mailbox_registers(struct smu_context *smu)
{}

void smu_v14_0_0_set_ppt_funcs(struct smu_context *smu)
{}