linux/drivers/gpu/drm/amd/pm/powerplay/inc/hardwaremanager.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _HARDWARE_MANAGER_H_
#define _HARDWARE_MANAGER_H_



struct pp_hwmgr;
struct pp_hw_power_state;
struct pp_power_state;
enum amd_dpm_forced_level;
struct PP_TemperatureRange;


struct phm_fan_speed_info { … };

/* Automatic Power State Throttling */
enum PHM_AutoThrottleSource { … };

PHM_AutoThrottleSource;

enum phm_platform_caps { … };

#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD …

/* Number of uint32_t entries used by CAPS table */
#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES …

struct pp_hw_descriptor { … };

enum PHM_PerformanceLevelDesignation { … };

PHM_PerformanceLevelDesignation;

struct PHM_PerformanceLevel { … };

PHM_PerformanceLevel;

/* Function for setting a platform cap */
static inline void phm_cap_set(uint32_t *caps,
			enum phm_platform_caps c)
{ … }

static inline void phm_cap_unset(uint32_t *caps,
			enum phm_platform_caps c)
{ … }

static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
{ … }

#define PP_CAP(c) …

#define PP_PCIEGenInvalid …
enum PP_PCIEGen { … };

PP_PCIEGen;

#define PP_Min_PCIEGen …
#define PP_Max_PCIEGen …
#define PP_Min_PCIELane …
#define PP_Max_PCIELane …

enum phm_clock_Type { … };

#define MAX_NUM_CLOCKS …

struct PP_Clocks { … };

struct pp_clock_info { … };

struct phm_platform_descriptor { … };

struct phm_clocks { … };

#define DPMTABLE_OD_UPDATE_SCLK …
#define DPMTABLE_OD_UPDATE_MCLK …
#define DPMTABLE_UPDATE_SCLK …
#define DPMTABLE_UPDATE_MCLK …
#define DPMTABLE_OD_UPDATE_VDDC …
#define DPMTABLE_UPDATE_SOCCLK …

struct phm_odn_performance_level { … };

struct phm_odn_clock_levels { … };

extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
		    const struct pp_hw_power_state *pcurrent_state,
		 const struct pp_hw_power_state *pnew_power_state);

extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				   struct pp_power_state *adjusted_ps,
			     const struct pp_power_state *current_ps);

extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);

extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);

extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
				 const struct pp_hw_power_state *pstate1,
				 const struct pp_hw_power_state *pstate2,
				 bool *equal);

extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
		const struct amd_pp_display_configuration *display_config);

extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
		struct amd_pp_simple_clock_info *info);

extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);

extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);

extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
				PHM_PerformanceLevelDesignation designation, uint32_t index,
				PHM_PerformanceLevel *level);

extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
			struct pp_clock_info *pclock_info,
			PHM_PerformanceLevelDesignation designation);

extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);

extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);

extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
		enum amd_pp_clock_type type,
		struct pp_clock_levels_with_latency *clocks);
extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
		enum amd_pp_clock_type type,
		struct pp_clock_levels_with_voltage *clocks);
extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
						void *clock_ranges);
extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
		struct pp_display_clock_request *clock);

extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);

extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count);

#endif /* _HARDWARE_MANAGER_H_ */