/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef PP_ATOMVOLTAGECTRL_H #define PP_ATOMVOLTAGECTRL_H #include "hwmgr.h" /* As returned from PowerConnectorDetectionTable. */ #define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE … #define PP_ATOM_POWER_BUDGET_SHOW_WARNING … #define PP_ATOM_POWER_BUDGET_SHOW_WAIVER … #define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR … /* New functions for Evergreen and beyond. */ #define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES … struct pp_atomctrl_clock_dividers { … }; pp_atomctrl_clock_dividers; pp_atomctrl_tcipll_fb_divider; pp_atomctrl_tcipll_fb_divider; struct pp_atomctrl_clock_dividers_rv730 { … }; pp_atomctrl_clock_dividers_rv730; struct pp_atomctrl_clock_dividers_kong { … }; pp_atomctrl_clock_dividers_kong; struct pp_atomctrl_clock_dividers_ci { … }; pp_atomctrl_clock_dividers_ci; struct pp_atomctrl_clock_dividers_vi { … }; pp_atomctrl_clock_dividers_vi; struct pp_atomctrl_clock_dividers_ai { … }; pp_atomctrl_clock_dividers_ai; pp_atomctrl_s_mpll_fb_divider; pp_atomctrl_s_mpll_fb_divider; enum pp_atomctrl_spread_spectrum_mode { … }; pp_atomctrl_spread_spectrum_mode; struct pp_atomctrl_memory_clock_param { … }; pp_atomctrl_memory_clock_param; struct pp_atomctrl_memory_clock_param_ai { … }; pp_atomctrl_memory_clock_param_ai; struct pp_atomctrl_internal_ss_info { … }; pp_atomctrl_internal_ss_info; #ifndef NUMBER_OF_M3ARB_PARAMS #define NUMBER_OF_M3ARB_PARAMS … #endif #ifndef NUMBER_OF_M3ARB_PARAM_SETS #define NUMBER_OF_M3ARB_PARAM_SETS … #endif struct pp_atomctrl_kong_system_info { … }; pp_atomctrl_kong_system_info; struct pp_atomctrl_memory_info { … }; pp_atomctrl_memory_info; #define MAX_AC_TIMING_ENTRIES … struct pp_atomctrl_memory_clock_range_table { … }; pp_atomctrl_memory_clock_range_table; struct pp_atomctrl_voltage_table_entry { … }; pp_atomctrl_voltage_table_entry; struct pp_atomctrl_voltage_table { … }; pp_atomctrl_voltage_table; #define VBIOS_MC_REGISTER_ARRAY_SIZE … #define VBIOS_MAX_AC_TIMING_ENTRIES … struct pp_atomctrl_mc_reg_entry { … }; pp_atomctrl_mc_reg_entry; struct pp_atomctrl_mc_register_address { … }; pp_atomctrl_mc_register_address; #define MAX_SCLK_RANGE … struct pp_atom_ctrl_sclk_range_table_entry{ … }; struct pp_atom_ctrl_sclk_range_table{ … }; struct pp_atomctrl_mc_reg_table { … }; pp_atomctrl_mc_reg_table; struct pp_atomctrl_gpio_pin_assignment { … }; pp_atomctrl_gpio_pin_assignment; struct pp_atom_ctrl__avfs_parameters { … }; struct _AtomCtrl_HiLoLeakageOffsetTable { … }; AtomCtrl_HiLoLeakageOffsetTable; struct _AtomCtrl_EDCLeakgeTable { … }; AtomCtrl_EDCLeakgeTable; extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage); extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); bool atomctrl_is_asic_internal_ss_supported(struct pp_hwmgr *hwmgr); extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table); extern int atomctrl_initialize_mc_reg_table_v2_2(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table); extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr); extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode); extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table); extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param); extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_kong *dividers); extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, uint16_t end_index, uint32_t *efuse); extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers); extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, uint8_t level); extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param); extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t *svd_gpio_id, uint8_t *svc_gpio_id, uint16_t *load_line); extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, uint16_t *vddc, uint16_t *vddci, uint16_t virtual_voltage_id, uint16_t efuse_voltage_id); extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id); extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, uint32_t *min_vddc); extern int atomctrl_get_edc_hilo_leakage_offset_table(struct pp_hwmgr *hwmgr, AtomCtrl_HiLoLeakageOffsetTable *table); extern int atomctrl_get_edc_leakage_table(struct pp_hwmgr *hwmgr, AtomCtrl_EDCLeakgeTable *table, uint16_t offset); extern int atomctrl_get_vddc_shared_railinfo(struct pp_hwmgr *hwmgr, uint8_t *shared_rail); #endif
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