#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/reboot.h>
#define SWSMU_CODE_LAYER_L3
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "atomfirmware.h"
#include "amdgpu_atomfirmware.h"
#include "amdgpu_atombios.h"
#include "smu_v14_0.h"
#include "soc15_common.h"
#include "atom.h"
#include "amdgpu_ras.h"
#include "smu_cmn.h"
#include "asic_reg/thm/thm_14_0_2_offset.h"
#include "asic_reg/thm/thm_14_0_2_sh_mask.h"
#include "asic_reg/mp/mp_14_0_2_offset.h"
#include "asic_reg/mp/mp_14_0_2_sh_mask.h"
#define regMP1_SMN_IH_SW_INT_mp1_14_0_0 …
#define regMP1_SMN_IH_SW_INT_mp1_14_0_0_BASE_IDX …
#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0 …
#define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX …
const int decoded_link_speed[5] = …;
const int decoded_link_width[7] = …;
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug
MODULE_FIRMWARE(…) …;
MODULE_FIRMWARE(…) …;
#define ENABLE_IMU_ARG_GFXOFF_ENABLE …
int smu_v14_0_init_microcode(struct smu_context *smu)
{ … }
void smu_v14_0_fini_microcode(struct smu_context *smu)
{ … }
int smu_v14_0_load_microcode(struct smu_context *smu)
{ … }
int smu_v14_0_init_pptable_microcode(struct smu_context *smu)
{ … }
int smu_v14_0_check_fw_status(struct smu_context *smu)
{ … }
int smu_v14_0_check_fw_version(struct smu_context *smu)
{ … }
static int smu_v14_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
{ … }
static int smu_v14_0_set_pptable_v2_1(struct smu_context *smu, void **table,
uint32_t *size, uint32_t pptable_id)
{ … }
static int smu_v14_0_get_pptable_from_vbios(struct smu_context *smu, void **table, uint32_t *size)
{ … }
int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu,
void **table,
uint32_t *size,
uint32_t pptable_id)
{ … }
int smu_v14_0_setup_pptable(struct smu_context *smu)
{ … }
int smu_v14_0_init_smc_tables(struct smu_context *smu)
{ … }
int smu_v14_0_fini_smc_tables(struct smu_context *smu)
{ … }
int smu_v14_0_init_power(struct smu_context *smu)
{ … }
int smu_v14_0_fini_power(struct smu_context *smu)
{ … }
int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu)
{ … }
int smu_v14_0_notify_memory_pool_location(struct smu_context *smu)
{ … }
int smu_v14_0_set_driver_table_location(struct smu_context *smu)
{ … }
int smu_v14_0_set_tool_table_location(struct smu_context *smu)
{ … }
int smu_v14_0_set_allowed_mask(struct smu_context *smu)
{ … }
int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable)
{ … }
int smu_v14_0_system_features_control(struct smu_context *smu,
bool en)
{ … }
int smu_v14_0_notify_display_change(struct smu_context *smu)
{ … }
int smu_v14_0_get_current_power_limit(struct smu_context *smu,
uint32_t *power_limit)
{ … }
int smu_v14_0_set_power_limit(struct smu_context *smu,
enum smu_ppt_limit_type limit_type,
uint32_t limit)
{ … }
static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned tyep,
enum amdgpu_interrupt_state state)
{ … }
#define THM_11_0__SRCID__THM_DIG_THERM_L2H …
#define THM_11_0__SRCID__THM_DIG_THERM_H2L …
static int smu_v14_0_irq_process(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{ … }
static const struct amdgpu_irq_src_funcs smu_v14_0_irq_funcs = …;
int smu_v14_0_register_irq_handler(struct smu_context *smu)
{ … }
static int smu_v14_0_wait_for_reset_complete(struct smu_context *smu,
uint64_t event_arg)
{ … }
int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event,
uint64_t event_arg)
{ … }
int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max)
{ … }
int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
uint32_t max)
{ … }
int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
uint32_t max)
{ … }
int smu_v14_0_set_performance_level(struct smu_context *smu,
enum amd_dpm_forced_level level)
{ … }
int smu_v14_0_set_power_source(struct smu_context *smu,
enum smu_power_src_type power_src)
{ … }
static int smu_v14_0_get_dpm_freq_by_index(struct smu_context *smu,
enum smu_clk_type clk_type,
uint16_t level,
uint32_t *value)
{ … }
static int smu_v14_0_get_dpm_level_count(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value)
{ … }
static int smu_v14_0_get_fine_grained_status(struct smu_context *smu,
enum smu_clk_type clk_type,
bool *is_fine_grained_dpm)
{ … }
int smu_v14_0_set_single_dpm_table(struct smu_context *smu,
enum smu_clk_type clk_type,
struct smu_14_0_dpm_table *single_dpm_table)
{ … }
int smu_v14_0_set_vcn_enable(struct smu_context *smu,
bool enable)
{ … }
int smu_v14_0_set_jpeg_enable(struct smu_context *smu,
bool enable)
{ … }
int smu_v14_0_run_btc(struct smu_context *smu)
{ … }
int smu_v14_0_gpo_control(struct smu_context *smu,
bool enablement)
{ … }
int smu_v14_0_deep_sleep_control(struct smu_context *smu,
bool enablement)
{ … }
int smu_v14_0_gfx_ulv_control(struct smu_context *smu,
bool enablement)
{ … }
int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu,
enum smu_baco_seq baco_seq)
{ … }
int smu_v14_0_get_bamaco_support(struct smu_context *smu)
{ … }
enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu)
{ … }
int smu_v14_0_baco_set_state(struct smu_context *smu,
enum smu_baco_state state)
{ … }
int smu_v14_0_baco_enter(struct smu_context *smu)
{ … }
int smu_v14_0_baco_exit(struct smu_context *smu)
{ … }
int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu)
{ … }
int smu_v14_0_set_default_dpm_tables(struct smu_context *smu)
{ … }
int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long input[], uint32_t size)
{ … }
static int smu_v14_0_allow_ih_interrupt(struct smu_context *smu)
{ … }
static int smu_v14_0_process_pending_interrupt(struct smu_context *smu)
{ … }
int smu_v14_0_enable_thermal_alert(struct smu_context *smu)
{ … }
int smu_v14_0_disable_thermal_alert(struct smu_context *smu)
{ … }