/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2023 Inochi Amaoto <[email protected]> */ #ifndef _CLK_SOPHGO_CV1800_H_ #define _CLK_SOPHGO_CV1800_H_ #include <dt-bindings/clock/sophgo,cv1800.h> #define CV1800_CLK_MAX … #define CV1810_CLK_MAX … #define REG_PLL_G2_CTRL … #define REG_PLL_G2_STATUS … #define REG_MIPIMPLL_CSR … #define REG_A0PLL_CSR … #define REG_DISPPLL_CSR … #define REG_CAM0PLL_CSR … #define REG_CAM1PLL_CSR … #define REG_PLL_G2_SSC_SYN_CTRL … #define REG_A0PLL_SSC_SYN_CTRL … #define REG_A0PLL_SSC_SYN_SET … #define REG_A0PLL_SSC_SYN_SPAN … #define REG_A0PLL_SSC_SYN_STEP … #define REG_DISPPLL_SSC_SYN_CTRL … #define REG_DISPPLL_SSC_SYN_SET … #define REG_DISPPLL_SSC_SYN_SPAN … #define REG_DISPPLL_SSC_SYN_STEP … #define REG_CAM0PLL_SSC_SYN_CTRL … #define REG_CAM0PLL_SSC_SYN_SET … #define REG_CAM0PLL_SSC_SYN_SPAN … #define REG_CAM0PLL_SSC_SYN_STEP … #define REG_CAM1PLL_SSC_SYN_CTRL … #define REG_CAM1PLL_SSC_SYN_SET … #define REG_CAM1PLL_SSC_SYN_SPAN … #define REG_CAM1PLL_SSC_SYN_STEP … #define REG_APLL_FRAC_DIV_CTRL … #define REG_APLL_FRAC_DIV_M … #define REG_APLL_FRAC_DIV_N … #define REG_MIPIMPLL_CLK_CSR … #define REG_A0PLL_CLK_CSR … #define REG_DISPPLL_CLK_CSR … #define REG_CAM0PLL_CLK_CSR … #define REG_CAM1PLL_CLK_CSR … #define REG_CLK_CAM0_SRC_DIV … #define REG_CLK_CAM1_SRC_DIV … /* top_pll_g6 */ #define REG_PLL_G6_CTRL … #define REG_PLL_G6_STATUS … #define REG_MPLL_CSR … #define REG_TPLL_CSR … #define REG_FPLL_CSR … #define REG_PLL_G6_SSC_SYN_CTRL … #define REG_DPLL_SSC_SYN_CTRL … #define REG_DPLL_SSC_SYN_SET … #define REG_DPLL_SSC_SYN_SPAN … #define REG_DPLL_SSC_SYN_STEP … #define REG_MPLL_SSC_SYN_CTRL … #define REG_MPLL_SSC_SYN_SET … #define REG_MPLL_SSC_SYN_SPAN … #define REG_MPLL_SSC_SYN_STEP … #define REG_TPLL_SSC_SYN_CTRL … #define REG_TPLL_SSC_SYN_SET … #define REG_TPLL_SSC_SYN_SPAN … #define REG_TPLL_SSC_SYN_STEP … /* clkgen */ #define REG_CLK_EN_0 … #define REG_CLK_EN_1 … #define REG_CLK_EN_2 … #define REG_CLK_EN_3 … #define REG_CLK_EN_4 … #define REG_CLK_SEL_0 … #define REG_CLK_BYP_0 … #define REG_CLK_BYP_1 … #define REG_DIV_CLK_A53_0 … #define REG_DIV_CLK_A53_1 … #define REG_DIV_CLK_CPU_AXI0 … #define REG_DIV_CLK_CPU_GIC … #define REG_DIV_CLK_TPU … #define REG_DIV_CLK_EMMC … #define REG_DIV_CLK_EMMC_100K … #define REG_DIV_CLK_SD0 … #define REG_DIV_CLK_SD0_100K … #define REG_DIV_CLK_SD1 … #define REG_DIV_CLK_SD1_100K … #define REG_DIV_CLK_SPI_NAND … #define REG_DIV_CLK_ETH0_500M … #define REG_DIV_CLK_ETH1_500M … #define REG_DIV_CLK_GPIO_DB … #define REG_DIV_CLK_SDMA_AUD0 … #define REG_DIV_CLK_SDMA_AUD1 … #define REG_DIV_CLK_SDMA_AUD2 … #define REG_DIV_CLK_SDMA_AUD3 … #define REG_DIV_CLK_CAM0_200 … #define REG_DIV_CLK_AXI4 … #define REG_DIV_CLK_AXI6 … #define REG_DIV_CLK_DSI_ESC … #define REG_DIV_CLK_AXI_VIP … #define REG_DIV_CLK_SRC_VIP_SYS_0 … #define REG_DIV_CLK_SRC_VIP_SYS_1 … #define REG_DIV_CLK_DISP_SRC_VIP … #define REG_DIV_CLK_AXI_VIDEO_CODEC … #define REG_DIV_CLK_VC_SRC0 … #define REG_DIV_CLK_1M … #define REG_DIV_CLK_SPI … #define REG_DIV_CLK_I2C … #define REG_DIV_CLK_SRC_VIP_SYS_2 … #define REG_DIV_CLK_AUDSRC … #define REG_DIV_CLK_PWM_SRC_0 … #define REG_DIV_CLK_AP_DEBUG … #define REG_DIV_CLK_RTCSYS_SRC_0 … #define REG_DIV_CLK_C906_0_0 … #define REG_DIV_CLK_C906_0_1 … #define REG_DIV_CLK_C906_1_0 … #define REG_DIV_CLK_C906_1_1 … #define REG_DIV_CLK_SRC_VIP_SYS_3 … #define REG_DIV_CLK_SRC_VIP_SYS_4 … #endif /* _CLK_SOPHGO_CV1800_H_ */
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