linux/drivers/clk/sophgo/clk-cv18xx-pll.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2023 Inochi Amaoto <[email protected]>
 */

#ifndef _CLK_SOPHGO_CV1800_PLL_H_
#define _CLK_SOPHGO_CV1800_PLL_H_

#include "clk-cv18xx-common.h"

struct cv1800_clk_pll_limit { … };

#define _CV1800_PLL_LIMIT(_min, _max) …				\

#define for_each_pll_limit_range(_var, _restrict) …

struct cv1800_clk_pll_synthesizer { … };

#define _PLL_PRE_DIV_SEL_FIELD …
#define _PLL_POST_DIV_SEL_FIELD …
#define _PLL_SEL_MODE_FIELD …
#define _PLL_DIV_SEL_FIELD …
#define _PLL_ICTRL_FIELD …

#define _PLL_ALL_FIELD_MASK …

#define PLL_COPY_REG(_dest, _src) …

#define PLL_GET_PRE_DIV_SEL(_reg) …
#define PLL_GET_POST_DIV_SEL(_reg) …
#define PLL_GET_SEL_MODE(_reg) …
#define PLL_GET_DIV_SEL(_reg) …
#define PLL_GET_ICTRL(_reg) …

#define PLL_SET_PRE_DIV_SEL(_reg, _val) …
#define PLL_SET_POST_DIV_SEL(_reg, _val) …
#define PLL_SET_SEL_MODE(_reg, _val) …
#define PLL_SET_DIV_SEL(_reg, _val) …
#define PLL_SET_ICTRL(_reg, _val) …

struct cv1800_clk_pll { … };

#define CV1800_INTEGRAL_PLL(_name, _parent, _pll_reg,			\
			     _pll_pwd_reg, _pll_pwd_shift,		\
			     _pll_status_reg, _pll_status_shift,	\
			     _pll_limit, _flags) …

#define CV1800_FACTIONAL_PLL(_name, _parent, _pll_reg,			\
			     _pll_pwd_reg, _pll_pwd_shift,		\
			     _pll_status_reg, _pll_status_shift,	\
			     _pll_limit, _pll_syn, _flags) …

extern const struct clk_ops cv1800_clk_ipll_ops;
extern const struct clk_ops cv1800_clk_fpll_ops;

#endif // _CLK_SOPHGO_CV1800_PLL_H_