linux/drivers/clk/sophgo/clk-cv18xx-pll.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2023 Inochi Amaoto <[email protected]>
 */

#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/limits.h>
#include <linux/spinlock.h>

#include "clk-cv18xx-pll.h"

static inline struct cv1800_clk_pll *hw_to_cv1800_clk_pll(struct clk_hw *hw)
{ … }

static unsigned long ipll_calc_rate(unsigned long parent_rate,
				    unsigned long pre_div_sel,
				    unsigned long div_sel,
				    unsigned long post_div_sel)
{ … }

static unsigned long ipll_recalc_rate(struct clk_hw *hw,
				      unsigned long parent_rate)
{ … }

static int ipll_find_rate(const struct cv1800_clk_pll_limit *limit,
			  unsigned long prate, unsigned long *rate,
			  u32 *value)
{ … }

static int ipll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{ … }

static void pll_get_mode_ctrl(unsigned long div_sel,
			      bool (*mode_ctrl_check)(unsigned long,
						      unsigned long,
						      unsigned long),
			      const struct cv1800_clk_pll_limit *limit,
			      u32 *value)
{ … }

static bool ipll_check_mode_ctrl_restrict(unsigned long div_sel,
					  unsigned long ictrl,
					  unsigned long mode)
{ … }

static int ipll_set_rate(struct clk_hw *hw, unsigned long rate,
			 unsigned long parent_rate)
{ … }

static int pll_enable(struct clk_hw *hw)
{ … }

static void pll_disable(struct clk_hw *hw)
{ … }

static int pll_is_enable(struct clk_hw *hw)
{ … }

const struct clk_ops cv1800_clk_ipll_ops = …;

#define PLL_SYN_FACTOR_DOT_POS …
#define PLL_SYN_FACTOR_MINIMUM …

static bool fpll_is_factional_mode(struct cv1800_clk_pll *pll)
{ … }

static unsigned long fpll_calc_rate(unsigned long parent_rate,
				    unsigned long pre_div_sel,
				    unsigned long div_sel,
				    unsigned long post_div_sel,
				    unsigned long ssc_syn_set,
				    bool is_full_parent)
{ … }

static unsigned long fpll_recalc_rate(struct clk_hw *hw,
					  unsigned long parent_rate)
{ … }

static unsigned long fpll_find_synthesizer(unsigned long parent,
					   unsigned long rate,
					   unsigned long pre_div,
					   unsigned long div,
					   unsigned long post_div,
					   bool is_full_parent,
					   u32 *ssc_syn_set)
{ … }

static int fpll_find_rate(struct cv1800_clk_pll *pll,
			  const struct cv1800_clk_pll_limit *limit,
			  unsigned long prate,
			  unsigned long *rate,
			  u32 *value, u32 *ssc_syn_set)
{ … }

static int fpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{ … }

static bool fpll_check_mode_ctrl_restrict(unsigned long div_sel,
					  unsigned long ictrl,
					  unsigned long mode)
{ … }

static int fpll_set_rate(struct clk_hw *hw, unsigned long rate,
			 unsigned long parent_rate)
{ … }

static u8 fpll_get_parent(struct clk_hw *hw)
{ … }

static int fpll_set_parent(struct clk_hw *hw, u8 index)
{ … }

const struct clk_ops cv1800_clk_fpll_ops = …;