/* * Copyright 2019 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #include <linux/module.h> #include <linux/fdtable.h> #include <linux/uaccess.h> #include <linux/firmware.h> #include "amdgpu.h" #include "amdgpu_amdkfd.h" #include "amdgpu_amdkfd_arcturus.h" #include "amdgpu_reset.h" #include "sdma0/sdma0_4_2_2_offset.h" #include "sdma0/sdma0_4_2_2_sh_mask.h" #include "sdma1/sdma1_4_2_2_offset.h" #include "sdma1/sdma1_4_2_2_sh_mask.h" #include "sdma2/sdma2_4_2_2_offset.h" #include "sdma2/sdma2_4_2_2_sh_mask.h" #include "sdma3/sdma3_4_2_2_offset.h" #include "sdma3/sdma3_4_2_2_sh_mask.h" #include "sdma4/sdma4_4_2_2_offset.h" #include "sdma4/sdma4_4_2_2_sh_mask.h" #include "sdma5/sdma5_4_2_2_offset.h" #include "sdma5/sdma5_4_2_2_sh_mask.h" #include "sdma6/sdma6_4_2_2_offset.h" #include "sdma6/sdma6_4_2_2_sh_mask.h" #include "sdma7/sdma7_4_2_2_offset.h" #include "sdma7/sdma7_4_2_2_sh_mask.h" #include "v9_structs.h" #include "soc15.h" #include "soc15d.h" #include "amdgpu_amdkfd_gfx_v9.h" #include "gfxhub_v1_0.h" #include "mmhub_v9_4.h" #include "gc/gc_9_0_offset.h" #include "gc/gc_9_0_sh_mask.h" #define HQD_N_REGS … #define DUMP_REG(addr) … static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) { … } static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, unsigned int engine_id, unsigned int queue_id) { … } int kgd_arcturus_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, uint32_t __user *wptr, struct mm_struct *mm) { … } int kgd_arcturus_hqd_sdma_dump(struct amdgpu_device *adev, uint32_t engine_id, uint32_t queue_id, uint32_t (**dump)[2], uint32_t *n_regs) { … } bool kgd_arcturus_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd) { … } int kgd_arcturus_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, unsigned int utimeout) { … } /* * Helper used to suspend/resume gfx pipe for image post process work to set * barrier behaviour. */ static int suspend_resume_compute_scheduler(struct amdgpu_device *adev, bool suspend) { … } static void set_barrier_auto_waitcnt(struct amdgpu_device *adev, bool enable_waitcnt) { … } /* * restore_dbg_registers is ignored here but is a general interface requirement * for devices that support GFXOFF and where the RLC save/restore list * does not support hw registers for debugging i.e. the driver has to manually * initialize the debug mode registers after it has disabled GFX off during the * debug session. */ static uint32_t kgd_arcturus_enable_debug_trap(struct amdgpu_device *adev, bool restore_dbg_registers, uint32_t vmid) { … } /* * keep_trap_enabled is ignored here but is a general interface requirement * for devices that support multi-process debugging where the performance * overhead from trap temporary setup needs to be bypassed when the debug * session has ended. */ static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev, bool keep_trap_enabled, uint32_t vmid) { … } const struct kfd2kgd_calls arcturus_kfd2kgd = …;
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