linux/drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _HWMGR_H_
#define _HWMGR_H_

#include <linux/seq_file.h>
#include "amd_powerplay.h"
#include "hardwaremanager.h"
#include "hwmgr_ppt.h"
#include "ppatomctrl.h"
#include "power_state.h"
#include "smu_helper.h"

struct pp_hwmgr;
struct phm_fan_speed_info;
struct pp_atomctrl_voltage_table;

#define VOLTAGE_SCALE …
#define VOLTAGE_VID_OFFSET_SCALE1 …
#define VOLTAGE_VID_OFFSET_SCALE2 …

enum DISPLAY_GAP { … };
DISPLAY_GAP;

enum BACO_STATE { … };

struct vi_dpm_level { … };

struct vi_dpm_table { … };

#define PCIE_PERF_REQ_REMOVE_REGISTRY …
#define PCIE_PERF_REQ_FORCE_LOWPOWER …
#define PCIE_PERF_REQ_GEN1 …
#define PCIE_PERF_REQ_GEN2 …
#define PCIE_PERF_REQ_GEN3 …

enum PHM_BackEnd_Magic { … };

struct phm_set_power_state_input { … };

struct phm_clock_array { … };

struct phm_clock_voltage_dependency_record { … };

struct phm_vceclock_voltage_dependency_record { … };

struct phm_uvdclock_voltage_dependency_record { … };

struct phm_samuclock_voltage_dependency_record { … };

struct phm_acpclock_voltage_dependency_record { … };

struct phm_clock_voltage_dependency_table { … };

struct phm_phase_shedding_limits_record { … };

struct phm_uvd_clock_voltage_dependency_record { … };

struct phm_uvd_clock_voltage_dependency_table { … };

struct phm_acp_clock_voltage_dependency_record { … };

struct phm_acp_clock_voltage_dependency_table { … };

struct phm_vce_clock_voltage_dependency_record { … };

struct phm_phase_shedding_limits_table { … };

struct phm_vceclock_voltage_dependency_table { … };

struct phm_uvdclock_voltage_dependency_table { … };

struct phm_samuclock_voltage_dependency_table { … };

struct phm_acpclock_voltage_dependency_table { … };

struct phm_vce_clock_voltage_dependency_table { … };


enum SMU_ASIC_RESET_MODE { … };

struct pp_smumgr_func { … };

struct pp_hwmgr_func { … };

struct pp_table_func { … };

phm_cac_leakage_record;

struct phm_cac_leakage_table { … };

struct phm_samu_clock_voltage_dependency_record { … };


struct phm_samu_clock_voltage_dependency_table { … };

struct phm_cac_tdp_table { … };

struct phm_tdp_table { … };

struct phm_ppm_table { … };

struct phm_vq_budgeting_record { … };

struct phm_vq_budgeting_table { … };

struct phm_clock_and_voltage_limits { … };

/* Structure to hold PPTable information */

struct phm_ppt_v1_information { … };

struct phm_ppt_v2_information { … };

struct phm_ppt_v3_information { … };

struct phm_dynamic_state_info { … };

struct pp_fan_info { … };

struct pp_advance_fan_control_parameters { … };

struct pp_thermal_controller_info { … };

struct phm_microcode_version_info { … };

enum PP_TABLE_VERSION { … };

/**
 * The main hardware manager structure.
 */
#define Workload_Policy_Max …

struct pp_hwmgr { … };

int hwmgr_early_init(struct pp_hwmgr *hwmgr);
int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
int hwmgr_suspend(struct pp_hwmgr *hwmgr);
int hwmgr_resume(struct pp_hwmgr *hwmgr);

int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
				enum amd_pp_task task_id,
				enum amd_pm_state_type *user_state);


#define PHM_ENTIRE_REGISTER_MASK …

int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);

#endif /* _HWMGR_H_ */