/* * SMU_8_0 Register documentation * * Copyright (C) 2014 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef SMU_8_0_D_H #define SMU_8_0_D_H #define ixTHM_TCON_CSR_CONFIG … #define ixTHM_TCON_CSR_DATA … #define ixTHM_TCON_HTC … #define ixTHM_TCON_CUR_TMP … #define ixTHM_TCON_THERM_TRIP … #define ixTHM_GPIO_PROCHOT_CTRL … #define ixTHM_GPIO_THERMTRIP_CTRL … #define ixTHM_THERMAL_INT_ENA … #define ixTHM_THERMAL_INT_CTRL … #define ixTHM_THERMAL_INT_STATUS … #define ixTMON0_RDIL0_DATA … #define ixTMON0_RDIL1_DATA … #define ixTMON0_RDIL2_DATA … #define ixTMON0_RDIL3_DATA … #define ixTMON0_RDIL4_DATA … #define ixTMON0_RDIL5_DATA … #define ixTMON0_RDIL6_DATA … #define ixTMON0_RDIL7_DATA … #define ixTMON0_RDIL8_DATA … #define ixTMON0_RDIL9_DATA … #define ixTMON0_RDIL10_DATA … #define ixTMON0_RDIL11_DATA … #define ixTMON0_RDIL12_DATA … #define ixTMON0_RDIL13_DATA … #define ixTMON0_RDIL14_DATA … #define ixTMON0_RDIL15_DATA … #define ixTMON0_RDIR0_DATA … #define ixTMON0_RDIR1_DATA … #define ixTMON0_RDIR2_DATA … #define ixTMON0_RDIR3_DATA … #define ixTMON0_RDIR4_DATA … #define ixTMON0_RDIR5_DATA … #define ixTMON0_RDIR6_DATA … #define ixTMON0_RDIR7_DATA … #define ixTMON0_RDIR8_DATA … #define ixTMON0_RDIR9_DATA … #define ixTMON0_RDIR10_DATA … #define ixTMON0_RDIR11_DATA … #define ixTMON0_RDIR12_DATA … #define ixTMON0_RDIR13_DATA … #define ixTMON0_RDIR14_DATA … #define ixTMON0_RDIR15_DATA … #define ixTMON0_INT_DATA … #define ixTMON0_RDIL_PRESENT0 … #define ixTMON0_RDIL_PRESENT1 … #define ixTMON0_RDIR_PRESENT0 … #define ixTMON0_RDIR_PRESENT1 … #define ixTMON0_CONFIG … #define ixTMON0_TEMP_CALC_COEFF0 … #define ixTMON0_TEMP_CALC_COEFF1 … #define ixTMON0_TEMP_CALC_COEFF2 … #define ixTMON0_TEMP_CALC_COEFF3 … #define ixTMON0_TEMP_CALC_COEFF4 … #define ixTMON0_DEBUG0 … #define ixTMON0_DEBUG1 … #define ixTMON1_RDIL0_DATA … #define ixTMON1_RDIL1_DATA … #define ixTMON1_RDIL2_DATA … #define ixTMON1_RDIL3_DATA … #define ixTMON1_RDIL4_DATA … #define ixTMON1_RDIL5_DATA … #define ixTMON1_RDIL6_DATA … #define ixTMON1_RDIL7_DATA … #define ixTMON1_RDIL8_DATA … #define ixTMON1_RDIL9_DATA … #define ixTMON1_RDIL10_DATA … #define ixTMON1_RDIL11_DATA … #define ixTMON1_RDIL12_DATA … #define ixTMON1_RDIL13_DATA … #define ixTMON1_RDIL14_DATA … #define ixTMON1_RDIL15_DATA … #define ixTMON1_RDIR0_DATA … #define ixTMON1_RDIR1_DATA … #define ixTMON1_RDIR2_DATA … #define ixTMON1_RDIR3_DATA … #define ixTMON1_RDIR4_DATA … #define ixTMON1_RDIR5_DATA … #define ixTMON1_RDIR6_DATA … #define ixTMON1_RDIR7_DATA … #define ixTMON1_RDIR8_DATA … #define ixTMON1_RDIR9_DATA … #define ixTMON1_RDIR10_DATA … #define ixTMON1_RDIR11_DATA … #define ixTMON1_RDIR12_DATA … #define ixTMON1_RDIR13_DATA … #define ixTMON1_RDIR14_DATA … #define ixTMON1_RDIR15_DATA … #define ixTMON1_INT_DATA … #define ixTMON1_RDIL_PRESENT0 … #define ixTMON1_RDIL_PRESENT1 … #define ixTMON1_RDIR_PRESENT0 … #define ixTMON1_RDIR_PRESENT1 … #define ixTMON1_CONFIG … #define ixTMON1_TEMP_CALC_COEFF0 … #define ixTMON1_TEMP_CALC_COEFF1 … #define ixTMON1_TEMP_CALC_COEFF2 … #define ixTMON1_TEMP_CALC_COEFF3 … #define ixTMON1_TEMP_CALC_COEFF4 … #define ixTMON1_DEBUG0 … #define ixTMON1_DEBUG1 … #define ixTHM_TMON0_REMOTE_START … #define ixTHM_TMON0_REMOTE_END … #define ixTHM_TMON1_REMOTE_START … #define ixTHM_TMON1_REMOTE_END … #define ixTHM_TCON_LOCAL0 … #define ixTHM_TCON_LOCAL1 … #define ixTHM_TCON_LOCAL2 … #define ixTHM_TCON_LOCAL3 … #define ixTHM_TCON_LOCAL4 … #define ixTHM_TCON_LOCAL5 … #define ixTHM_TCON_LOCAL6 … #define ixTHM_TCON_LOCAL7 … #define ixTHM_TCON_LOCAL8 … #define ixTHM_TCON_LOCAL9 … #define ixTHM_TCON_LOCAL10 … #define ixTHM_TCON_LOCAL11 … #define ixTHM_TCON_LOCAL12 … #define ixTHM_TCON_LOCAL13 … #define ixTHM_TCON_LOCAL14 … #define ixTHM_FUSE0 … #define ixTHM_FUSE1 … #define ixTHM_FUSE2 … #define ixTHM_FUSE3 … #define ixTHM_FUSE4 … #define ixTHM_FUSE5 … #define ixTHM_FUSE6 … #define ixTHM_FUSE7 … #define ixTHM_FUSE8 … #define ixTHM_FUSE9 … #define ixTHM_FUSE10 … #define ixTHM_FUSE11 … #define ixTHM_FUSE12 … #define mmMP0PUB_IND_INDEX … #define mmMP_SMUIF0_MP0PUB_IND_INDEX … #define mmMP_SMUIF1_MP0PUB_IND_INDEX … #define mmMP_SMUIF2_MP0PUB_IND_INDEX … #define mmMP_SMUIF3_MP0PUB_IND_INDEX … #define mmMP_SMUIF4_MP0PUB_IND_INDEX … #define mmMP_SMUIF5_MP0PUB_IND_INDEX … #define mmMP_SMUIF6_MP0PUB_IND_INDEX … #define mmMP_SMUIF7_MP0PUB_IND_INDEX … #define mmMP_SMUIF8_MP0PUB_IND_INDEX … #define mmMP_SMUIF9_MP0PUB_IND_INDEX … #define mmMP_SMUIF10_MP0PUB_IND_INDEX … #define mmMP_SMUIF11_MP0PUB_IND_INDEX … #define mmMP_SMUIF12_MP0PUB_IND_INDEX … #define mmMP_SMUIF13_MP0PUB_IND_INDEX … #define mmMP_SMUIF14_MP0PUB_IND_INDEX … #define mmMP_SMUIF15_MP0PUB_IND_INDEX … #define mmMP0PUB_IND_DATA … #define mmMP_SMUIF0_MP0PUB_IND_DATA … #define mmMP_SMUIF1_MP0PUB_IND_DATA … #define mmMP_SMUIF2_MP0PUB_IND_DATA … #define mmMP_SMUIF3_MP0PUB_IND_DATA … #define mmMP_SMUIF4_MP0PUB_IND_DATA … #define mmMP_SMUIF5_MP0PUB_IND_DATA … #define mmMP_SMUIF6_MP0PUB_IND_DATA … #define mmMP_SMUIF7_MP0PUB_IND_DATA … #define mmMP_SMUIF8_MP0PUB_IND_DATA … #define mmMP_SMUIF9_MP0PUB_IND_DATA … #define mmMP_SMUIF10_MP0PUB_IND_DATA … #define mmMP_SMUIF11_MP0PUB_IND_DATA … #define mmMP_SMUIF12_MP0PUB_IND_DATA … #define mmMP_SMUIF13_MP0PUB_IND_DATA … #define mmMP_SMUIF14_MP0PUB_IND_DATA … #define mmMP_SMUIF15_MP0PUB_IND_DATA … #define mmMP0PUB_IND_INDEX_0 … #define mmMP0PUB_IND_DATA_0 … #define mmMP0PUB_IND_INDEX_1 … #define mmMP0PUB_IND_DATA_1 … #define mmMP0PUB_IND_INDEX_2 … #define mmMP0PUB_IND_DATA_2 … #define mmMP0PUB_IND_INDEX_3 … #define mmMP0PUB_IND_DATA_3 … #define mmMP0PUB_IND_INDEX_4 … #define mmMP0PUB_IND_DATA_4 … #define mmMP0PUB_IND_INDEX_5 … #define mmMP0PUB_IND_DATA_5 … #define mmMP0PUB_IND_INDEX_6 … #define mmMP0PUB_IND_DATA_6 … #define mmMP0PUB_IND_INDEX_7 … #define mmMP0PUB_IND_DATA_7 … #define mmMP0PUB_IND_INDEX_8 … #define mmMP0PUB_IND_DATA_8 … #define mmMP0PUB_IND_INDEX_9 … #define mmMP0PUB_IND_DATA_9 … #define mmMP0PUB_IND_INDEX_10 … #define mmMP0PUB_IND_DATA_10 … #define mmMP0PUB_IND_INDEX_11 … #define mmMP0PUB_IND_DATA_11 … #define mmMP0PUB_IND_INDEX_12 … #define mmMP0PUB_IND_DATA_12 … #define mmMP0PUB_IND_INDEX_13 … #define mmMP0PUB_IND_DATA_13 … #define mmMP0PUB_IND_INDEX_14 … #define mmMP0PUB_IND_DATA_14 … #define mmMP0PUB_IND_INDEX_15 … #define mmMP0PUB_IND_DATA_15 … #define mmMP0_IND_ACCESS_CNTL … #define mmMP0_MSP_MESSAGE_0 … #define mmMP0_MSP_MESSAGE_1 … #define mmMP0_MSP_MESSAGE_2 … #define mmMP0_MSP_MESSAGE_3 … #define mmMP0_MSP_MESSAGE_4 … #define mmMP0_MSP_MESSAGE_5 … #define mmMP0_MSP_MESSAGE_6 … #define mmMP0_MSP_MESSAGE_7 … #define mmSAM_IH_EXT_ERR_INTR … #define mmSAM_IH_EXT_ERR_INTR_STATUS … #define mmMP0_DISP_TIMER0_CTRL0 … #define mmMP0_DISP_TIMER0_CTRL1 … #define mmMP0_DISP_TIMER0_CMP_AUTOINC … #define mmMP0_DISP_TIMER0_INTEN … #define mmMP0_DISP_TIMER0_OCMP_0_0 … #define mmMP0_DISP_TIMER0_OCMP_0_1 … #define mmMP0_DISP_TIMER0_CNT … #define mmMP0_DISP_TIMER1_CTRL0 … #define mmMP0_DISP_TIMER1_CTRL1 … #define mmMP0_DISP_TIMER1_CMP_AUTOINC … #define mmMP0_DISP_TIMER1_INTEN … #define mmMP0_DISP_TIMER1_OCMP_0_0 … #define mmMP0_DISP_TIMER1_OCMP_0_1 … #define mmMP0_DISP_TIMER1_CNT … #define mmSMU_MP1_SRBM2P_MSG_0 … #define mmSMU_MP1_SRBM2P_MSG_1 … #define mmSMU_MP1_SRBM2P_MSG_2 … #define mmSMU_MP1_SRBM2P_MSG_3 … #define mmSMU_MP1_SRBM2P_MSG_4 … #define mmSMU_MP1_SRBM2P_MSG_5 … #define mmSMU_MP1_SRBM2P_MSG_6 … #define mmSMU_MP1_SRBM2P_MSG_7 … #define mmSMU_MP1_SRBM2P_MSG_8 … #define mmSMU_MP1_SRBM2P_MSG_9 … #define mmSMU_MP1_SRBM2P_MSG_10 … #define mmSMU_MP1_SRBM2P_MSG_11 … #define mmSMU_MP1_SRBM2P_MSG_12 … #define mmSMU_MP1_SRBM2P_MSG_13 … #define mmSMU_MP1_SRBM2P_MSG_14 … #define mmSMU_MP1_SRBM2P_MSG_15 … #define mmSMU_MP1_SRBM2P_RESP_0 … #define mmSMU_MP1_SRBM2P_RESP_1 … #define mmSMU_MP1_SRBM2P_RESP_2 … #define mmSMU_MP1_SRBM2P_RESP_3 … #define mmSMU_MP1_SRBM2P_RESP_4 … #define mmSMU_MP1_SRBM2P_RESP_5 … #define mmSMU_MP1_SRBM2P_RESP_6 … #define mmSMU_MP1_SRBM2P_RESP_7 … #define mmSMU_MP1_SRBM2P_RESP_8 … #define mmSMU_MP1_SRBM2P_RESP_9 … #define mmSMU_MP1_SRBM2P_RESP_10 … #define mmSMU_MP1_SRBM2P_RESP_11 … #define mmSMU_MP1_SRBM2P_RESP_12 … #define mmSMU_MP1_SRBM2P_RESP_13 … #define mmSMU_MP1_SRBM2P_RESP_14 … #define mmSMU_MP1_SRBM2P_RESP_15 … #define mmSMU_MP1_SRBM2P_ARG_0 … #define mmSMU_MP1_SRBM2P_ARG_1 … #define mmSMU_MP1_SRBM2P_ARG_2 … #define mmSMU_MP1_SRBM2P_ARG_3 … #define mmSMU_MP1_SRBM2P_ARG_4 … #define mmSMU_MP1_SRBM2P_ARG_5 … #define mmSMU_MP1_SRBM2P_ARG_6 … #define mmSMU_MP1_SRBM2P_ARG_7 … #define mmSMU_MP1_SRBM2P_ARG_8 … #define mmSMU_MP1_SRBM2P_ARG_9 … #define mmSMU_MP1_SRBM2P_ARG_10 … #define mmSMU_MP1_SRBM2P_ARG_11 … #define mmSMU_MP1_SRBM2P_ARG_12 … #define mmSMU_MP1_SRBM2P_ARG_13 … #define mmSMU_MP1_SRBM2P_ARG_14 … #define mmSMU_MP1_SRBM2P_ARG_15 … #define mmSMU_MP1_ACP2MP_RESP … #define mmSMU_MP1_DC2MP_RESP … #define mmSMU_MP1_UVD2MP_RESP … #define mmSMU_MP1_VCE2MP_RESP … #define mmSMU_MP1_RLC2MP_RESP … #define mmMP_FPS_CNT … #define mmSMU_DISP0_TIMER_INT_CONTROL … #define mmSMU_DISP1_TIMER_INT_CONTROL … #define mmSMU_SRBM_CONFIG … #define ixMP_FPS_CNT_XBAR … #define ixMP_SRBM_CONFIG_XBAR … #define ixMP_SRBM_CONTROL … #define ixMP_SRBM_ACCVIO_LOG … #define ixMP_SRBM_ACCVIO_ADDR … #define ixMP_CRBBM_CONTROL … #define ixMP_CRBBM_ACCVIO_LOG … #define ixMP_CRBBM_ACCVIO_ADDR … #define ixMP_DRAM_CNTL_WRREQ_CNTL … #define ixMP_DRAM_CNTL_WRREQ_CNTL_1 … #define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR … #define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR … #define ixMP_DRAM_CNTL_WRREQ_MASK … #define ixMP_DRAM_CNTL_WRREQ_DATA_0 … #define ixMP_DRAM_CNTL_WRREQ_DATA_1 … #define ixMP_DRAM_CNTL_WRREQ_DATA_2 … #define ixMP_DRAM_CNTL_WRREQ_DATA_3 … #define ixMP_DRAM_CNTL_WRREQ_DATA_4 … #define ixMP_DRAM_CNTL_WRREQ_DATA_5 … #define ixMP_DRAM_CNTL_WRREQ_DATA_6 … #define ixMP_DRAM_CNTL_WRREQ_DATA_7 … #define ixMP_DRAM_CNTL_WRREQ_STATUS … #define ixMP_DRAM_CNTL_WRRET_STATUS_0 … #define ixMP_DRAM_CNTL_RDREQ_ADDR … #define ixMP_DRAM_CNTL_RDREQ_CNTL … #define ixMP_DRAM_CNTL_RDREQ_CNTL_1 … #define ixMP_DRAM_CNTL_RDRET_VALID … #define ixMP_DRAM_CNTL_RDRET_NACK … #define ixMP_DRAM_CNTL_RDRET_DATA_0 … #define ixMP_DRAM_CNTL_RDRET_DATA_1 … #define ixMP_DRAM_CNTL_RDRET_DATA_2 … #define ixMP_DRAM_CNTL_RDRET_DATA_3 … #define ixMP_DRAM_CNTL_RDRET_DATA_4 … #define ixMP_DRAM_CNTL_RDRET_DATA_5 … #define ixMP_DRAM_CNTL_RDRET_DATA_6 … #define ixMP_DRAM_CNTL_RDRET_DATA_7 … #define ixMP_DRAM_CNTL_RDRET_DATA_8 … #define ixMP_DRAM_CNTL_RDRET_DATA_9 … #define ixMP_DRAM_CNTL_RDRET_DATA_10 … #define ixMP_DRAM_CNTL_RDRET_DATA_11 … #define ixMP_DRAM_CNTL_RDRET_DATA_12 … #define ixMP_DRAM_CNTL_RDRET_DATA_13 … #define ixMP_DRAM_CNTL_RDRET_DATA_14 … #define ixMP_DRAM_CNTL_RDRET_DATA_15 … #define ixMP_DRAM_CNTL_RDRET_DATA_16 … #define ixMP_DRAM_CNTL_RDRET_DATA_17 … #define ixMP_DRAM_CNTL_RDRET_DATA_18 … #define ixMP_DRAM_CNTL_RDRET_DATA_19 … #define ixMP_DRAM_CNTL_RDRET_DATA_20 … #define ixMP_DRAM_CNTL_RDRET_DATA_21 … #define ixMP_DRAM_CNTL_RDRET_DATA_22 … #define ixMP_DRAM_CNTL_RDRET_DATA_23 … #define ixMP_DRAM_CNTL_RDRET_DATA_24 … #define ixMP_DRAM_CNTL_RDRET_DATA_25 … #define ixMP_DRAM_CNTL_RDRET_DATA_26 … #define ixMP_DRAM_CNTL_RDRET_DATA_27 … #define ixMP_DRAM_CNTL_RDRET_DATA_28 … #define ixMP_DRAM_CNTL_RDRET_DATA_29 … #define ixMP_DRAM_CNTL_RDRET_DATA_30 … #define ixMP_DRAM_CNTL_RDRET_DATA_31 … #define ixMP_DRAM_CNTL_RDRET_DATA_32 … #define ixMP_DRAM_CNTL_RDRET_DATA_33 … #define ixMP_DRAM_CNTL_RDRET_DATA_34 … #define ixMP_DRAM_CNTL_RDRET_DATA_35 … #define ixMP_DRAM_CNTL_RDRET_DATA_36 … #define ixMP_DRAM_CNTL_RDRET_DATA_37 … #define ixMP_DRAM_CNTL_RDRET_DATA_38 … #define ixMP_DRAM_CNTL_RDRET_DATA_39 … #define ixMP_DRAM_CNTL_RDRET_DATA_40 … #define ixMP_DRAM_CNTL_RDRET_DATA_41 … #define ixMP_DRAM_CNTL_RDRET_DATA_42 … #define ixMP_DRAM_CNTL_RDRET_DATA_43 … #define ixMP_DRAM_CNTL_RDRET_DATA_44 … #define ixMP_DRAM_CNTL_RDRET_DATA_45 … #define ixMP_DRAM_CNTL_RDRET_DATA_46 … #define ixMP_DRAM_CNTL_RDRET_DATA_47 … #define ixMP_DRAM_CNTL_RDRET_DATA_48 … #define ixMP_DRAM_CNTL_RDRET_DATA_49 … #define ixMP_DRAM_CNTL_RDRET_DATA_50 … #define ixMP_DRAM_CNTL_RDRET_DATA_51 … #define ixMP_DRAM_CNTL_RDRET_DATA_52 … #define ixMP_DRAM_CNTL_RDRET_DATA_53 … #define ixMP_DRAM_CNTL_RDRET_DATA_54 … #define ixMP_DRAM_CNTL_RDRET_DATA_55 … #define ixMP_DRAM_CNTL_RDRET_DATA_56 … #define ixMP_DRAM_CNTL_RDRET_DATA_57 … #define ixMP_DRAM_CNTL_RDRET_DATA_58 … #define ixMP_DRAM_CNTL_RDRET_DATA_59 … #define ixMP_DRAM_CNTL_RDRET_DATA_60 … #define ixMP_DRAM_CNTL_RDRET_DATA_61 … #define ixMP_DRAM_CNTL_RDRET_DATA_62 … #define ixMP_DRAM_CNTL_RDRET_DATA_63 … #define ixMP_IOC_CTRL … #define ixMP_IOC_RDDATA … #define ixMP_IOC_PHASE1 … #define ixMP_IOC_PHASE2 … #define ixMP_IOC_PHASE3 … #define ixMP_IOC_READ_0 … #define ixMP_IOC_READ_1 … #define ixMP_IOC_READ_2 … #define ixMP_IOC_READ_3 … #define ixMP_IOC_READ_4 … #define ixMP_IOC_READ_5 … #define ixMP_IOC_READ_6 … #define ixMP_IOC_READ_7 … #define ixMP_IOC_READ_8 … #define ixMP_IOC_READ_9 … #define ixMP_IOC_READ_10 … #define ixMP_IOC_READ_11 … #define ixMP_IOC_READ_12 … #define ixMP_IOC_READ_13 … #define ixMP_IOC_READ_14 … #define ixMP_IOC_READ_15 … #define ixMP_IOC_WRITE_0 … #define ixMP_IOC_WRITE_1 … #define ixMP_IOC_WRITE_2 … #define ixMP_IOC_WRITE_3 … #define ixMP_IOC_WRITE_4 … #define ixMP_IOC_WRITE_5 … #define ixMP_IOC_WRITE_6 … #define ixMP_IOC_WRITE_7 … #define ixMP_IOC_WRITE_8 … #define ixMP_IOC_WRITE_9 … #define ixMP_IOC_WRITE_10 … #define ixMP_IOC_WRITE_11 … #define ixMP_IOC_WRITE_12 … #define ixMP_IOC_WRITE_13 … #define ixMP_IOC_WRITE_14 … #define ixMP_IOC_WRITE_15 … #define ixMP_INTERRUPT_CONTROL … #define ixMP0_SW_INT … #define ixMP0_SW_INT_CTXID … #define ixMP1_SW_INT … #define ixMP1_SW_INT_CTXID … #define ixDISP_TIMER_ID … #define mmPWRHW_SMC_IND_INDEX … #define mmPWRHW0_PWRHW_SMC_IND_INDEX … #define mmPWRHW1_PWRHW_SMC_IND_INDEX … #define mmPWRHW2_PWRHW_SMC_IND_INDEX … #define mmPWRHW3_PWRHW_SMC_IND_INDEX … #define mmPWRHW_SMC_IND_DATA … #define mmPWRHW0_PWRHW_SMC_IND_DATA … #define mmPWRHW1_PWRHW_SMC_IND_DATA … #define mmPWRHW2_PWRHW_SMC_IND_DATA … #define mmPWRHW3_PWRHW_SMC_IND_DATA … #define ixCURRENT_STATE_CPU0 … #define ixCURRENT_STATE_CPU1 … #define ixCPU_REDUN_DONE0 … #define ixCPU_REDUN_DONE1 … #define ixCURRENT_VID_CPU0 … #define ixCURRENT_VID_CPU1 … #define ixUNBPM_PWRMGT_ACK … #define ixCURRENT_FREQ_STATE_NB … #define ixCURRENT_PSTATE_NB … #define ixUNBPM_MSG_INT_CONFIG … #define ixUNBPM_NBPWRMGT_CMD … #define ixUNBPM_NBPWRMGT_FSM_CFG … #define ixDDR0_FUSE_SSB_XFER … #define ixDDR0_FUSE_SSB_XFER_CFG … #define ixDDR1_FUSE_SSB_XFER … #define ixDDR1_FUSE_SSB_XFER_CFG … #define ixUNBPM_FUSES_VAL_PWROK … #define ixSYNFIFO_CLK_RATIO … #define ixMISC_SMU_PWRMGT_CFG0 … #define ixMISC_GNB_PWRMGT_CFG1 … #define ixMISC_SMU_PWRMGT_CFG1 … #define ixMISC_GNB_PWRMGT_DATA … #define ixGN_GNB_SLOW … #define ixGN_FORCE_NBPS1 … #define ixMISC_SMU_PWRMGT_DATA … #define ixNB_COF … #define ixUNBPM_CK_IRESET … #define ixCURRENT_VID_NB … #define ixSPR_FUSE_PSTATEPWR1 … #define ixSPR_FUSE_PSTATEPWR2 … #define ixSPR_FUSE_PSTATEPWR3 … #define ixSPR_FUSE_THERMAL_SCRATCH … #define ixSPR_PRODUCT_INFO0 … #define ixSPR_SERIALNUM_REG1 … #define ixSPR_SERIALNUM_REG2 … #define ixSPR_PRODUCT_INFO1 … #define ixSPR_EXT_PRODUCT_INFO … #define ixSPR_MSIDFUSE … #define ixSPR_LINK_PRODUCT_INFO … #define ixSPR_BRAND_NAME_ADDR … #define ixSPR_BRAND_NAME_DATA … #define ixSPR_COMBO_PHY_PRODUCT_INFO … #define ixMISC_GNB_PWRMGT_CFG0 … #define ixUNBPM_EXIT_TO_PSTATE … #define ixUNBPM_WARM_RESET_HS_STATUS … #define ixUNBPM_VOLTAGE_CNTL … #define ixUNBPM_VOLTAGE_STATUS … #define ixNUM_BOOST_STATES … #define ixWARM_RESET_NB_CONTROL … #define ixONION_NO_STREAMS_PEND … #define ixSPR_PROGRAMMABLE_CTRL … #define ixPHN_FUSERX_MISC_FUSES … #define ixUNBPM_PWRCTRL_MISC … #define ixCSTATE_ACTIVE_SAMPLER … #define ixUNBPM_DEBUG_CONFIG_STATUS … #define ixUNBPM_AXIMST_LAST_CMD … #define ixUNB_IF_INTRGEN_LAST_SENT … #define ixUNBPM_DEBUG_BUS_CNTL … #define ixUNBPM_PWRMGT_REQ_DBG_STATUS … #define ixUNBPM_VIDCHG_REQ_DBG_STATUS … #define ixUNBPM_SCRATCH_0 … #define ixUNBPM_SCRATCH_1 … #define ixPOWERON_CPU_0 … #define ixPOWERREADY_CPU_0 … #define ixPGRUNFEEDBACK_CPU_0 … #define ixRCC3ON_CPU_0 … #define ixRCC3EXITDONE_CPU_0 … #define ixCORE_FUNC_LATE_SSB_XFER_0 … #define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 … #define ixCORE_REDUN_SSB_XFER_0 … #define ixCORE_REDUN_SSB_XFER_CFG_0 … #define ixCORE_APM_SSB_XFER_0 … #define ixCORE_APM_SSB_XFER_CFG_0 … #define ixCOREPM_PWRCTRL_MISC_0 … #define ixLDOIVRON_CPU_0 … #define ixLDOIVREXITDONE_CPU_0 … #define ixRCC3_TARGETPSMREF_CPU_0 … #define ixIVR_TARGETPSMREF_CPU_0 … #define ixCK_JTCOOLRESET_LATCHED_CPU_0 … #define ixCK_DISABLECORE_CPU_0 … #define ixCOREPM_ID_0 … #define ixCOREPM_SCRATCH_0 … #define ixRCC3_WAKEMIN_CPU_0 … #define ixSPMI_CONFIG0_0 … #define ixSPMI_CONFIG1_0 … #define ixSPMI_FSM_READ_TRIGGER_0 … #define ixSPMI_FSM_WRITE_TRIGGER_0 … #define ixSPMI_FSM_RESET_TRIGGER_0 … #define ixSPMI_FSM_BUSY_0 … #define ixSPMI_PATH_0 … #define ixSPMI_C6_STATE_0 … #define ixSPMI_JTAG_OVER_0 … #define ixSPMI_SRAM_ADDRESS_0 … #define ixSPMI_SRAM_DATA_0 … #define ixSPMI_RESET_0 … #define ixSPMI_FORCE_CLOCK_GATERS_0 … #define ixSPMI_SPARE_0 … #define ixSPMI_SPARE_EX_0 … #define ixSPMI_SRAM_CLK_GATER_0 … #define ixPOWERON_CPU_1 … #define ixPOWERREADY_CPU_1 … #define ixPGRUNFEEDBACK_CPU_1 … #define ixRCC3ON_CPU_1 … #define ixRCC3EXITDONE_CPU_1 … #define ixCORE_FUNC_LATE_SSB_XFER_1 … #define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 … #define ixCORE_REDUN_SSB_XFER_1 … #define ixCORE_REDUN_SSB_XFER_CFG_1 … #define ixCORE_APM_SSB_XFER_1 … #define ixCORE_APM_SSB_XFER_CFG_1 … #define ixCOREPM_PWRCTRL_MISC_1 … #define ixLDOIVRON_CPU_1 … #define ixLDOIVREXITDONE_CPU_1 … #define ixRCC3_TARGETPSMREF_CPU_1 … #define ixIVR_TARGETPSMREF_CPU_1 … #define ixCK_JTCOOLRESET_LATCHED_CPU_1 … #define ixCK_DISABLECORE_CPU_1 … #define ixCOREPM_ID_1 … #define ixCOREPM_SCRATCH_1 … #define ixRCC3_WAKEMIN_CPU_1 … #define ixSPMI_CONFIG0_1 … #define ixSPMI_CONFIG1_1 … #define ixSPMI_FSM_READ_TRIGGER_1 … #define ixSPMI_FSM_WRITE_TRIGGER_1 … #define ixSPMI_FSM_RESET_TRIGGER_1 … #define ixSPMI_FSM_BUSY_1 … #define ixSPMI_PATH_1 … #define ixSPMI_C6_STATE_1 … #define ixSPMI_JTAG_OVER_1 … #define ixSPMI_SRAM_ADDRESS_1 … #define ixSPMI_SRAM_DATA_1 … #define ixSPMI_RESET_1 … #define ixSPMI_FORCE_CLOCK_GATERS_1 … #define ixSPMI_SPARE_1 … #define ixSPMI_SPARE_EX_1 … #define ixSPMI_SRAM_CLK_GATER_1 … #define ixGENERAL_PWRMGT … #define ixCNB_PWRMGT_CNTL … #define ixSCLK_PWRMGT_CNTL … #define ixTARGET_AND_CURRENT_PROFILE_INDEX … #define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 … #define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 … #define ixCG_FREQ_TRAN_VOTING_0 … #define ixCG_FREQ_TRAN_VOTING_1 … #define ixCG_FREQ_TRAN_VOTING_2 … #define ixCG_FREQ_TRAN_VOTING_3 … #define ixCG_FREQ_TRAN_VOTING_4 … #define ixCG_FREQ_TRAN_VOTING_5 … #define ixCG_FREQ_TRAN_VOTING_6 … #define ixCG_FREQ_TRAN_VOTING_7 … #define ixCG_STATIC_SCREEN_PARAMETER … #define ixCG_ACPI_CNTL … #define ixSCLK_DEEP_SLEEP_CNTL … #define ixSCLK_DEEP_SLEEP_CNTL2 … #define ixSCLK_DEEP_SLEEP_CNTL3 … #define ixSCLK_DEEP_SLEEP_MISC_CNTL … #define ixLCLK_DEEP_SLEEP_CNTL … #define ixLCLK_DEEP_SLEEP_CNTL2 … #define ixSMU_VOLTAGE_STATUS … #define ixCG_ULV_PARAMETER … #define ixPWR_DC_RESP … #define ixPWR_VCE_RESP … #define ixPWR_UVD_RESP … #define ixPWR_ACP_RESP … #define ixPWR_DC_REQ … #define ixSCLK_MIN_DIV … #define ixPCIE_PGFSM_CONFIG … #define ixPCIE_PGFSM_WRITE … #define ixSERDES_BUSY … #define ixPCIE_PGFSM2_CONFIG … #define ixPCIE_PGFSM2_WRITE … #define ixSERDES2_BUSY … #define ixPCIE_PGFSM_0_READ … #define ixPCIE_PGFSM_1_READ … #define ixPWR_ACPI_INTERRUPT … #define ixVDDGFX_IDLE_PARAMETER … #define ixVDDGFX_IDLE_CONTROL … #define ixVDDGFX_IDLE_EXIT … #define ixREG_SCLK_DEEP_SLEEP_EXIT … #define ixCAC_WEIGHT_LKG_DC_3 … #define ixLCAC_MC0_CNTL … #define ixLCAC_MC0_OVR_SEL … #define ixLCAC_MC0_OVR_VAL … #define ixLCAC_MC1_CNTL … #define ixLCAC_MC1_OVR_SEL … #define ixLCAC_MC1_OVR_VAL … #define ixLCAC_MC2_CNTL … #define ixLCAC_MC2_OVR_SEL … #define ixLCAC_MC2_OVR_VAL … #define ixLCAC_MC3_CNTL … #define ixLCAC_MC3_OVR_SEL … #define ixLCAC_MC3_OVR_VAL … #define ixLCAC_CPL_CNTL … #define ixLCAC_CPL_OVR_SEL … #define ixLCAC_CPL_OVR_VAL … #define ixMISC_UNB_PWRMGT_CFG0 … #define ixMISC_UNB_PWRMGT_CFG1 … #define ixMISC_UNB_PWRMGT_DATA … #define ixGNBPM_SMU_PWRMGT_DATA … #define ixDMA_ACTIVE_SAMPLER_CFG … #define ixSOUTHBRIDGE_TYPE … #define ixGNBPM_SMU_PWRMGT_STATUS … #define ixALLOW_SR_INTR_CTRL … #define mmGC_CAC_LKG_AGGR_LOWER … #define mmGC_CAC_LKG_AGGR_UPPER … #define ixGC_CAC_WEIGHT_CU_0 … #define ixGC_CAC_WEIGHT_CU_1 … #define ixGC_CAC_WEIGHT_CU_2 … #define ixGC_CAC_WEIGHT_CU_3 … #define ixGC_CAC_ACC_CU0 … #define ixGC_CAC_ACC_CU1 … #define ixGC_CAC_ACC_CU2 … #define ixGC_CAC_ACC_CU3 … #define ixGC_CAC_ACC_CU4 … #define ixGC_CAC_ACC_CU5 … #define ixGC_CAC_ACC_CU6 … #define ixGC_CAC_ACC_CU7 … #define ixGC_CAC_OVRD_CU … #endif /* SMU_8_0_D_H */
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