#ifndef SMU72_H
#define SMU72_H
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
#define SMU__NUM_SCLK_DPM_STATE …
#define SMU__NUM_MCLK_DPM_LEVELS …
#define SMU__NUM_LCLK_DPM_LEVELS …
#define SMU__NUM_PCIE_DPM_LEVELS …
enum SID_OPTION { … };
enum Poly3rdOrderCoeff { … };
struct SMU7_Poly3rdOrder_Data { … };
SMU7_Poly3rdOrder_Data;
struct Power_Calculator_Data { … };
PowerCalculatorData_t;
struct Gc_Cac_Weight_Data { … };
GcCacWeight_Data;
data_64_t;
data_128_t;
#define SMU7_CONTEXT_ID_SMC …
#define SMU7_CONTEXT_ID_VBIOS …
#define SMU72_MAX_LEVELS_VDDC …
#define SMU72_MAX_LEVELS_VDDGFX …
#define SMU72_MAX_LEVELS_VDDCI …
#define SMU72_MAX_LEVELS_MVDD …
#define SMU_MAX_SMIO_LEVELS …
#define SMU72_MAX_LEVELS_GRAPHICS …
#define SMU72_MAX_LEVELS_MEMORY …
#define SMU72_MAX_LEVELS_GIO …
#define SMU72_MAX_LEVELS_LINK …
#define SMU72_MAX_LEVELS_UVD …
#define SMU72_MAX_LEVELS_VCE …
#define SMU72_MAX_LEVELS_ACP …
#define SMU72_MAX_LEVELS_SAMU …
#define SMU72_MAX_ENTRIES_SMIO …
#define DPM_NO_LIMIT …
#define DPM_NO_UP …
#define DPM_GO_DOWN …
#define DPM_GO_UP …
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL …
#define SMU7_FIRST_DPM_MEMORY_LEVEL …
#define GPIO_CLAMP_MODE_VRHOT …
#define GPIO_CLAMP_MODE_THERM …
#define GPIO_CLAMP_MODE_DC …
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT …
#define SCRATCH_B_TARG_PCIE_INDEX_MASK …
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT …
#define SCRATCH_B_CURR_PCIE_INDEX_MASK …
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT …
#define SCRATCH_B_TARG_UVD_INDEX_MASK …
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT …
#define SCRATCH_B_CURR_UVD_INDEX_MASK …
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT …
#define SCRATCH_B_TARG_VCE_INDEX_MASK …
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT …
#define SCRATCH_B_CURR_VCE_INDEX_MASK …
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT …
#define SCRATCH_B_TARG_ACP_INDEX_MASK …
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT …
#define SCRATCH_B_CURR_ACP_INDEX_MASK …
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT …
#define SCRATCH_B_TARG_SAMU_INDEX_MASK …
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT …
#define SCRATCH_B_CURR_SAMU_INDEX_MASK …
#define CG_XDMA_MASK …
#define CG_XDMA_SHIFT …
#define CG_UVD_MASK …
#define CG_UVD_SHIFT …
#define CG_VCE_MASK …
#define CG_VCE_SHIFT …
#define CG_SAMU_MASK …
#define CG_SAMU_SHIFT …
#define CG_GFX_MASK …
#define CG_GFX_SHIFT …
#define CG_SDMA_MASK …
#define CG_SDMA_SHIFT …
#define CG_HDP_MASK …
#define CG_HDP_SHIFT …
#define CG_MC_MASK …
#define CG_MC_SHIFT …
#define CG_DRM_MASK …
#define CG_DRM_SHIFT …
#define CG_ROM_MASK …
#define CG_ROM_SHIFT …
#define CG_BIF_MASK …
#define CG_BIF_SHIFT …
#define SMU72_DTE_ITERATIONS …
#define SMU72_DTE_SOURCES …
#define SMU72_DTE_SINKS …
#define SMU72_NUM_CPU_TES …
#define SMU72_NUM_GPU_TES …
#define SMU72_NUM_NON_TES …
#define SMU72_DTE_FAN_SCALAR_MIN …
#define SMU72_DTE_FAN_SCALAR_MAX …
#define SMU72_DTE_FAN_TEMP_MAX …
#define SMU72_DTE_FAN_TEMP_MIN …
#if defined SMU__FUSION_ONLY
#define SMU7_DTE_ITERATIONS …
#define SMU7_DTE_SOURCES …
#define SMU7_DTE_SINKS …
#define SMU7_NUM_CPU_TES …
#define SMU7_NUM_GPU_TES …
#define SMU7_NUM_NON_TES …
#endif
struct SMU7_HystController_Data { … };
SMU7_HystController_Data;
struct SMU72_PIDController { … };
SMU72_PIDController;
struct SMU7_LocalDpmScoreboard { … };
SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS …
VoltageChangeHandler_t;
struct SMU_VoltageLevel { … };
SMU_VoltageLevel;
struct SMU7_VoltageScoreboard { … };
SMU7_VoltageScoreboard;
#define SMU7_MAX_PCIE_LINK_SPEEDS …
struct SMU7_PCIeLinkSpeedScoreboard { … };
SMU7_PCIeLinkSpeedScoreboard;
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES …
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES …
#define SMU7_SCALE_I …
#define SMU7_SCALE_R …
struct SMU7_PowerScoreboard { … };
SMU7_PowerScoreboard;
struct SMU7_ThermalScoreboard { … };
SMU7_ThermalScoreboard;
#define SMU7_SCLK_DPM_CONFIG_MASK …
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK …
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK …
#define SMU7_MCLK_DPM_CONFIG_MASK …
#define SMU7_UVD_DPM_CONFIG_MASK …
#define SMU7_VCE_DPM_CONFIG_MASK …
#define SMU7_ACP_DPM_CONFIG_MASK …
#define SMU7_SAMU_DPM_CONFIG_MASK …
#define SMU7_PCIEGEN_DPM_CONFIG_MASK …
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE …
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE …
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE …
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE …
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE …
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE …
struct SMU72_SoftRegisters { … };
SMU72_SoftRegisters;
struct SMU72_Firmware_Header { … };
SMU72_Firmware_Header;
#define SMU72_FIRMWARE_HEADER_LOCATION …
enum DisplayConfig { … };
#define MC_BLOCK_COUNT …
#define CPL_BLOCK_COUNT …
#define SE_BLOCK_COUNT …
#define GC_BLOCK_COUNT …
struct SMU7_Local_Cac { … };
SMU7_Local_Cac;
struct SMU7_Local_Cac_Table { … };
SMU7_Local_Cac_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#define CG_SYS_BITMASK_FIRST_BIT …
#define CG_SYS_BITMASK_LAST_BIT …
#define CG_SYS_BIF_MGLS_SHIFT …
#define CG_SYS_ROM_SHIFT …
#define CG_SYS_MC_MGCG_SHIFT …
#define CG_SYS_MC_MGLS_SHIFT …
#define CG_SYS_SDMA_MGCG_SHIFT …
#define CG_SYS_SDMA_MGLS_SHIFT …
#define CG_SYS_DRM_MGCG_SHIFT …
#define CG_SYS_HDP_MGCG_SHIFT …
#define CG_SYS_HDP_MGLS_SHIFT …
#define CG_SYS_DRM_MGLS_SHIFT …
#define CG_SYS_BIF_MGLS_MASK …
#define CG_SYS_ROM_MASK …
#define CG_SYS_MC_MGCG_MASK …
#define CG_SYS_MC_MGLS_MASK …
#define CG_SYS_SDMA_MGCG_MASK …
#define CG_SYS_SDMA_MGLS_MASK …
#define CG_SYS_DRM_MGCG_MASK …
#define CG_SYS_HDP_MGCG_MASK …
#define CG_SYS_HDP_MGLS_MASK …
#define CG_SYS_DRM_MGLS_MASK …
#define CG_GFX_BITMASK_FIRST_BIT …
#define CG_GFX_BITMASK_LAST_BIT …
#define CG_GFX_CGCG_SHIFT …
#define CG_GFX_CGLS_SHIFT …
#define CG_CPF_MGCG_SHIFT …
#define CG_RLC_MGCG_SHIFT …
#define CG_GFX_OTHERS_MGCG_SHIFT …
#define CG_GFX_CGCG_MASK …
#define CG_GFX_CGLS_MASK …
#define CG_CPF_MGCG_MASK …
#define CG_RLC_MGCG_MASK …
#define CG_GFX_OTHERS_MGCG_MASK …
#define VRCONF_VDDC_MASK …
#define VRCONF_VDDC_SHIFT …
#define VRCONF_VDDGFX_MASK …
#define VRCONF_VDDGFX_SHIFT …
#define VRCONF_VDDCI_MASK …
#define VRCONF_VDDCI_SHIFT …
#define VRCONF_MVDD_MASK …
#define VRCONF_MVDD_SHIFT …
#define VR_MERGED_WITH_VDDC …
#define VR_SVI2_PLANE_1 …
#define VR_SVI2_PLANE_2 …
#define VR_SMIO_PATTERN_1 …
#define VR_SMIO_PATTERN_2 …
#define VR_STATIC_VOLTAGE …
#define CLOCK_STRETCHER_MAX_ENTRIES …
#define CKS_LOOKUPTable_MAX_ENTRIES …
#define CLOCK_STRETCHER_SETTING_DDT_MASK …
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT …
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK …
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT …
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK …
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT …
struct SMU_ClockStretcherDataTableEntry { … };
SMU_ClockStretcherDataTableEntry;
struct SMU_ClockStretcherDataTable { … };
SMU_ClockStretcherDataTable;
struct SMU_CKS_LOOKUPTableEntry { … };
SMU_CKS_LOOKUPTableEntry;
struct SMU_CKS_LOOKUPTable { … };
SMU_CKS_LOOKUPTable;
#endif