/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef SMU71_H #define SMU71_H #if !defined(SMC_MICROCODE) #pragma pack(push, 1) #endif #define SMU__NUM_PCIE_DPM_LEVELS … #define SMU__NUM_SCLK_DPM_STATE … #define SMU__NUM_MCLK_DPM_LEVELS … #define SMU__VARIANT__ICELAND … #define SMU__DGPU_ONLY … #define SMU__DYNAMIC_MCARB_SETTINGS … enum SID_OPTION { … }; data_64_t; data_128_t; #define SMU7_CONTEXT_ID_SMC … #define SMU7_CONTEXT_ID_VBIOS … #define SMU71_MAX_LEVELS_VDDC … #define SMU71_MAX_LEVELS_VDDCI … #define SMU71_MAX_LEVELS_MVDD … #define SMU71_MAX_LEVELS_VDDNB … #define SMU71_MAX_LEVELS_GRAPHICS … #define SMU71_MAX_LEVELS_MEMORY … #define SMU71_MAX_LEVELS_GIO … #define SMU71_MAX_LEVELS_LINK … #define SMU71_MAX_ENTRIES_SMIO … #define DPM_NO_LIMIT … #define DPM_NO_UP … #define DPM_GO_DOWN … #define DPM_GO_UP … #define SMU7_FIRST_DPM_GRAPHICS_LEVEL … #define SMU7_FIRST_DPM_MEMORY_LEVEL … #define GPIO_CLAMP_MODE_VRHOT … #define GPIO_CLAMP_MODE_THERM … #define GPIO_CLAMP_MODE_DC … #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT … #define SCRATCH_B_TARG_PCIE_INDEX_MASK … #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT … #define SCRATCH_B_CURR_PCIE_INDEX_MASK … #define SCRATCH_B_TARG_UVD_INDEX_SHIFT … #define SCRATCH_B_TARG_UVD_INDEX_MASK … #define SCRATCH_B_CURR_UVD_INDEX_SHIFT … #define SCRATCH_B_CURR_UVD_INDEX_MASK … #define SCRATCH_B_TARG_VCE_INDEX_SHIFT … #define SCRATCH_B_TARG_VCE_INDEX_MASK … #define SCRATCH_B_CURR_VCE_INDEX_SHIFT … #define SCRATCH_B_CURR_VCE_INDEX_MASK … #define SCRATCH_B_TARG_ACP_INDEX_SHIFT … #define SCRATCH_B_TARG_ACP_INDEX_MASK … #define SCRATCH_B_CURR_ACP_INDEX_SHIFT … #define SCRATCH_B_CURR_ACP_INDEX_MASK … #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT … #define SCRATCH_B_TARG_SAMU_INDEX_MASK … #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT … #define SCRATCH_B_CURR_SAMU_INDEX_MASK … #if defined SMU__DGPU_ONLY #define SMU71_DTE_ITERATIONS … #define SMU71_DTE_SOURCES … #define SMU71_DTE_SINKS … #define SMU71_NUM_CPU_TES … #define SMU71_NUM_GPU_TES … #define SMU71_NUM_NON_TES … #endif #if defined SMU__FUSION_ONLY #define SMU7_DTE_ITERATIONS … #define SMU7_DTE_SOURCES … #define SMU7_DTE_SINKS … #define SMU7_NUM_CPU_TES … #define SMU7_NUM_GPU_TES … #define SMU7_NUM_NON_TES … #endif struct SMU71_PIDController { … }; SMU71_PIDController; struct SMU7_LocalDpmScoreboard { … }; SMU7_LocalDpmScoreboard; #define SMU7_MAX_VOLTAGE_CLIENTS … struct SMU7_VoltageScoreboard { … }; SMU7_VoltageScoreboard; // ------------------------------------------------------------------------------------------------------------------------- #define SMU7_MAX_PCIE_LINK_SPEEDS … struct SMU7_PCIeLinkSpeedScoreboard { … }; SMU7_PCIeLinkSpeedScoreboard; // -------------------------------------------------------- CAC table ------------------------------------------------------ #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES … #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES … #define SMU7_SCALE_I … #define SMU7_SCALE_R … struct SMU7_PowerScoreboard { … }; SMU7_PowerScoreboard; // -------------------------------------------------------------------------------------------------- struct SMU7_ThermalScoreboard { … }; SMU7_ThermalScoreboard; // For FeatureEnables: #define SMU7_SCLK_DPM_CONFIG_MASK … #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK … #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK … #define SMU7_MCLK_DPM_CONFIG_MASK … #define SMU7_UVD_DPM_CONFIG_MASK … #define SMU7_VCE_DPM_CONFIG_MASK … #define SMU7_ACP_DPM_CONFIG_MASK … #define SMU7_SAMU_DPM_CONFIG_MASK … #define SMU7_PCIEGEN_DPM_CONFIG_MASK … #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE … #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE … #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE … #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE … #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE … #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE … // All 'soft registers' should be uint32_t. struct SMU71_SoftRegisters { … }; SMU71_SoftRegisters; struct SMU71_Firmware_Header { … }; SMU71_Firmware_Header; struct SMU7_HystController_Data { … }; SMU7_HystController_Data; #define SMU71_FIRMWARE_HEADER_LOCATION … enum DisplayConfig { … }; //#define SX_BLOCK_COUNT 8 //#define MC_BLOCK_COUNT 1 //#define CPL_BLOCK_COUNT 27 #if defined SMU__VARIANT__ICELAND #define SX_BLOCK_COUNT … #define MC_BLOCK_COUNT … #define CPL_BLOCK_COUNT … #endif struct SMU7_Local_Cac { … }; SMU7_Local_Cac; struct SMU7_Local_Cac_Table { … }; SMU7_Local_Cac_Table; #if !defined(SMC_MICROCODE) #pragma pack(pop) #endif #endif
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