#ifndef _SMU7_HWMGR_H
#define _SMU7_HWMGR_H
#include "hwmgr.h"
#include "ppatomctrl.h"
#define SMU7_MAX_HARDWARE_POWERLEVELS …
#define SMU7_VOLTAGE_CONTROL_NONE …
#define SMU7_VOLTAGE_CONTROL_BY_GPIO …
#define SMU7_VOLTAGE_CONTROL_BY_SVID2 …
#define SMU7_VOLTAGE_CONTROL_MERGED …
enum gpu_pt_config_reg_type { … };
struct gpu_pt_config_reg { … };
struct smu7_performance_level { … };
struct smu7_thermal_temperature_setting { … };
struct smu7_uvd_clocks { … };
struct smu7_vce_clocks { … };
struct smu7_power_state { … };
struct smu7_dpm_level { … };
#define SMU7_MAX_DEEPSLEEP_DIVIDER_ID …
#define MAX_REGULAR_DPM_NUMBER …
#define SMU7_MINIMUM_ENGINE_CLOCK …
struct smu7_single_dpm_table { … };
struct smu7_dpm_table { … };
struct smu7_clock_registers { … };
#define DISABLE_MC_LOADMICROCODE …
#define DISABLE_MC_CFGPROGRAMMING …
struct smu7_voltage_smio_registers { … };
#define SMU7_MAX_LEAKAGE_COUNT …
struct smu7_leakage_voltage { … };
struct smu7_vbios_boot_state { … };
struct smu7_display_timing { … };
struct smu7_dpmlevel_enable_mask { … };
struct smu7_pcie_perf_range { … };
struct smu7_odn_clock_voltage_dependency_table { … };
struct smu7_odn_dpm_table { … };
struct profile_mode_setting { … };
struct smu7_mclk_latency_entries { … };
struct smu7_mclk_latency_table { … };
struct smu7_hwmgr { … };
#define SMU7_Q88_FORMAT_CONVERSION_UNIT …
enum SMU7_I2CLineID { … };
#define SMU7_I2C_DDC1DATA …
#define SMU7_I2C_DDC1CLK …
#define SMU7_I2C_DDC2DATA …
#define SMU7_I2C_DDC2CLK …
#define SMU7_I2C_DDC3DATA …
#define SMU7_I2C_DDC3CLK …
#define SMU7_I2C_SDA …
#define SMU7_I2C_SCL …
#define SMU7_I2C_DDC4DATA …
#define SMU7_I2C_DDC4CLK …
#define SMU7_I2C_DDC5DATA …
#define SMU7_I2C_DDC5CLK …
#define SMU7_I2C_DDC6DATA …
#define SMU7_I2C_DDC6CLK …
#define SMU7_I2C_DDCVGADATA …
#define SMU7_I2C_DDCVGACLK …
#define SMU7_UNUSED_GPIO_PIN …
uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
uint32_t clock_insr);
#endif