/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _FIJI_PP_SMC_H_ #define _FIJI_PP_SMC_H_ #pragma pack(push, 1) #define PPSMC_SWSTATE_FLAG_DC … #define PPSMC_SWSTATE_FLAG_UVD … #define PPSMC_SWSTATE_FLAG_VCE … #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL … #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL … #define PPSMC_THERMAL_PROTECT_TYPE_NONE … #define PPSMC_SYSTEMFLAG_GPIO_DC … #define PPSMC_SYSTEMFLAG_STEPVDDC … #define PPSMC_SYSTEMFLAG_GDDR5 … #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP … #define PPSMC_SYSTEMFLAG_REGULATOR_HOT … #define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG … #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK … #define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK … #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE … #define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE … /* Defines for DPM 2.0 */ #define PPSMC_DPM2FLAGS_TDPCLMP … #define PPSMC_DPM2FLAGS_PWRSHFT … #define PPSMC_DPM2FLAGS_OCP … /* Defines for display watermark level */ #define PPSMC_DISPLAY_WATERMARK_LOW … #define PPSMC_DISPLAY_WATERMARK_HIGH … /* In the HW performance level's state flags: */ #define PPSMC_STATEFLAG_AUTO_PULSE_SKIP … #define PPSMC_STATEFLAG_POWERBOOST … #define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT … #define PPSMC_STATEFLAG_POWERSHIFT … #define PPSMC_STATEFLAG_SLOW_READ_MARGIN … #define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE … #define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS … /* Fan control algorithm: */ #define FDO_MODE_HARDWARE … #define FDO_MODE_PIECE_WISE_LINEAR … enum FAN_CONTROL { … }; /* Gemini Modes*/ #define PPSMC_GeminiModeNone … #define PPSMC_GeminiModeMaster … #define PPSMC_GeminiModeSlave … /* Return codes for driver to SMC communication. */ #define PPSMC_Result_OK … #define PPSMC_Result_NoMore … #define PPSMC_Result_NotNow … #define PPSMC_Result_Failed … #define PPSMC_Result_UnknownCmd … #define PPSMC_Result_UnknownVT … #define PPSMC_isERROR(x) … #define PPSMC_MSG_Halt … #define PPSMC_MSG_Resume … #define PPSMC_MSG_EnableDPMLevel … #define PPSMC_MSG_ZeroLevelsDisabled … #define PPSMC_MSG_OneLevelsDisabled … #define PPSMC_MSG_TwoLevelsDisabled … #define PPSMC_MSG_EnableThermalInterrupt … #define PPSMC_MSG_RunningOnAC … #define PPSMC_MSG_LevelUp … #define PPSMC_MSG_LevelDown … #define PPSMC_MSG_ResetDPMCounters … #define PPSMC_MSG_SwitchToSwState … #define PPSMC_MSG_SwitchToSwStateLast … #define PPSMC_MSG_SwitchToInitialState … #define PPSMC_MSG_NoForcedLevel … #define PPSMC_MSG_ForceHigh … #define PPSMC_MSG_ForceMediumOrHigh … #define PPSMC_MSG_SwitchToMinimumPower … #define PPSMC_MSG_ResumeFromMinimumPower … #define PPSMC_MSG_EnableCac … #define PPSMC_MSG_DisableCac … #define PPSMC_DPMStateHistoryStart … #define PPSMC_DPMStateHistoryStop … #define PPSMC_CACHistoryStart … #define PPSMC_CACHistoryStop … #define PPSMC_TDPClampingActive … #define PPSMC_TDPClampingInactive … #define PPSMC_StartFanControl … #define PPSMC_StopFanControl … #define PPSMC_NoDisplay … #define PPSMC_HasDisplay … #define PPSMC_MSG_UVDPowerOFF … #define PPSMC_MSG_UVDPowerON … #define PPSMC_MSG_EnableULV … #define PPSMC_MSG_DisableULV … #define PPSMC_MSG_EnterULV … #define PPSMC_MSG_ExitULV … #define PPSMC_PowerShiftActive … #define PPSMC_PowerShiftInactive … #define PPSMC_OCPActive … #define PPSMC_OCPInactive … #define PPSMC_CACLongTermAvgEnable … #define PPSMC_CACLongTermAvgDisable … #define PPSMC_MSG_InferredStateSweep_Start … #define PPSMC_MSG_InferredStateSweep_Stop … #define PPSMC_MSG_SwitchToLowestInfState … #define PPSMC_MSG_SwitchToNonInfState … #define PPSMC_MSG_AllStateSweep_Start … #define PPSMC_MSG_AllStateSweep_Stop … #define PPSMC_MSG_SwitchNextLowerInfState … #define PPSMC_MSG_SwitchNextHigherInfState … #define PPSMC_MSG_MclkRetrainingTest … #define PPSMC_MSG_ForceTDPClamping … #define PPSMC_MSG_CollectCAC_PowerCorreln … #define PPSMC_MSG_CollectCAC_WeightCalib … #define PPSMC_MSG_CollectCAC_SQonly … #define PPSMC_MSG_CollectCAC_TemperaturePwr … #define PPSMC_MSG_ExtremitiesTest_Start … #define PPSMC_MSG_ExtremitiesTest_Stop … #define PPSMC_FlushDataCache … #define PPSMC_FlushInstrCache … #define PPSMC_MSG_SetEnabledLevels … #define PPSMC_MSG_SetForcedLevels … #define PPSMC_MSG_ResetToDefaults … #define PPSMC_MSG_SetForcedLevelsAndJump … #define PPSMC_MSG_SetCACHistoryMode … #define PPSMC_MSG_EnableDTE … #define PPSMC_MSG_DisableDTE … #define PPSMC_MSG_SmcSpaceSetAddress … #define PPSMC_MSG_BREAK … /* Trinity Specific Messages*/ #define PPSMC_MSG_Test … #define PPSMC_MSG_DPM_Voltage_Pwrmgt … #define PPSMC_MSG_DPM_Config … #define PPSMC_MSG_PM_Controller_Start … #define PPSMC_MSG_DPM_ForceState … #define PPSMC_MSG_PG_PowerDownSIMD … #define PPSMC_MSG_PG_PowerUpSIMD … #define PPSMC_MSG_PM_Controller_Stop … #define PPSMC_MSG_PG_SIMD_Config … #define PPSMC_MSG_Voltage_Cntl_Enable … #define PPSMC_MSG_Thermal_Cntl_Enable … #define PPSMC_MSG_Reset_Service … #define PPSMC_MSG_VCEPowerOFF … #define PPSMC_MSG_VCEPowerON … #define PPSMC_MSG_DPM_Disable_VCE_HS … #define PPSMC_MSG_DPM_Enable_VCE_HS … #define PPSMC_MSG_DPM_N_LevelsDisabled … #define PPSMC_MSG_DCEPowerOFF … #define PPSMC_MSG_DCEPowerON … #define PPSMC_MSG_PCIE_DDIPowerDown … #define PPSMC_MSG_PCIE_DDIPowerUp … #define PPSMC_MSG_PCIE_CascadePLLPowerDown … #define PPSMC_MSG_PCIE_CascadePLLPowerUp … #define PPSMC_MSG_SYSPLLPowerOff … #define PPSMC_MSG_SYSPLLPowerOn … #define PPSMC_MSG_DCE_RemoveVoltageAdjustment … #define PPSMC_MSG_DCE_AllowVoltageAdjustment … #define PPSMC_MSG_DISPLAYPHYStatusNotify … #define PPSMC_MSG_EnableBAPM … #define PPSMC_MSG_DisableBAPM … #define PPSMC_MSG_Spmi_Enable … #define PPSMC_MSG_Spmi_Timer … #define PPSMC_MSG_LCLK_DPM_Config … #define PPSMC_MSG_VddNB_Request … #define PPSMC_MSG_PCIE_DDIPhyPowerDown … #define PPSMC_MSG_PCIE_DDIPhyPowerUp … #define PPSMC_MSG_MCLKDPM_Config … #define PPSMC_MSG_UVDDPM_Config … #define PPSMC_MSG_VCEDPM_Config … #define PPSMC_MSG_ACPDPM_Config … #define PPSMC_MSG_SAMUDPM_Config … #define PPSMC_MSG_UVDDPM_SetEnabledMask … #define PPSMC_MSG_VCEDPM_SetEnabledMask … #define PPSMC_MSG_ACPDPM_SetEnabledMask … #define PPSMC_MSG_SAMUDPM_SetEnabledMask … #define PPSMC_MSG_MCLKDPM_ForceState … #define PPSMC_MSG_MCLKDPM_NoForcedLevel … #define PPSMC_MSG_Thermal_Cntl_Disable … #define PPSMC_MSG_SetTDPLimit … #define PPSMC_MSG_Voltage_Cntl_Disable … #define PPSMC_MSG_PCIeDPM_Enable … #define PPSMC_MSG_ACPPowerOFF … #define PPSMC_MSG_ACPPowerON … #define PPSMC_MSG_SAMPowerOFF … #define PPSMC_MSG_SAMPowerON … #define PPSMC_MSG_SDMAPowerOFF … #define PPSMC_MSG_SDMAPowerON … #define PPSMC_MSG_PCIeDPM_Disable … #define PPSMC_MSG_IOMMUPowerOFF … #define PPSMC_MSG_IOMMUPowerON … #define PPSMC_MSG_NBDPM_Enable … #define PPSMC_MSG_NBDPM_Disable … #define PPSMC_MSG_NBDPM_ForceNominal … #define PPSMC_MSG_NBDPM_ForcePerformance … #define PPSMC_MSG_NBDPM_UnForce … #define PPSMC_MSG_SCLKDPM_SetEnabledMask … #define PPSMC_MSG_MCLKDPM_SetEnabledMask … #define PPSMC_MSG_PCIeDPM_ForceLevel … #define PPSMC_MSG_PCIeDPM_UnForceLevel … #define PPSMC_MSG_EnableACDCGPIOInterrupt … #define PPSMC_MSG_EnableVRHotGPIOInterrupt … #define PPSMC_MSG_SwitchToAC … #define PPSMC_MSG_XDMAPowerOFF … #define PPSMC_MSG_XDMAPowerON … #define PPSMC_MSG_DPM_Enable … #define PPSMC_MSG_DPM_Disable … #define PPSMC_MSG_MCLKDPM_Enable … #define PPSMC_MSG_MCLKDPM_Disable … #define PPSMC_MSG_LCLKDPM_Enable … #define PPSMC_MSG_LCLKDPM_Disable … #define PPSMC_MSG_UVDDPM_Enable … #define PPSMC_MSG_UVDDPM_Disable … #define PPSMC_MSG_SAMUDPM_Enable … #define PPSMC_MSG_SAMUDPM_Disable … #define PPSMC_MSG_ACPDPM_Enable … #define PPSMC_MSG_ACPDPM_Disable … #define PPSMC_MSG_VCEDPM_Enable … #define PPSMC_MSG_VCEDPM_Disable … #define PPSMC_MSG_LCLKDPM_SetEnabledMask … #define PPSMC_MSG_DPM_FPS_Mode … #define PPSMC_MSG_DPM_Activity_Mode … #define PPSMC_MSG_VddC_Request … #define PPSMC_MSG_MCLKDPM_GetEnabledMask … #define PPSMC_MSG_LCLKDPM_GetEnabledMask … #define PPSMC_MSG_SCLKDPM_GetEnabledMask … #define PPSMC_MSG_UVDDPM_GetEnabledMask … #define PPSMC_MSG_SAMUDPM_GetEnabledMask … #define PPSMC_MSG_ACPDPM_GetEnabledMask … #define PPSMC_MSG_VCEDPM_GetEnabledMask … #define PPSMC_MSG_PCIeDPM_SetEnabledMask … #define PPSMC_MSG_PCIeDPM_GetEnabledMask … #define PPSMC_MSG_TDCLimitEnable … #define PPSMC_MSG_TDCLimitDisable … #define PPSMC_MSG_DPM_AutoRotate_Mode … #define PPSMC_MSG_DISPCLK_FROM_FCH … #define PPSMC_MSG_DISPCLK_FROM_DFS … #define PPSMC_MSG_DPREFCLK_FROM_FCH … #define PPSMC_MSG_DPREFCLK_FROM_DFS … #define PPSMC_MSG_PmStatusLogStart … #define PPSMC_MSG_PmStatusLogSample … #define PPSMC_MSG_SCLK_AutoDPM_ON … #define PPSMC_MSG_MCLK_AutoDPM_ON … #define PPSMC_MSG_LCLK_AutoDPM_ON … #define PPSMC_MSG_UVD_AutoDPM_ON … #define PPSMC_MSG_SAMU_AutoDPM_ON … #define PPSMC_MSG_ACP_AutoDPM_ON … #define PPSMC_MSG_VCE_AutoDPM_ON … #define PPSMC_MSG_PCIe_AutoDPM_ON … #define PPSMC_MSG_MASTER_AutoDPM_ON … #define PPSMC_MSG_MASTER_AutoDPM_OFF … #define PPSMC_MSG_DYNAMICDISPPHYPOWER … #define PPSMC_MSG_CAC_COLLECTION_ON … #define PPSMC_MSG_CAC_COLLECTION_OFF … #define PPSMC_MSG_CAC_CORRELATION_ON … #define PPSMC_MSG_CAC_CORRELATION_OFF … #define PPSMC_MSG_PM_STATUS_TO_DRAM_ON … #define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF … #define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT … #define PPSMC_MSG_PkgPwrLimitEnable … #define PPSMC_MSG_PkgPwrLimitDisable … #define PPSMC_MSG_PkgPwrSetLimit … #define PPSMC_MSG_OverDriveSetTargetTdp … #define PPSMC_MSG_SCLKDPM_FreezeLevel … #define PPSMC_MSG_SCLKDPM_UnfreezeLevel … #define PPSMC_MSG_MCLKDPM_FreezeLevel … #define PPSMC_MSG_MCLKDPM_UnfreezeLevel … #define PPSMC_MSG_START_DRAM_LOGGING … #define PPSMC_MSG_STOP_DRAM_LOGGING … #define PPSMC_MSG_MASTER_DeepSleep_ON … #define PPSMC_MSG_MASTER_DeepSleep_OFF … #define PPSMC_MSG_Remove_DC_Clamp … #define PPSMC_MSG_DisableACDCGPIOInterrupt … #define PPSMC_MSG_OverrideVoltageControl_SetVddc … #define PPSMC_MSG_OverrideVoltageControl_SetVddci … #define PPSMC_MSG_SetVidOffset_1 … #define PPSMC_MSG_SetVidOffset_2 … #define PPSMC_MSG_GetVidOffset_1 … #define PPSMC_MSG_GetVidOffset_2 … #define PPSMC_MSG_THERMAL_OVERDRIVE_Enable … #define PPSMC_MSG_THERMAL_OVERDRIVE_Disable … #define PPSMC_MSG_SetTjMax … #define PPSMC_MSG_SetFanPwmMax … #define PPSMC_MSG_WaitForMclkSwitchFinish … #define PPSMC_MSG_ENABLE_THERMAL_DPM … #define PPSMC_MSG_DISABLE_THERMAL_DPM … #define PPSMC_MSG_API_GetSclkFrequency … #define PPSMC_MSG_API_GetMclkFrequency … #define PPSMC_MSG_API_GetSclkBusy … #define PPSMC_MSG_API_GetMclkBusy … #define PPSMC_MSG_API_GetAsicPower … #define PPSMC_MSG_SetFanRpmMax … #define PPSMC_MSG_SetFanSclkTarget … #define PPSMC_MSG_SetFanMinPwm … #define PPSMC_MSG_SetFanTemperatureTarget … #define PPSMC_MSG_BACO_StartMonitor … #define PPSMC_MSG_BACO_Cancel … #define PPSMC_MSG_EnableVddGfx … #define PPSMC_MSG_DisableVddGfx … #define PPSMC_MSG_UcodeAddressLow … #define PPSMC_MSG_UcodeAddressHigh … #define PPSMC_MSG_UcodeLoadStatus … #define PPSMC_MSG_DRV_DRAM_ADDR_HI … #define PPSMC_MSG_DRV_DRAM_ADDR_LO … #define PPSMC_MSG_SMU_DRAM_ADDR_HI … #define PPSMC_MSG_SMU_DRAM_ADDR_LO … #define PPSMC_MSG_LoadUcodes … #define PPSMC_MSG_PowerStateNotify … #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI … #define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO … #define PPSMC_MSG_VBIOS_DRAM_ADDR_HI … #define PPSMC_MSG_VBIOS_DRAM_ADDR_LO … #define PPSMC_MSG_LoadVBios … #define PPSMC_MSG_GetUcodeVersion … #define DMCUSMC_MSG_PSREntry … #define DMCUSMC_MSG_PSRExit … #define PPSMC_MSG_EnableClockGatingFeature … #define PPSMC_MSG_DisableClockGatingFeature … #define PPSMC_MSG_IsDeviceRunning … #define PPSMC_MSG_LoadMetaData … #define PPSMC_MSG_TMON_AutoCaliberate_Enable … #define PPSMC_MSG_TMON_AutoCaliberate_Disable … #define PPSMC_MSG_GetTelemetry1Slope … #define PPSMC_MSG_GetTelemetry1Offset … #define PPSMC_MSG_GetTelemetry2Slope … #define PPSMC_MSG_GetTelemetry2Offset … #define PPSMC_MSG_EnableAvfs … #define PPSMC_MSG_DisableAvfs … #define PPSMC_MSG_PerformBtc … #define PPSMC_MSG_GetHbmCode … #define PPSMC_MSG_GetVrVddcTemperature … #define PPSMC_MSG_GetVrMvddTemperature … #define PPSMC_MSG_GetLiquidTemperature … #define PPSMC_MSG_GetPlxTemperature … #define PPSMC_MSG_RequestI2CControl … #define PPSMC_MSG_ReleaseI2CControl … #define PPSMC_MSG_LedConfig … #define PPSMC_MSG_SetHbmFanCode … #define PPSMC_MSG_SetHbmThrottleCode … #define PPSMC_MSG_GetEnabledPsm … #define PPSMC_MSG_AgmStartPsm … #define PPSMC_MSG_AgmReadPsm … #define PPSMC_MSG_AgmResetPsm … #define PPSMC_MSG_ReadVftCell … /* AVFS Only - Remove Later */ #define PPSMC_MSG_VftTableIsValid … /* If the SMC firmware has an event status soft register this is what the individual bits mean.*/ #define PPSMC_EVENT_STATUS_THERMAL … #define PPSMC_EVENT_STATUS_REGULATORHOT … #define PPSMC_EVENT_STATUS_DC … PPSMC_Msg; #pragma pack(pop) #endif
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