/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "pp_debug.h" #include "smumgr.h" #include "smu7_dyn_defaults.h" #include "smu73.h" #include "smu_ucode_xfer_vi.h" #include "fiji_smumgr.h" #include "fiji_ppsmc.h" #include "smu73_discrete.h" #include "ppatomctrl.h" #include "smu/smu_7_1_3_d.h" #include "smu/smu_7_1_3_sh_mask.h" #include "gmc/gmc_8_1_d.h" #include "gmc/gmc_8_1_sh_mask.h" #include "oss/oss_3_0_d.h" #include "gca/gfx_8_0_d.h" #include "bif/bif_5_0_d.h" #include "bif/bif_5_0_sh_mask.h" #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" #include "hardwaremanager.h" #include "cgs_common.h" #include "atombios.h" #include "pppcielanes.h" #include "hwmgr.h" #include "smu7_hwmgr.h" #define AVFS_EN_MSB … #define AVFS_EN_LSB … #define FIJI_SMC_SIZE … #define POWERTUNE_DEFAULT_SET_MAX … #define VDDC_VDDCI_DELTA … #define MC_CG_ARB_FREQ_F1 … /* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs * not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */ static const uint16_t fiji_clock_stretcher_lookup_table[2][4] = …; /* [FF, SS] type, [] 4 voltage ranges, and * [Floor Freq, Boundary Freq, VID min , VID max] */ static const uint32_t fiji_clock_stretcher_ddt_table[2][4][4] = …; /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] * (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ static const uint8_t fiji_clock_stretch_amount_conversion[2][6] = …; static const struct fiji_pt_defaults fiji_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = …; static const struct SMU73_Discrete_GraphicsLevel avfs_graphics_level[8] = …; static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr) { … } static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr) { … } static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr) { … } static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr) { … } static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr) { … } static int fiji_start_smu(struct pp_hwmgr *hwmgr) { … } static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr) { … } static int fiji_smu_init(struct pp_hwmgr *hwmgr) { … } static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, uint32_t clock, uint32_t *voltage, uint32_t *mvdd) { … } static uint16_t scale_fan_gain_settings(uint16_t raw_setting) { … } static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda) { … } static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) { … } static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_Ulv *state) { … } static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_DpmTable *table) { … } static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk) { … } static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level) { … } static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) { … } /* * MCLK Frequency Ratio * SEQ_CG_RESP Bit[31:24] - 0x0 * Bit[27:24] \96 DDR3 Frequency ratio * 0x0 <= 100MHz, 450 < 0x8 <= 500MHz * 100 < 0x1 <= 150MHz, 500 < 0x9 <= 550MHz * 150 < 0x2 <= 200MHz, 550 < 0xA <= 600MHz * 200 < 0x3 <= 250MHz, 600 < 0xB <= 650MHz * 250 < 0x4 <= 300MHz, 650 < 0xC <= 700MHz * 300 < 0x5 <= 350MHz, 700 < 0xD <= 750MHz * 350 < 0x6 <= 400MHz, 750 < 0xE <= 800MHz * 400 < 0x7 <= 450MHz, 800 < 0xF */ static uint8_t fiji_get_mclk_frequency_ratio(uint32_t mem_clock) { … } static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk) { … } static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level) { … } static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pat) { … } static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr, SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr, SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, int32_t eng_clock, int32_t mem_clock, struct SMU73_Discrete_MCArbDramTimingTableEntry *arb_regs) { … } static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_DpmTable *table) { … } static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) { … } static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr, struct SMU73_Discrete_DpmTable *table) { … } static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr) { … } static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr) { … } static int fiji_init_smc_table(struct pp_hwmgr *hwmgr) { … } static int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) { … } static int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr) { … } static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) { … } static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) { … } static uint32_t fiji_get_offsetof(uint32_t type, uint32_t member) { … } static uint32_t fiji_get_mac_definition(uint32_t value) { … } static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr) { … } static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr) { … } static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) { … } static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr) { … } static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) { … } static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr) { … } static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting) { … } const struct pp_smumgr_func fiji_smu_funcs = …;
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