linux/drivers/gpu/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
// CZ Ucode Loading Definitions
#ifndef SMU_UCODE_XFER_CZ_H
#define SMU_UCODE_XFER_CZ_H

#define NUM_JOBLIST_ENTRIES

#define TASK_TYPE_NO_ACTION
#define TASK_TYPE_UCODE_LOAD
#define TASK_TYPE_UCODE_SAVE
#define TASK_TYPE_REG_LOAD
#define TASK_TYPE_REG_SAVE
#define TASK_TYPE_INITIALIZE

#define TASK_ARG_REG_SMCIND
#define TASK_ARG_REG_MMIO
#define TASK_ARG_REG_FCH
#define TASK_ARG_REG_UNB

#define TASK_ARG_INIT_MM_PWR_LOG
#define TASK_ARG_INIT_CLK_TABLE

#define JOB_GFX_SAVE
#define JOB_GFX_RESTORE
#define JOB_FCH_SAVE
#define JOB_FCH_RESTORE
#define JOB_UNB_SAVE
#define JOB_UNB_RESTORE
#define JOB_GMC_SAVE
#define JOB_GMC_RESTORE
#define JOB_GNB_SAVE
#define JOB_GNB_RESTORE

#define IGNORE_JOB
#define END_OF_TASK_LIST

// Size of DRAM regions (in bytes) requested by SMU:
#define SMU_DRAM_REQ_MM_PWR_LOG 

#define UCODE_ID_SDMA0
#define UCODE_ID_SDMA1
#define UCODE_ID_CP_CE
#define UCODE_ID_CP_PFP
#define UCODE_ID_CP_ME
#define UCODE_ID_CP_MEC_JT1
#define UCODE_ID_CP_MEC_JT2
#define UCODE_ID_GMCON_RENG
#define UCODE_ID_RLC_G
#define UCODE_ID_RLC_SCRATCH
#define UCODE_ID_RLC_SRM_ARAM
#define UCODE_ID_RLC_SRM_DRAM
#define UCODE_ID_DMCU_ERAM
#define UCODE_ID_DMCU_IRAM

#define UCODE_ID_SDMA0_MASK       
#define UCODE_ID_SDMA1_MASK        
#define UCODE_ID_CP_CE_MASK      
#define UCODE_ID_CP_PFP_MASK         
#define UCODE_ID_CP_ME_MASK          
#define UCODE_ID_CP_MEC_JT1_MASK             
#define UCODE_ID_CP_MEC_JT2_MASK          
#define UCODE_ID_GMCON_RENG_MASK            
#define UCODE_ID_RLC_G_MASK           
#define UCODE_ID_RLC_SCRATCH_MASK         
#define UCODE_ID_RLC_SRM_ARAM_MASK                
#define UCODE_ID_RLC_SRM_DRAM_MASK                 
#define UCODE_ID_DMCU_ERAM_MASK             
#define UCODE_ID_DMCU_IRAM_MASK              

#define UCODE_ID_SDMA0_SIZE_BYTE        
#define UCODE_ID_SDMA1_SIZE_BYTE          
#define UCODE_ID_CP_CE_SIZE_BYTE        
#define UCODE_ID_CP_PFP_SIZE_BYTE           
#define UCODE_ID_CP_ME_SIZE_BYTE            
#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE               
#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE            
#define UCODE_ID_GMCON_RENG_SIZE_BYTE              
#define UCODE_ID_RLC_G_SIZE_BYTE             
#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE           
#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE                  
#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE                   
#define UCODE_ID_DMCU_ERAM_SIZE_BYTE               
#define UCODE_ID_DMCU_IRAM_SIZE_BYTE                 

#define NUM_UCODES

data_64_t;

struct SMU_Task {};
SMU_Task;

struct TOC {};

// META DATA COMMAND Definitions
#define METADATA_CMD_MODE0 
#define METADATA_CMD_MODE1 
#define METADATA_CMD_MODE2 
#define METADATA_CMD_MODE3
#define METADATA_CMD_DELAY
#define METADATA_CMD_CHNG_REGSPACE
#define METADATA_PERFORM_ON_SAVE
#define METADATA_PERFORM_ON_LOAD
#define METADATA_CMD_ARG_MASK
#define METADATA_CMD_ARG_SHIFT

// Simple register addr/data fields
struct SMU_MetaData_Mode0 {};
SMU_MetaData_Mode0;

// Register addr/data with mask
struct SMU_MetaData_Mode1 {};
SMU_MetaData_Mode1;

struct SMU_MetaData_Mode2 {};
SMU_MetaData_Mode2;

// Always write data (even on a save operation)
struct SMU_MetaData_Mode3 {};
SMU_MetaData_Mode3;

#endif