/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef SMU75_H #define SMU75_H #pragma pack(push, 1) data_64_t; data_128_t; #define SMU__DGPU_ONLY #define SMU__NUM_SCLK_DPM_STATE … #define SMU__NUM_MCLK_DPM_LEVELS … #define SMU__NUM_LCLK_DPM_LEVELS … #define SMU__NUM_PCIE_DPM_LEVELS … #define SMU7_CONTEXT_ID_SMC … #define SMU7_CONTEXT_ID_VBIOS … #define SMU75_MAX_LEVELS_VDDC … #define SMU75_MAX_LEVELS_VDDGFX … #define SMU75_MAX_LEVELS_VDDCI … #define SMU75_MAX_LEVELS_MVDD … #define SMU_MAX_SMIO_LEVELS … #define SMU75_MAX_LEVELS_GRAPHICS … #define SMU75_MAX_LEVELS_MEMORY … #define SMU75_MAX_LEVELS_GIO … #define SMU75_MAX_LEVELS_LINK … #define SMU75_MAX_LEVELS_UVD … #define SMU75_MAX_LEVELS_VCE … #define SMU75_MAX_LEVELS_ACP … #define SMU75_MAX_LEVELS_SAMU … #define SMU75_MAX_ENTRIES_SMIO … #define DPM_NO_LIMIT … #define DPM_NO_UP … #define DPM_GO_DOWN … #define DPM_GO_UP … #define SMU7_FIRST_DPM_GRAPHICS_LEVEL … #define SMU7_FIRST_DPM_MEMORY_LEVEL … #define GPIO_CLAMP_MODE_VRHOT … #define GPIO_CLAMP_MODE_THERM … #define GPIO_CLAMP_MODE_DC … #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT … #define SCRATCH_B_TARG_PCIE_INDEX_MASK … #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT … #define SCRATCH_B_CURR_PCIE_INDEX_MASK … #define SCRATCH_B_TARG_UVD_INDEX_SHIFT … #define SCRATCH_B_TARG_UVD_INDEX_MASK … #define SCRATCH_B_CURR_UVD_INDEX_SHIFT … #define SCRATCH_B_CURR_UVD_INDEX_MASK … #define SCRATCH_B_TARG_VCE_INDEX_SHIFT … #define SCRATCH_B_TARG_VCE_INDEX_MASK … #define SCRATCH_B_CURR_VCE_INDEX_SHIFT … #define SCRATCH_B_CURR_VCE_INDEX_MASK … #define SCRATCH_B_TARG_ACP_INDEX_SHIFT … #define SCRATCH_B_TARG_ACP_INDEX_MASK … #define SCRATCH_B_CURR_ACP_INDEX_SHIFT … #define SCRATCH_B_CURR_ACP_INDEX_MASK … #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT … #define SCRATCH_B_TARG_SAMU_INDEX_MASK … #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT … #define SCRATCH_B_CURR_SAMU_INDEX_MASK … /* Virtualization Defines */ #define CG_XDMA_MASK … #define CG_XDMA_SHIFT … #define CG_UVD_MASK … #define CG_UVD_SHIFT … #define CG_VCE_MASK … #define CG_VCE_SHIFT … #define CG_SAMU_MASK … #define CG_SAMU_SHIFT … #define CG_GFX_MASK … #define CG_GFX_SHIFT … #define CG_SDMA_MASK … #define CG_SDMA_SHIFT … #define CG_HDP_MASK … #define CG_HDP_SHIFT … #define CG_MC_MASK … #define CG_MC_SHIFT … #define CG_DRM_MASK … #define CG_DRM_SHIFT … #define CG_ROM_MASK … #define CG_ROM_SHIFT … #define CG_BIF_MASK … #define CG_BIF_SHIFT … #if defined SMU__DGPU_ONLY #define SMU75_DTE_ITERATIONS … #define SMU75_DTE_SOURCES … #define SMU75_DTE_SINKS … #define SMU75_NUM_CPU_TES … #define SMU75_NUM_GPU_TES … #define SMU75_NUM_NON_TES … #define SMU75_DTE_FAN_SCALAR_MIN … #define SMU75_DTE_FAN_SCALAR_MAX … #define SMU75_DTE_FAN_TEMP_MAX … #define SMU75_DTE_FAN_TEMP_MIN … #endif #define SMU75_THERMAL_INPUT_LOOP_COUNT … #define SMU75_THERMAL_CLAMP_MODE_COUNT … #define EXP_M1_1 … #define EXP_M2_1 … #define EXP_B_1 … #define EXP_M1_2 … #define EXP_M2_2 … #define EXP_B_2 … #define EXP_M1_3 … #define EXP_M2_3 … #define EXP_B_3 … #define EXP_M1_4 … #define EXP_M2_4 … #define EXP_B_4 … #define EXP_M1_5 … #define EXP_M2_5 … #define EXP_B_5 … struct SMU7_HystController_Data { … }; SMU7_HystController_Data; struct SMU75_PIDController { … }; SMU75_PIDController; struct SMU7_LocalDpmScoreboard { … }; SMU7_LocalDpmScoreboard; #define SMU7_MAX_VOLTAGE_CLIENTS … VoltageChangeHandler_t; #define VDDC_MASK … #define VDDC_SHIFT … #define VDDCI_MASK … #define VDDCI_SHIFT … #define PHASES_MASK … #define PHASES_SHIFT … SMU_VoltageLevel; struct SMU7_VoltageScoreboard { … }; SMU7_VoltageScoreboard; #define SMU7_MAX_PCIE_LINK_SPEEDS … struct SMU7_PCIeLinkSpeedScoreboard { … }; SMU7_PCIeLinkSpeedScoreboard; #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES … #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES … #define SMU7_SCALE_I … #define SMU7_SCALE_R … struct SMU7_PowerScoreboard { … }; SMU7_PowerScoreboard; #define SMU7_SCLK_DPM_CONFIG_MASK … #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK … #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK … #define SMU7_MCLK_DPM_CONFIG_MASK … #define SMU7_UVD_DPM_CONFIG_MASK … #define SMU7_VCE_DPM_CONFIG_MASK … #define SMU7_ACP_DPM_CONFIG_MASK … #define SMU7_SAMU_DPM_CONFIG_MASK … #define SMU7_PCIEGEN_DPM_CONFIG_MASK … #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE … #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE … #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE … #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE … #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE … #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE … struct SMU75_SoftRegisters { … }; SMU75_SoftRegisters; struct SMU75_Firmware_Header { … }; SMU75_Firmware_Header; #define SMU7_FIRMWARE_HEADER_LOCATION … enum DisplayConfig { … }; #define MC_BLOCK_COUNT … #define CPL_BLOCK_COUNT … #define SE_BLOCK_COUNT … #define GC_BLOCK_COUNT … struct SMU7_Local_Cac { … }; SMU7_Local_Cac; struct SMU7_Local_Cac_Table { … }; SMU7_Local_Cac_Table; #pragma pack(pop) #define CG_SYS_BITMASK_FIRST_BIT … #define CG_SYS_BITMASK_LAST_BIT … #define CG_SYS_BIF_MGLS_SHIFT … #define CG_SYS_ROM_SHIFT … #define CG_SYS_MC_MGCG_SHIFT … #define CG_SYS_MC_MGLS_SHIFT … #define CG_SYS_SDMA_MGCG_SHIFT … #define CG_SYS_SDMA_MGLS_SHIFT … #define CG_SYS_DRM_MGCG_SHIFT … #define CG_SYS_HDP_MGCG_SHIFT … #define CG_SYS_HDP_MGLS_SHIFT … #define CG_SYS_DRM_MGLS_SHIFT … #define CG_SYS_BIF_MGCG_SHIFT … #define CG_SYS_BIF_MGLS_MASK … #define CG_SYS_ROM_MASK … #define CG_SYS_MC_MGCG_MASK … #define CG_SYS_MC_MGLS_MASK … #define CG_SYS_SDMA_MGCG_MASK … #define CG_SYS_SDMA_MGLS_MASK … #define CG_SYS_DRM_MGCG_MASK … #define CG_SYS_HDP_MGCG_MASK … #define CG_SYS_HDP_MGLS_MASK … #define CG_SYS_DRM_MGLS_MASK … #define CG_SYS_BIF_MGCG_MASK … #define CG_GFX_BITMASK_FIRST_BIT … #define CG_GFX_BITMASK_LAST_BIT … #define CG_GFX_CGCG_SHIFT … #define CG_GFX_CGLS_SHIFT … #define CG_CPF_MGCG_SHIFT … #define CG_RLC_MGCG_SHIFT … #define CG_GFX_OTHERS_MGCG_SHIFT … #define CG_GFX_3DCG_SHIFT … #define CG_GFX_3DLS_SHIFT … #define CG_GFX_RLC_LS_SHIFT … #define CG_GFX_CP_LS_SHIFT … #define CG_GFX_CGCG_MASK … #define CG_GFX_CGLS_MASK … #define CG_CPF_MGCG_MASK … #define CG_RLC_MGCG_MASK … #define CG_GFX_OTHERS_MGCG_MASK … #define CG_GFX_3DCG_MASK … #define CG_GFX_3DLS_MASK … #define CG_GFX_RLC_LS_MASK … #define CG_GFX_CP_LS_MASK … #define VRCONF_VDDC_MASK … #define VRCONF_VDDC_SHIFT … #define VRCONF_VDDGFX_MASK … #define VRCONF_VDDGFX_SHIFT … #define VRCONF_VDDCI_MASK … #define VRCONF_VDDCI_SHIFT … #define VRCONF_MVDD_MASK … #define VRCONF_MVDD_SHIFT … #define VR_MERGED_WITH_VDDC … #define VR_SVI2_PLANE_1 … #define VR_SVI2_PLANE_2 … #define VR_SMIO_PATTERN_1 … #define VR_SMIO_PATTERN_2 … #define VR_STATIC_VOLTAGE … #define CLOCK_STRETCHER_MAX_ENTRIES … #define CKS_LOOKUPTable_MAX_ENTRIES … #define CLOCK_STRETCHER_SETTING_DDT_MASK … #define CLOCK_STRETCHER_SETTING_DDT_SHIFT … #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK … #define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT … #define CLOCK_STRETCHER_SETTING_ENABLE_MASK … #define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT … struct SMU_ClockStretcherDataTableEntry { … }; SMU_ClockStretcherDataTableEntry; struct SMU_ClockStretcherDataTable { … }; SMU_ClockStretcherDataTable; struct SMU_CKS_LOOKUPTableEntry { … }; SMU_CKS_LOOKUPTableEntry; struct SMU_CKS_LOOKUPTable { … }; SMU_CKS_LOOKUPTable; struct AgmAvfsData_t { … }; AgmAvfsData_t; enum VFT_COLUMNS { … }; enum { … }; enum { … }; #define VFT_TABLE_DEFINED #define TEMP_RANGE_MAXSTEPS … struct VFT_CELL_t { … }; VFT_CELL_t; #ifdef SMU__FIRMWARE_SCKS_PRESENT__1 struct SCS_CELL_t { uint16_t PsmCnt[NUM_SCKS_STATE_TYPES]; }; typedef struct SCS_CELL_t SCS_CELL_t; #endif struct VFT_TABLE_t { … }; VFT_TABLE_t; #define BTCGB_VDROOP_TABLE_MAX_ENTRIES … #define AVFSGB_VDROOP_TABLE_MAX_ENTRIES … struct GB_VDROOP_TABLE_t { … }; GB_VDROOP_TABLE_t; struct SMU_QuadraticCoeffs { … }; SMU_QuadraticCoeffs; struct AVFS_Margin_t { … }; AVFS_Margin_t; struct AVFS_CksOff_Gbv_t { … }; AVFS_CksOff_Gbv_t; struct AVFS_CksOff_AvfsGbv_t { … }; AVFS_CksOff_AvfsGbv_t; struct AVFS_CksOff_BtcGbv_t { … }; AVFS_CksOff_BtcGbv_t; struct AVFS_meanNsigma_t { … }; AVFS_meanNsigma_t; struct AVFS_Sclk_Offset_t { … }; AVFS_Sclk_Offset_t; struct Power_Sharing_t { … }; Power_Sharing_t; #endif
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