/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef SMU75_DISCRETE_H #define SMU75_DISCRETE_H #include "smu75.h" #pragma pack(push, 1) #define NUM_SCLK_RANGE … #define VCO_3_6 … #define VCO_2_4 … #define POSTDIV_DIV_BY_1 … #define POSTDIV_DIV_BY_2 … #define POSTDIV_DIV_BY_4 … #define POSTDIV_DIV_BY_8 … #define POSTDIV_DIV_BY_16 … struct sclkFcwRange_t { … }; sclkFcwRange_t; struct SMIO_Pattern { … }; SMIO_Pattern; struct SMIO_Table { … }; SMIO_Table; struct SMU_SclkSetting { … }; SMU_SclkSetting; struct SMU75_Discrete_GraphicsLevel { … }; SMU75_Discrete_GraphicsLevel; struct SMU75_Discrete_ACPILevel { … }; SMU75_Discrete_ACPILevel; struct SMU75_Discrete_Ulv { … }; SMU75_Discrete_Ulv; struct SMU75_Discrete_MemoryLevel { … }; SMU75_Discrete_MemoryLevel; struct SMU75_Discrete_LinkLevel { … }; SMU75_Discrete_LinkLevel; /* MC ARB DRAM Timing registers. */ struct SMU75_Discrete_MCArbDramTimingTableEntry { … }; SMU75_Discrete_MCArbDramTimingTableEntry; struct SMU75_Discrete_MCArbDramTimingTable { … }; SMU75_Discrete_MCArbDramTimingTable; /* UVD VCLK/DCLK state (level) definition. */ struct SMU75_Discrete_UvdLevel { … }; SMU75_Discrete_UvdLevel; /* Clocks for other external blocks (VCE, ACP, SAMU). */ struct SMU75_Discrete_ExtClkLevel { … }; SMU75_Discrete_ExtClkLevel; struct SMU75_Discrete_StateInfo { … }; SMU75_Discrete_StateInfo; struct SMU75_Discrete_DpmTable { … }; SMU75_Discrete_DpmTable; struct SMU75_Discrete_FanTable { … }; SMU75_Discrete_FanTable; #define SMU7_DISCRETE_GPIO_SCLK_DEBUG … #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT … struct SMU7_MclkDpmScoreboard { … }; SMU7_MclkDpmScoreboard; struct SMU7_UlvScoreboard { … }; SMU7_UlvScoreboard; struct VddgfxSavedRegisters { … }; VddgfxSavedRegisters; struct SMU7_VddGfxScoreboard { … }; SMU7_VddGfxScoreboard; struct SMU7_TdcLimitScoreboard { … }; SMU7_TdcLimitScoreboard; struct SMU7_PkgPwrLimitScoreboard { … }; SMU7_PkgPwrLimitScoreboard; struct SMU7_BapmScoreboard { … }; SMU7_BapmScoreboard; struct SMU7_AcpiScoreboard { … }; SMU7_AcpiScoreboard; struct SMU75_Discrete_PmFuses { … }; SMU75_Discrete_PmFuses; struct SMU7_Discrete_Log_Header_Table { … }; SMU7_Discrete_Log_Header_Table; struct SMU7_Discrete_Log_Cntl { … }; SMU7_Discrete_Log_Cntl; #if defined SMU__DGPU_ONLY #define CAC_ACC_NW_NUM_OF_SIGNALS … #endif struct SMU7_Discrete_Cac_Collection_Table { … }; SMU7_Discrete_Cac_Collection_Table; struct SMU7_Discrete_Cac_Verification_Table { … }; SMU7_Discrete_Cac_Verification_Table; struct SMU7_Discrete_Pm_Status_Table { … }; SMU7_Discrete_Pm_Status_Table; struct SMU7_Discrete_AutoWattMan_Status_Table { … }; SMU7_Discrete_AutoWattMan_Status_Table; #define SMU7_MAX_GFX_CU_COUNT … #define SMU7_MIN_GFX_CU_COUNT … #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_SHIFT … #define SMU7_GFX_CU_PG_ENABLE_DC_MAX_CU_MASK … #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_SHIFT … #define SMU7_GFX_CU_PG_ENABLE_AC_MAX_CU_MASK … struct SMU7_GfxCuPgScoreboard { … }; SMU7_GfxCuPgScoreboard; #define SMU7_SCLK_CAC … #define SMU7_MCLK_CAC … #define SMU7_VCLK_CAC … #define SMU7_DCLK_CAC … #define SMU7_ECLK_CAC … #define SMU7_ACLK_CAC … #define SMU7_SAMCLK_CAC … #define SMU7_DISPCLK_CAC … #define SMU7_CAC_CONSTANT … #define SMU7_CAC_CONSTANT_SHIFT … #define SMU7_VDDCI_MCLK_CONST … #define SMU7_VDDCI_MCLK_CONST_SHIFT … #define SMU7_VDDCI_VDDCI_CONST … #define SMU7_VDDCI_VDDCI_CONST_SHIFT … #define SMU7_VDDCI_CONST … #define SMU7_VDDCI_STROBE_PWR … #define SMU7_VDDR1_CONST … #define SMU7_VDDR1_CAC_WEIGHT … #define SMU7_VDDR1_CAC_WEIGHT_SHIFT … #define SMU7_VDDR1_STROBE_PWR … #define SMU7_AREA_COEFF_UVD … #define SMU7_AREA_COEFF_VCE … #define SMU7_AREA_COEFF_ACP … #define SMU7_AREA_COEFF_SAMU … #define SMU7_THERM_OUT_MODE_DISABLE … #define SMU7_THERM_OUT_MODE_THERM_ONLY … #define SMU7_THERM_OUT_MODE_THERM_VRHOT … #define SQ_Enable_MASK … #define SQ_IR_MASK … #define SQ_PCC_MASK … #define SQ_EDC_MASK … #define TCP_Enable_MASK … #define TCP_IR_MASK … #define TCP_PCC_MASK … #define TCP_EDC_MASK … #define TD_Enable_MASK … #define TD_IR_MASK … #define TD_PCC_MASK … #define TD_EDC_MASK … #define DB_Enable_MASK … #define DB_IR_MASK … #define DB_PCC_MASK … #define DB_EDC_MASK … #define SQ_Enable_SHIFT … #define SQ_IR_SHIFT … #define SQ_PCC_SHIFT … #define SQ_EDC_SHIFT … #define TCP_Enable_SHIFT … #define TCP_IR_SHIFT … #define TCP_PCC_SHIFT … #define TCP_EDC_SHIFT … #define TD_Enable_SHIFT … #define TD_IR_SHIFT … #define TD_PCC_SHIFT … #define TD_EDC_SHIFT … #define DB_Enable_SHIFT … #define DB_IR_SHIFT … #define DB_PCC_SHIFT … #define DB_EDC_SHIFT … #define PMFUSES_AVFSSIZE … #define BTCGB0_Vdroop_Enable_MASK … #define BTCGB1_Vdroop_Enable_MASK … #define AVFSGB0_Vdroop_Enable_MASK … #define AVFSGB1_Vdroop_Enable_MASK … #define BTCGB0_Vdroop_Enable_SHIFT … #define BTCGB1_Vdroop_Enable_SHIFT … #define AVFSGB0_Vdroop_Enable_SHIFT … #define AVFSGB1_Vdroop_Enable_SHIFT … #pragma pack(pop) #endif
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