linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h

/*
 * Copyright 2017 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef VEGA12_SMU9_DRIVER_IF_H
#define VEGA12_SMU9_DRIVER_IF_H

/**** IMPORTANT ***
 * SMU TEAM: Always increment the interface version if
 * any structure is changed in this file
 */
#define SMU9_DRIVER_IF_VERSION

#define PPTABLE_V12_SMU_VERSION

#define NUM_GFXCLK_DPM_LEVELS
#define NUM_VCLK_DPM_LEVELS
#define NUM_DCLK_DPM_LEVELS
#define NUM_ECLK_DPM_LEVELS
#define NUM_MP0CLK_DPM_LEVELS
#define NUM_UCLK_DPM_LEVELS
#define NUM_SOCCLK_DPM_LEVELS
#define NUM_DCEFCLK_DPM_LEVELS
#define NUM_DISPCLK_DPM_LEVELS
#define NUM_PIXCLK_DPM_LEVELS
#define NUM_PHYCLK_DPM_LEVELS
#define NUM_LINK_LEVELS

#define MAX_GFXCLK_DPM_LEVEL
#define MAX_VCLK_DPM_LEVEL
#define MAX_DCLK_DPM_LEVEL
#define MAX_ECLK_DPM_LEVEL
#define MAX_MP0CLK_DPM_LEVEL
#define MAX_UCLK_DPM_LEVEL
#define MAX_SOCCLK_DPM_LEVEL
#define MAX_DCEFCLK_DPM_LEVEL
#define MAX_DISPCLK_DPM_LEVEL
#define MAX_PIXCLK_DPM_LEVEL
#define MAX_PHYCLK_DPM_LEVEL
#define MAX_LINK_LEVEL


#define PPSMC_GeminiModeNone
#define PPSMC_GeminiModeMaster
#define PPSMC_GeminiModeSlave


#define FEATURE_DPM_PREFETCHER_BIT
#define FEATURE_DPM_GFXCLK_BIT
#define FEATURE_DPM_UCLK_BIT
#define FEATURE_DPM_SOCCLK_BIT
#define FEATURE_DPM_UVD_BIT
#define FEATURE_DPM_VCE_BIT
#define FEATURE_ULV_BIT
#define FEATURE_DPM_MP0CLK_BIT
#define FEATURE_DPM_LINK_BIT
#define FEATURE_DPM_DCEFCLK_BIT
#define FEATURE_DS_GFXCLK_BIT
#define FEATURE_DS_SOCCLK_BIT
#define FEATURE_DS_LCLK_BIT
#define FEATURE_PPT_BIT
#define FEATURE_TDC_BIT
#define FEATURE_THERMAL_BIT
#define FEATURE_GFX_PER_CU_CG_BIT
#define FEATURE_RM_BIT
#define FEATURE_DS_DCEFCLK_BIT
#define FEATURE_ACDC_BIT
#define FEATURE_VR0HOT_BIT
#define FEATURE_VR1HOT_BIT
#define FEATURE_FW_CTF_BIT
#define FEATURE_LED_DISPLAY_BIT
#define FEATURE_FAN_CONTROL_BIT
#define FEATURE_GFX_EDC_BIT
#define FEATURE_GFXOFF_BIT
#define FEATURE_CG_BIT
#define FEATURE_ACG_BIT
#define FEATURE_SPARE_29_BIT
#define FEATURE_SPARE_30_BIT
#define FEATURE_SPARE_31_BIT

#define NUM_FEATURES

#define FEATURE_DPM_PREFETCHER_MASK
#define FEATURE_DPM_GFXCLK_MASK
#define FEATURE_DPM_UCLK_MASK
#define FEATURE_DPM_SOCCLK_MASK
#define FEATURE_DPM_UVD_MASK
#define FEATURE_DPM_VCE_MASK
#define FEATURE_ULV_MASK
#define FEATURE_DPM_MP0CLK_MASK
#define FEATURE_DPM_LINK_MASK
#define FEATURE_DPM_DCEFCLK_MASK
#define FEATURE_DS_GFXCLK_MASK
#define FEATURE_DS_SOCCLK_MASK
#define FEATURE_DS_LCLK_MASK
#define FEATURE_PPT_MASK
#define FEATURE_TDC_MASK
#define FEATURE_THERMAL_MASK
#define FEATURE_GFX_PER_CU_CG_MASK
#define FEATURE_RM_MASK
#define FEATURE_DS_DCEFCLK_MASK
#define FEATURE_ACDC_MASK
#define FEATURE_VR0HOT_MASK
#define FEATURE_VR1HOT_MASK
#define FEATURE_FW_CTF_MASK
#define FEATURE_LED_DISPLAY_MASK
#define FEATURE_FAN_CONTROL_MASK
#define FEATURE_GFX_EDC_MASK
#define FEATURE_GFXOFF_MASK
#define FEATURE_CG_MASK
#define FEATURE_ACG_MASK
#define FEATURE_SPARE_29_MASK
#define FEATURE_SPARE_30_MASK
#define FEATURE_SPARE_31_MASK


#define DPM_OVERRIDE_DISABLE_SOCCLK_PID
#define DPM_OVERRIDE_DISABLE_UCLK_PID
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_SOCCLK
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_UVD_UCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_SOCCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_VCLK_UCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_SOCCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_DCLK_UCLK
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_SOCCLK
#define DPM_OVERRIDE_ENABLE_VOLT_LINK_VCE_UCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_SOCCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_ECLK_UCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_SOCCLK
#define DPM_OVERRIDE_ENABLE_FREQ_LINK_GFXCLK_UCLK
#define DPM_OVERRIDE_ENABLE_GFXOFF_GFXCLK_SWITCH
#define DPM_OVERRIDE_ENABLE_GFXOFF_SOCCLK_SWITCH
#define DPM_OVERRIDE_ENABLE_GFXOFF_UCLK_SWITCH


#define VR_MAPPING_VR_SELECT_MASK
#define VR_MAPPING_VR_SELECT_SHIFT

#define VR_MAPPING_PLANE_SELECT_MASK
#define VR_MAPPING_PLANE_SELECT_SHIFT


#define PSI_SEL_VR0_PLANE0_PSI0
#define PSI_SEL_VR0_PLANE0_PSI1
#define PSI_SEL_VR0_PLANE1_PSI0
#define PSI_SEL_VR0_PLANE1_PSI1
#define PSI_SEL_VR1_PLANE0_PSI0
#define PSI_SEL_VR1_PLANE0_PSI1
#define PSI_SEL_VR1_PLANE1_PSI0
#define PSI_SEL_VR1_PLANE1_PSI1


#define THROTTLER_STATUS_PADDING_BIT
#define THROTTLER_STATUS_TEMP_EDGE_BIT
#define THROTTLER_STATUS_TEMP_HOTSPOT_BIT
#define THROTTLER_STATUS_TEMP_HBM_BIT
#define THROTTLER_STATUS_TEMP_VR_GFX_BIT
#define THROTTLER_STATUS_TEMP_VR_MEM_BIT
#define THROTTLER_STATUS_TEMP_LIQUID_BIT
#define THROTTLER_STATUS_TEMP_PLX_BIT
#define THROTTLER_STATUS_TEMP_SKIN_BIT
#define THROTTLER_STATUS_TDC_GFX_BIT
#define THROTTLER_STATUS_TDC_SOC_BIT
#define THROTTLER_STATUS_PPT_BIT
#define THROTTLER_STATUS_FIT_BIT
#define THROTTLER_STATUS_PPM_BIT


#define TABLE_TRANSFER_OK
#define TABLE_TRANSFER_FAILED


#define WORKLOAD_DEFAULT_BIT
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT
#define WORKLOAD_PPLIB_POWER_SAVING_BIT
#define WORKLOAD_PPLIB_VIDEO_BIT
#define WORKLOAD_PPLIB_VR_BIT
#define WORKLOAD_PPLIB_COMPUTE_BIT
#define WORKLOAD_PPLIB_CUSTOM_BIT
#define WORKLOAD_PPLIB_COUNT

QuadraticInt_t;

LinearInt_t;

DroopInt_t;

PPCLK_e;

enum {};

DpmDescriptor_t;

#pragma pack(push, 1)
PPTable_t;
#pragma pack(pop)

DriverSmuConfig_t;

OverDriveTable_t;

SmuMetrics_t;

WatermarkRowGeneric_t;

#define NUM_WM_RANGES

WM_CLOCK_e;

Watermarks_t;

AvfsDebugTable_t;

AvfsFuseOverride_t;

DpmActivityMonitorCoeffInt_t;




#define TABLE_PPTABLE
#define TABLE_WATERMARKS
#define TABLE_AVFS
#define TABLE_AVFS_PSM_DEBUG
#define TABLE_AVFS_FUSE_OVERRIDE
#define TABLE_PMSTATUSLOG
#define TABLE_SMU_METRICS
#define TABLE_DRIVER_SMU_CONFIG
#define TABLE_ACTIVITY_MONITOR_COEFF
#define TABLE_OVERDRIVE
#define TABLE_COUNT


#define UCLK_SWITCH_SLOW
#define UCLK_SWITCH_FAST


#define SQ_Enable_MASK
#define SQ_IR_MASK
#define SQ_PCC_MASK
#define SQ_EDC_MASK

#define TCP_Enable_MASK
#define TCP_IR_MASK
#define TCP_PCC_MASK
#define TCP_EDC_MASK

#define TD_Enable_MASK
#define TD_IR_MASK
#define TD_PCC_MASK
#define TD_EDC_MASK

#define DB_Enable_MASK
#define DB_IR_MASK
#define DB_PCC_MASK
#define DB_EDC_MASK

#define SQ_Enable_SHIFT
#define SQ_IR_SHIFT
#define SQ_PCC_SHIFT
#define SQ_EDC_SHIFT

#define TCP_Enable_SHIFT
#define TCP_IR_SHIFT
#define TCP_PCC_SHIFT
#define TCP_EDC_SHIFT

#define TD_Enable_SHIFT
#define TD_IR_SHIFT
#define TD_PCC_SHIFT
#define TD_EDC_SHIFT

#define DB_Enable_SHIFT
#define DB_IR_SHIFT
#define DB_PCC_SHIFT
#define DB_EDC_SHIFT

#define REMOVE_FMAX_MARGIN_BIT
#define REMOVE_DCTOL_MARGIN_BIT
#define REMOVE_PLATFORM_MARGIN_BIT

#endif