#ifndef PP_ATOMFWCTRL_H
#define PP_ATOMFWCTRL_H
#include "hwmgr.h"
BIOS_CLKID;
#define GetIndexIntoMasterCmdTable(FieldName) …
#define GetIndexIntoMasterDataTable(FieldName) …
#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES …
struct pp_atomfwctrl_voltage_table_entry { … };
struct pp_atomfwctrl_voltage_table { … };
struct pp_atomfwctrl_gpio_pin_assignment { … };
struct pp_atomfwctrl_clock_dividers_soc15 { … };
struct pp_atomfwctrl_avfs_parameters { … };
struct pp_atomfwctrl_gpio_parameters { … };
struct pp_atomfwctrl_bios_boot_up_values { … };
struct pp_atomfwctrl_smc_dpm_parameters { … };
int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
uint32_t clock_type, uint32_t clock_value,
struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
uint8_t voltage_type, uint8_t voltage_mode);
int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
struct pp_atomfwctrl_avfs_parameters *param);
int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
struct pp_atomfwctrl_gpio_parameters *param);
int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
struct pp_atomfwctrl_bios_boot_up_values *boot_values);
int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
struct pp_atomfwctrl_smc_dpm_parameters *param);
int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
uint8_t clk_id, uint8_t syspll_id,
uint32_t *frequency);
#endif