/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _VEGA12_HWMGR_H_ #define _VEGA12_HWMGR_H_ #include "hwmgr.h" #include "vega12/smu9_driver_if.h" #include "ppatomfwctrl.h" #define VEGA12_MAX_HARDWARE_POWERLEVELS … #define WaterMarksExist … #define WaterMarksLoaded … #define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS … #define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS … #define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS … #define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS … enum { … }; #define GNLD_DPM_MAX … #define SMC_DPM_FEATURES … struct smu_features { … }; struct vega12_dpm_level { … }; #define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID … #define MAX_REGULAR_DPM_NUMBER … #define MAX_PCIE_CONF … #define VEGA12_MINIMUM_ENGINE_CLOCK … struct vega12_dpm_state { … }; struct vega12_single_dpm_table { … }; struct vega12_odn_dpm_control { … }; struct vega12_pcie_table { … }; struct vega12_dpm_table { … }; #define VEGA12_MAX_LEAKAGE_COUNT … struct vega12_leakage_voltage { … }; struct vega12_display_timing { … }; struct vega12_dpmlevel_enable_mask { … }; struct vega12_vbios_boot_state { … }; #define DPMTABLE_OD_UPDATE_SCLK … #define DPMTABLE_OD_UPDATE_MCLK … #define DPMTABLE_UPDATE_SCLK … #define DPMTABLE_UPDATE_MCLK … #define DPMTABLE_OD_UPDATE_VDDC … struct vega12_smc_state_table { … }; struct vega12_mclk_latency_entries { … }; struct vega12_mclk_latency_table { … }; struct vega12_registry_data { … }; struct vega12_odn_clock_voltage_dependency_table { … }; struct vega12_odn_dpm_table { … }; struct vega12_odn_fan_table { … }; struct vega12_clock_range { … }; struct vega12_hwmgr { … }; #define VEGA12_DPM2_NEAR_TDP_DEC … #define VEGA12_DPM2_ABOVE_SAFE_INC … #define VEGA12_DPM2_BELOW_SAFE_INC … #define VEGA12_DPM2_LTA_WINDOW_SIZE … #define VEGA12_DPM2_LTS_TRUNCATE … #define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT … #define VEGA12_DPM2_MAXPS_PERCENT_M … #define VEGA12_DPM2_MAXPS_PERCENT_H … #define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN … #define VEGA12_DPM2_SQ_RAMP_MAX_POWER … #define VEGA12_DPM2_SQ_RAMP_MIN_POWER … #define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA … #define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE … #define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO … #define VEGA12_VOLTAGE_CONTROL_NONE … #define VEGA12_VOLTAGE_CONTROL_BY_GPIO … #define VEGA12_VOLTAGE_CONTROL_BY_SVID2 … #define VEGA12_VOLTAGE_CONTROL_MERGED … /* To convert to Q8.8 format for firmware */ #define VEGA12_Q88_FORMAT_CONVERSION_UNIT … #define VEGA12_UNUSED_GPIO_PIN … #define VEGA12_THERM_OUT_MODE_DISABLE … #define VEGA12_THERM_OUT_MODE_THERM_ONLY … #define VEGA12_THERM_OUT_MODE_THERM_VRHOT … #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT … #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT … #define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT … #define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT … #define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT … #define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT … #define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT … #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT … #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT … #define VEGA12_UMD_PSTATE_GFXCLK_LEVEL … #define VEGA12_UMD_PSTATE_SOCCLK_LEVEL … #define VEGA12_UMD_PSTATE_MCLK_LEVEL … #define VEGA12_UMD_PSTATE_UVDCLK_LEVEL … #define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL … int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); #endif /* _VEGA12_HWMGR_H_ */
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