/* * Copyright 2016 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #ifndef _VEGA10_HWMGR_H_ #define _VEGA10_HWMGR_H_ #include "hwmgr.h" #include "smu9_driver_if.h" #include "ppatomctrl.h" #include "ppatomfwctrl.h" #include "vega10_ppsmc.h" #include "vega10_powertune.h" #define VEGA10_MAX_HARDWARE_POWERLEVELS … #define WaterMarksExist … #define WaterMarksLoaded … enum { … }; #define GNLD_DPM_MAX … #define SMC_DPM_FEATURES … struct smu_features { … }; struct vega10_performance_level { … }; struct vega10_bacos { … }; struct vega10_uvd_clocks { … }; struct vega10_vce_clocks { … }; struct vega10_power_state { … }; struct vega10_dpm_level { … }; #define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID … #define MAX_REGULAR_DPM_NUMBER … #define MAX_PCIE_CONF … #define VEGA10_MINIMUM_ENGINE_CLOCK … struct vega10_dpm_state { … }; struct vega10_single_dpm_table { … }; struct vega10_pcie_table { … }; struct vega10_dpm_table { … }; #define VEGA10_MAX_LEAKAGE_COUNT … struct vega10_leakage_voltage { … }; struct vega10_display_timing { … }; struct vega10_dpmlevel_enable_mask { … }; struct vega10_vbios_boot_state { … }; struct vega10_smc_state_table { … }; struct vega10_mclk_latency_entries { … }; struct vega10_mclk_latency_table { … }; struct vega10_registry_data { … }; struct vega10_odn_clock_voltage_dependency_table { … }; struct vega10_odn_vddc_lookup_table { … }; struct vega10_odn_dpm_table { … }; struct vega10_odn_fan_table { … }; struct vega10_hwmgr { … }; #define VEGA10_DPM2_NEAR_TDP_DEC … #define VEGA10_DPM2_ABOVE_SAFE_INC … #define VEGA10_DPM2_BELOW_SAFE_INC … #define VEGA10_DPM2_LTA_WINDOW_SIZE … #define VEGA10_DPM2_LTS_TRUNCATE … #define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT … #define VEGA10_DPM2_MAXPS_PERCENT_M … #define VEGA10_DPM2_MAXPS_PERCENT_H … #define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN … #define VEGA10_DPM2_SQ_RAMP_MAX_POWER … #define VEGA10_DPM2_SQ_RAMP_MIN_POWER … #define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA … #define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE … #define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO … #define VEGA10_VOLTAGE_CONTROL_NONE … #define VEGA10_VOLTAGE_CONTROL_BY_GPIO … #define VEGA10_VOLTAGE_CONTROL_BY_SVID2 … #define VEGA10_VOLTAGE_CONTROL_MERGED … /* To convert to Q8.8 format for firmware */ #define VEGA10_Q88_FORMAT_CONVERSION_UNIT … #define VEGA10_UNUSED_GPIO_PIN … #define VEGA10_THERM_OUT_MODE_DISABLE … #define VEGA10_THERM_OUT_MODE_THERM_ONLY … #define VEGA10_THERM_OUT_MODE_THERM_VRHOT … #define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT … #define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT … #define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT … #define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT … #define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT … #define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT … #define VEGA10_UMD_PSTATE_GFXCLK_LEVEL … #define VEGA10_UMD_PSTATE_SOCCLK_LEVEL … #define VEGA10_UMD_PSTATE_MCLK_LEVEL … extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr); extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display); int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input); int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate); int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); int vega10_hwmgr_init(struct pp_hwmgr *hwmgr); #endif /* _VEGA10_HWMGR_H_ */
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