#include <linux/module.h>
#include <linux/slab.h>
#include "linux/delay.h"
#include <linux/types.h>
#include <linux/pci.h>
#include "smumgr.h"
#include "pp_debug.h"
#include "ci_smumgr.h"
#include "ppsmc.h"
#include "smu7_hwmgr.h"
#include "hardwaremanager.h"
#include "ppatomctrl.h"
#include "cgs_common.h"
#include "atombios.h"
#include "pppcielanes.h"
#include "smu7_smumgr.h"
#include "smu/smu_7_0_1_d.h"
#include "smu/smu_7_0_1_sh_mask.h"
#include "dce/dce_8_0_d.h"
#include "dce/dce_8_0_sh_mask.h"
#include "bif/bif_4_1_d.h"
#include "bif/bif_4_1_sh_mask.h"
#include "gca/gfx_7_2_d.h"
#include "gca/gfx_7_2_sh_mask.h"
#include "gmc/gmc_7_1_d.h"
#include "gmc/gmc_7_1_sh_mask.h"
#include "processpptables.h"
#define MC_CG_ARB_FREQ_F0 …
#define MC_CG_ARB_FREQ_F1 …
#define MC_CG_ARB_FREQ_F2 …
#define MC_CG_ARB_FREQ_F3 …
#define SMC_RAM_END …
#define CISLAND_MINIMUM_ENGINE_CLOCK …
#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID …
static const struct ci_pt_defaults defaults_hawaii_xt = …;
static const struct ci_pt_defaults defaults_hawaii_pro = …;
static const struct ci_pt_defaults defaults_bonaire_xt = …;
static const struct ci_pt_defaults defaults_saturn_xt = …;
static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
uint32_t smc_addr, uint32_t limit)
{ … }
static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
const uint8_t *src, uint32_t byte_count, uint32_t limit)
{ … }
static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
{ … }
static bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{ … }
static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
uint32_t *value, uint32_t limit)
{ … }
static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
{ … }
static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
uint16_t msg, uint32_t parameter)
{ … }
static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
{ … }
static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
uint32_t clock, uint32_t *vol)
{ … }
static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr,
uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk)
{ … }
static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
const struct phm_phase_shedding_limits_table *pl,
uint32_t sclk, uint32_t *p_shed)
{ … }
static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,
uint32_t clock_insr)
{ … }
static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level)
{ … }
static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
{ … }
static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
{ … }
static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr)
{ … }
static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
{ … }
static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
pp_atomctrl_voltage_table_entry *tab, uint16_t *hi,
uint16_t *lo)
{ … }
static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
pp_atomctrl_voltage_table_entry *tab,
SMU7_Discrete_VoltageLevel *smc_voltage_tab)
{ … }
static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr,
struct SMU7_Discrete_Ulv *state)
{ … }
static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr,
SMU7_Discrete_Ulv *ulv_level)
{ … }
static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
{ … }
static int ci_calculate_mclk_params(
struct pp_hwmgr *hwmgr,
uint32_t memory_clock,
SMU7_Discrete_MemoryLevel *mclk,
bool strobe_mode,
bool dllStateOn
)
{ … }
static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock,
bool strobe_mode)
{ … }
static uint8_t ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
{ … }
static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
uint32_t memory_clock, uint32_t *p_shed)
{ … }
static int ci_populate_single_memory_level(
struct pp_hwmgr *hwmgr,
uint32_t memory_clock,
SMU7_Discrete_MemoryLevel *memory_level
)
{ … }
static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
SMU7_Discrete_VoltageLevel *voltage)
{ … }
static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_memory_timing_parameters(
struct pp_hwmgr *hwmgr,
uint32_t engine_clock,
uint32_t memory_clock,
struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs
)
{ … }
static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
SMU7_Discrete_MCRegisters *mc_reg_table)
{ … }
static void ci_convert_mc_registers(
const struct ci_mc_reg_entry *entry,
SMU7_Discrete_MCRegisterSet *data,
uint32_t num_entries, uint32_t valid_flag)
{ … }
static int ci_convert_mc_reg_table_entry_to_smc(
struct pp_hwmgr *hwmgr,
const uint32_t memory_clock,
SMU7_Discrete_MCRegisterSet *mc_reg_table_data
)
{ … }
static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
SMU7_Discrete_MCRegisters *mc_regs)
{ … }
static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
SMU7_Discrete_DpmTable *table)
{ … }
static int ci_start_smc(struct pp_hwmgr *hwmgr)
{ … }
static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
{ … }
static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
{ … }
static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
{ … }
static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
{ … }
static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{ … }
static uint32_t ci_get_offsetof(uint32_t type, uint32_t member)
{ … }
static uint32_t ci_get_mac_definition(uint32_t value)
{ … }
static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
{ … }
static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
{ … }
static int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
{ … }
static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr)
{ … }
static bool ci_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg)
{ … }
static int ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
{ … }
static int ci_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
struct ci_mc_reg_table *ni_table)
{ … }
static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
struct ci_mc_reg_table *table)
{ … }
static int ci_set_valid_flag(struct ci_mc_reg_table *table)
{ … }
static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
{ … }
static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
{ … }
static int ci_smu_init(struct pp_hwmgr *hwmgr)
{ … }
static int ci_smu_fini(struct pp_hwmgr *hwmgr)
{ … }
static int ci_start_smu(struct pp_hwmgr *hwmgr)
{ … }
static int ci_update_dpm_settings(struct pp_hwmgr *hwmgr,
void *profile_setting)
{ … }
static int ci_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
{ … }
static int ci_update_vce_smc_table(struct pp_hwmgr *hwmgr)
{ … }
static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
{ … }
static void ci_reset_smc(struct pp_hwmgr *hwmgr)
{ … }
static void ci_stop_smc_clock(struct pp_hwmgr *hwmgr)
{ … }
static int ci_stop_smc(struct pp_hwmgr *hwmgr)
{ … }
const struct pp_smumgr_func ci_smu_funcs = …;