/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "amdgpu.h" #include "amdgpu_atombios.h" #include "nbio_v7_2.h" #include "nbio/nbio_7_2_0_offset.h" #include "nbio/nbio_7_2_0_sh_mask.h" #include <uapi/linux/kfd_ioctl.h> #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC … #define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX … #define regBIF_BX0_BIF_FB_EN_YC … #define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX … #define regBIF1_PCIE_MST_CTRL_3 … #define regBIF1_PCIE_MST_CTRL_3_BASE_IDX … #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT … #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT … #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK … #define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK … #define regBIF1_PCIE_TX_POWER_CTRL_1 … #define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX … #define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK … #define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK … static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev) { … } static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev) { … } static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable) { … } static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev) { … } static void nbio_v7_2_sdma_doorbell_range(struct amdgpu_device *adev, int instance, bool use_doorbell, int doorbell_index, int doorbell_size) { … } static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index, int instance) { … } static void nbio_v7_2_enable_doorbell_aperture(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_2_ih_doorbell_range(struct amdgpu_device *adev, bool use_doorbell, int doorbell_index) { … } static void nbio_v7_2_ih_control(struct amdgpu_device *adev) { … } static void nbio_v7_2_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable) { … } static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev, u64 *flags) { … } static u32 nbio_v7_2_get_hdp_flush_req_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_2_get_hdp_flush_done_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_2_get_pcie_index_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_2_get_pcie_data_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_2_get_pcie_port_index_offset(struct amdgpu_device *adev) { … } static u32 nbio_v7_2_get_pcie_port_data_offset(struct amdgpu_device *adev) { … } const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = …; static void nbio_v7_2_init_registers(struct amdgpu_device *adev) { … } #define MMIO_REG_HOLE_OFFSET … static void nbio_v7_2_set_reg_remap(struct amdgpu_device *adev) { … } const struct amdgpu_nbio_funcs nbio_v7_2_funcs = …;
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