/* * Copyright 2015 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include "pp_debug.h" #include <linux/delay.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/slab.h> #include <asm/div64.h> #if IS_ENABLED(CONFIG_X86_64) #include <asm/intel-family.h> #endif #include <drm/amdgpu_drm.h> #include "ppatomctrl.h" #include "atombios.h" #include "pptable_v1_0.h" #include "pppcielanes.h" #include "amd_pcie_helpers.h" #include "hardwaremanager.h" #include "process_pptables_v1_0.h" #include "cgs_common.h" #include "smu7_common.h" #include "hwmgr.h" #include "smu7_hwmgr.h" #include "smu_ucode_xfer_vi.h" #include "smu7_powertune.h" #include "smu7_dyn_defaults.h" #include "smu7_thermal.h" #include "smu7_clockpowergating.h" #include "processpptables.h" #include "pp_thermal.h" #include "smu7_baco.h" #include "smu7_smumgr.h" #include "polaris10_smumgr.h" #include "ivsrcid/ivsrcid_vislands30.h" #define MC_CG_ARB_FREQ_F0 … #define MC_CG_ARB_FREQ_F1 … #define MC_CG_ARB_FREQ_F2 … #define MC_CG_ARB_FREQ_F3 … #define MC_CG_SEQ_DRAMCONF_S0 … #define MC_CG_SEQ_DRAMCONF_S1 … #define MC_CG_SEQ_YCLK_SUSPEND … #define MC_CG_SEQ_YCLK_RESUME … #define SMC_CG_IND_START … #define SMC_CG_IND_END … #define MEM_FREQ_LOW_LATENCY … #define MEM_FREQ_HIGH_LATENCY … #define MEM_LATENCY_HIGH … #define MEM_LATENCY_LOW … #define MEM_LATENCY_ERR … #define MC_SEQ_MISC0_GDDR5_SHIFT … #define MC_SEQ_MISC0_GDDR5_MASK … #define MC_SEQ_MISC0_GDDR5_VALUE … #define PCIE_BUS_CLK … #define TCLK … static struct profile_mode_setting smu7_profiling[7] = …; #define PPSMC_MSG_SetVBITimeout_VEGAM … #define ixPWR_SVI2_PLANE1_LOAD … #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK … #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK … #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT … #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT … #define STRAP_EVV_REVISION_MSB … #define STRAP_EVV_REVISION_LSB … /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ enum DPM_EVENT_SRC { … }; #define ixDIDT_SQ_EDC_CTRL … #define ixDIDT_SQ_EDC_THRESHOLD … #define ixDIDT_SQ_EDC_STALL_PATTERN_1_2 … #define ixDIDT_SQ_EDC_STALL_PATTERN_3_4 … #define ixDIDT_SQ_EDC_STALL_PATTERN_5_6 … #define ixDIDT_SQ_EDC_STALL_PATTERN_7 … #define ixDIDT_TD_EDC_CTRL … #define ixDIDT_TD_EDC_THRESHOLD … #define ixDIDT_TD_EDC_STALL_PATTERN_1_2 … #define ixDIDT_TD_EDC_STALL_PATTERN_3_4 … #define ixDIDT_TD_EDC_STALL_PATTERN_5_6 … #define ixDIDT_TD_EDC_STALL_PATTERN_7 … #define ixDIDT_TCP_EDC_CTRL … #define ixDIDT_TCP_EDC_THRESHOLD … #define ixDIDT_TCP_EDC_STALL_PATTERN_1_2 … #define ixDIDT_TCP_EDC_STALL_PATTERN_3_4 … #define ixDIDT_TCP_EDC_STALL_PATTERN_5_6 … #define ixDIDT_TCP_EDC_STALL_PATTERN_7 … #define ixDIDT_DB_EDC_CTRL … #define ixDIDT_DB_EDC_THRESHOLD … #define ixDIDT_DB_EDC_STALL_PATTERN_1_2 … #define ixDIDT_DB_EDC_STALL_PATTERN_3_4 … #define ixDIDT_DB_EDC_STALL_PATTERN_5_6 … #define ixDIDT_DB_EDC_STALL_PATTERN_7 … uint32_t DIDTEDCConfig_P12[] = …; static const unsigned long PhwVIslands_Magic = …; static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); static int smu7_notify_has_display(struct pp_hwmgr *hwmgr); static struct smu7_power_state *cast_phw_smu7_power_state( struct pp_hw_power_state *hw_ps) { … } static const struct smu7_power_state *cast_const_phw_smu7_power_state( const struct pp_hw_power_state *hw_ps) { … } /** * smu7_get_mc_microcode_version - Find the MC microcode version and store it in the HwMgr struct * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) { … } static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) { … } static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) { … } /** * smu7_enable_smc_voltage_controller - Enable voltage control * * @hwmgr: the address of the powerplay hardware manager. * Return: always PP_Result_OK */ static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) { … } /** * smu7_voltage_control - Checks if we want to support voltage control * * @hwmgr: the address of the powerplay hardware manager. */ static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr) { … } /** * smu7_enable_voltage_control - Enable voltage control * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr) { … } static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table, struct phm_clock_voltage_dependency_table *voltage_dependency_table ) { … } /** * smu7_construct_voltage_tables - Create Voltage Tables. * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) { … } /** * smu7_program_static_screen_threshold_parameters - Programs static screed detection parameters * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_program_static_screen_threshold_parameters( struct pp_hwmgr *hwmgr) { … } /** * smu7_enable_display_gap - Setup display gap for glitch free memory clock switching. * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) { … } /** * smu7_program_voting_clients - Programs activity state transition voting clients * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) { … } static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) { … } /* Copy one arb setting to another and then switch the active set. * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. */ static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, uint32_t arb_src, uint32_t arb_dest) { … } static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) { … } /** * smu7_initial_switch_from_arbf0_to_f1 - Initial switch from ARB F0->F1 * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 * This function is to be called from the SetPowerState table. */ static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) { … } static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) { … } static uint16_t smu7_override_pcie_speed(struct pp_hwmgr *hwmgr) { … } static uint16_t smu7_override_pcie_width(struct pp_hwmgr *hwmgr) { … } static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) { … } static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) { … } /* * This function is to initialize all DPM state tables * for SMU7 based on the dependency table. * Dynamic state patching function will then trim these * state tables to the allowed range based * on the power policy or external client requests, * such as UVD request, etc. */ static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) { … } static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) { … } static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr) { … } static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr) { … } static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) { … } static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) { … } static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) { … } static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr) { … } static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) { … } static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) { … } static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { … } static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { … } static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr) { … } static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) { … } static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { … } static int smu7_start_dpm(struct pp_hwmgr *hwmgr) { … } static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { … } static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) { … } static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) { … } static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, PHM_AutoThrottleSource source) { … } static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) { … } static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, PHM_AutoThrottleSource source) { … } static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) { … } static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) { … } static int smu7_program_edc_didt_registers(struct pp_hwmgr *hwmgr, uint32_t *cac_config_regs, AtomCtrl_EDCLeakgeTable *edc_leakage_table) { … } static int smu7_populate_edc_leakage_registers(struct pp_hwmgr *hwmgr) { … } static void smu7_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) { … } static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) { … } static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) { … } static int smu7_update_avfs(struct pp_hwmgr *hwmgr) { … } static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) { … } static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) { … } static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr) { … } /** * smu7_get_evv_voltages - Get Leakage VDDC based on leakage ID. * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) { … } /** * smu7_patch_ppt_v1_with_vdd_leakage - Change virtual leakage voltage to actual value. * * @hwmgr: the address of the powerplay hardware manager. * @voltage: pointer to changing voltage * @leakage_table: pointer to leakage table */ static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr, uint16_t *voltage, struct smu7_leakage_voltage *leakage_table) { … } /** * smu7_patch_lookup_table_with_leakage - Patch voltage lookup table by EVV leakages. * * @hwmgr: the address of the powerplay hardware manager. * @lookup_table: pointer to voltage lookup table * @leakage_table: pointer to leakage table * Return: always 0 */ static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, struct smu7_leakage_voltage *leakage_table) { … } static int smu7_patch_clock_voltage_limits_with_vddc_leakage( struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table, uint16_t *vddc) { … } static int smu7_patch_voltage_dependency_tables_with_lookup_table( struct pp_hwmgr *hwmgr) { … } static int phm_add_voltage(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *look_up_table, phm_ppt_v1_voltage_lookup_record *record) { … } static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) { … } static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) { … } static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_voltage_lookup_table *lookup_table) { … } static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr) { … } static int smu7_find_highest_vddc(struct pp_hwmgr *hwmgr) { … } static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) { … } static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) { … } static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) { … } /** * smu7_patch_ppt_v0_with_vdd_leakage - Change virtual leakage voltage to actual value. * * @hwmgr: the address of the powerplay hardware manager. * @voltage: pointer to changing voltage * @leakage_table: pointer to leakage table */ static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr, uint32_t *voltage, struct smu7_leakage_voltage *leakage_table) { … } static int smu7_patch_vddc(struct pp_hwmgr *hwmgr, struct phm_clock_voltage_dependency_table *tab) { … } static int smu7_patch_vddci(struct pp_hwmgr *hwmgr, struct phm_clock_voltage_dependency_table *tab) { … } static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr, struct phm_vce_clock_voltage_dependency_table *tab) { … } static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr, struct phm_uvd_clock_voltage_dependency_table *tab) { … } static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, struct phm_phase_shedding_limits_table *tab) { … } static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr, struct phm_samu_clock_voltage_dependency_table *tab) { … } static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr, struct phm_acp_clock_voltage_dependency_table *tab) { … } static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, struct phm_clock_and_voltage_limits *tab) { … } static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) { … } static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) { … } static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) { … } static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { … } static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr) { … } #define LEAKAGE_ID_MSB … #define LEAKAGE_ID_LSB … static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr) { … } static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { … } static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) { … } static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) { … } static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { … } static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) { … } static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) { … } static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) { … } static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) { … } static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr, uint32_t vblank_time_us) { … } static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, struct pp_power_state *request_ps, const struct pp_power_state *current_ps) { … } static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { … } static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { … } static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps) { … } static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) { … } static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, void *state, struct pp_power_state *power_state, void *pp_table, uint32_t classification_flag) { … } static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, unsigned long entry_index, struct pp_power_state *state) { … } static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *power_state, unsigned int index, const void *clock_info) { … } static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, unsigned long entry_index, struct pp_power_state *state) { … } static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, unsigned long entry_index, struct pp_power_state *state) { … } static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) { … } static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { … } static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) { … } static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr, const struct smu7_power_state *smu7_ps) { … } static int smu7_request_link_speed_change_before_state_change( struct pp_hwmgr *hwmgr, const void *input) { … } static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { … } static int smu7_populate_and_upload_sclk_mclk_dpm_levels( struct pp_hwmgr *hwmgr, const void *input) { … } static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, struct smu7_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) { … } static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr, const struct smu7_power_state *smu7_ps) { … } static int smu7_generate_dpm_level_enable_mask( struct pp_hwmgr *hwmgr, const void *input) { … } static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { … } static int smu7_notify_link_speed_change_after_state_change( struct pp_hwmgr *hwmgr, const void *input) { … } static int smu7_notify_no_display(struct pp_hwmgr *hwmgr) { … } static int smu7_notify_has_display(struct pp_hwmgr *hwmgr) { … } static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) { … } static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) { … } static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) { … } static int smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) { … } /** * smu7_program_display_gap - Programs the display gap * * @hwmgr: the address of the powerplay hardware manager. * Return: always OK */ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) { … } static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { … } /** * smu7_set_max_fan_rpm_output - Set maximum target operating fan output RPM * * @hwmgr: the address of the powerplay hardware manager. * @us_max_fan_rpm: max operating fan RPM value. * Return: The response that came from the SMC. */ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) { … } static const struct amdgpu_irq_src_funcs smu7_irq_funcs = …; static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr) { … } static bool smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) { … } static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, const struct smu7_performance_level *pl2) { … } static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) { … } static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr) { … } static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr) { … } /** * smu7_get_memory_type - Find out if memory is GDDR5. * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_get_memory_type(struct pp_hwmgr *hwmgr) { … } /** * smu7_enable_acpi_power_management - Enables Dynamic Power Management by SMC * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr) { … } /** * smu7_init_power_gate_state - Initialize PowerGating States for different engines * * @hwmgr: the address of the powerplay hardware manager. * Return: always 0 */ static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr) { … } static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) { … } static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) { … } static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask) { … } static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf) { … } static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) { … } static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) { … } static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) { … } static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) { … } static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) { … } static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) { … } static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) { … } static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) { … } static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) { … } static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) { … } static int smu7_get_sclks_with_latency(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int smu7_get_mclks_with_latency(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int smu7_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct pp_clock_levels_with_latency *clocks) { … } static int smu7_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, void *clock_range) { … } static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, uint32_t virtual_addr_low, uint32_t virtual_addr_hi, uint32_t mc_addr_low, uint32_t mc_addr_hi, uint32_t size) { … } static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) { … } static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *thermal_data) { … } static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, enum PP_OD_DPM_TABLE_COMMAND type, uint32_t clk, uint32_t voltage) { … } static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, enum PP_OD_DPM_TABLE_COMMAND type, long *input, uint32_t size) { … } static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) { … } static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr, enum PP_SMC_POWER_PROFILE requst) { … } static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) { … } static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, PHM_PerformanceLevelDesignation designation, uint32_t index, PHM_PerformanceLevel *level) { … } static int smu7_power_off_asic(struct pp_hwmgr *hwmgr) { … } static const struct pp_hwmgr_func smu7_hwmgr_funcs = …; uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, uint32_t clock_insr) { … } int smu7_init_function_pointers(struct pp_hwmgr *hwmgr) { … }
Codebase Browser
linux