linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h

/*
 * Copyright 2017 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef SMU10_HWMGR_H
#define SMU10_HWMGR_H

#include "hwmgr.h"
#include "smu10_inc.h"
#include "smu10_driver_if.h"
#include "rv_ppsmc.h"


#define SMU10_MAX_HARDWARE_POWERLEVELS
#define SMU10_DYNCLK_NUMBER_OF_TREND_COEFFICIENTS

#define DPMFlags_SCLK_Enabled
#define DPMFlags_UVD_Enabled
#define DPMFlags_VCE_Enabled
#define DPMFlags_ACP_Enabled
#define DPMFlags_ForceHighestValid

/* Do not change the following, it is also defined in SMU8.h */
#define SMU_EnabledFeatureScoreboard_AcpDpmOn
#define SMU_EnabledFeatureScoreboard_SclkDpmOn
#define SMU_EnabledFeatureScoreboard_UvdDpmOn
#define SMU_EnabledFeatureScoreboard_VceDpmOn

#define SMU_PHYID_SHIFT

#define SMU10_PCIE_POWERGATING_TARGET_GFX
#define SMU10_PCIE_POWERGATING_TARGET_DDI
#define SMU10_PCIE_POWERGATING_TARGET_PLLCASCADE
#define SMU10_PCIE_POWERGATING_TARGET_PHY

enum VQ_TYPE {};

#define SUSTAINABLE_SCLK_MASK
#define SUSTAINABLE_SCLK_SHIFT
#define SUSTAINABLE_CU_MASK
#define SUSTAINABLE_CU_SHIFT

struct smu10_dpm_entry {};

struct smu10_power_level {};

/*used for the nbpsFlags field in smu10_power state*/
#define SMU10_POWERSTATE_FLAGS_NBPS_FORCEHIGH
#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH
#define SMU10_POWERSTATE_FLAGS_NBPS_LOCKTOLOW

#define SMU10_POWERSTATE_FLAGS_BAPM_DISABLE

struct smu10_uvd_clocks {};

struct pp_disable_nbpslo_flags {};


enum smu10_pstate_previous_action {};

struct smu10_power_state {};

#define SMU10_NUM_NBPSTATES
#define SMU10_NUM_NBPMEMORYCLOCK


struct smu10_display_phy_info_entry {};

#define SMU10_MAX_DISPLAYPHY_IDS

struct smu10_display_phy_info {};

#define MAX_DISPLAY_CLOCK_LEVEL

struct smu10_system_info{};

#define MAX_REGULAR_DPM_NUMBER

struct smu10_mclk_latency_entries {};

struct smu10_mclk_latency_table {};

struct smu10_clock_voltage_dependency_record {};


struct smu10_voltage_dependency_table {};

struct smu10_clock_voltage_information {};

struct smu10_hwmgr {};

struct pp_hwmgr;

int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);

/* UMD PState SMU10 Msg Parameters in MHz */
#define SMU10_UMD_PSTATE_GFXCLK
#define SMU10_UMD_PSTATE_SOCCLK
#define SMU10_UMD_PSTATE_FCLK
#define SMU10_UMD_PSTATE_VCE
#define SMU10_UMD_PSTATE_PROFILE_VCE

#define SMU10_UMD_PSTATE_PEAK_SOCCLK
#define SMU10_UMD_PSTATE_PEAK_FCLK

#define SMU10_UMD_PSTATE_MIN_FCLK
#define SMU10_UMD_PSTATE_MIN_SOCCLK
#define SMU10_UMD_PSTATE_MIN_VCE

#endif