smu10_hwmgr.c | Explore in Territory

/*
 * Copyright 2015 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "pp_debug.h"
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include "atom-types.h"
#include "atombios.h"
#include "processpptables.h"
#include "cgs_common.h"
#include "smumgr.h"
#include "hwmgr.h"
#include "hardwaremanager.h"
#include "rv_ppsmc.h"
#include "smu10_hwmgr.h"
#include "power_state.h"
#include "soc15_common.h"
#include "smu10.h"
#include "asic_reg/pwr/pwr_10_0_offset.h"
#include "asic_reg/pwr/pwr_10_0_sh_mask.h"

#define SMU10_MAX_DEEPSLEEP_DIVIDER_ID …
#define SMU10_MINIMUM_ENGINE_CLOCK …
#define SCLK_MIN_DIV_INTV_SHIFT …
#define SMU10_DISPCLK_BYPASS_THRESHOLD …
#define SMC_RAM_END …

static const unsigned long SMU10_Magic = …;


static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
		struct pp_display_clock_request *clock_req)
{ … }

static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
{ … }

static const struct smu10_power_state *cast_const_smu10_ps(
				const struct pp_hw_power_state *hw_ps)
{ … }

static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
			struct phm_clock_and_voltage_limits *table)
{ … }

static int smu10_init_dynamic_state_adjustment_rule_settings(
							struct pp_hwmgr *hwmgr)
{ … }

static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
{ … }

static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
{ … }

static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
{ … }

static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
{ … }

static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
{ … }

static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
{ … }

static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
{ … }

static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
{ … }

static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
{ … }


static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
{ … }

static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
{ … }

static void smu10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
{ … }

static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
				struct pp_power_state  *prequest_ps,
			const struct pp_power_state *pcurrent_ps)
{ … }

/* temporary hardcoded clock voltage breakdown tables */
static const DpmClock_t VddDcfClk[] = …;

static const DpmClock_t VddSocClk[] = …;

static const DpmClock_t VddFClk[] = …;

static const DpmClock_t VddDispClk[] = …;

static const DpmClock_t VddDppClk[] = …;

static const DpmClock_t VddPhyClk[] = …;

static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
			struct smu10_voltage_dependency_table **pptable,
			uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
{ … }


static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
				enum amd_dpm_forced_level level)
{ … }

static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
{ … }

static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
{ … }

static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
					struct pp_hw_power_state *hw_ps)
{ … }

static int smu10_dpm_get_pp_table_entry_callback(
						     struct pp_hwmgr *hwmgr,
					   struct pp_hw_power_state *hw_ps,
							  unsigned int index,
						     const void *clock_info)
{ … }

static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
		    unsigned long entry, struct pp_power_state *ps)
{ … }

static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
{ … }


static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
			bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
{ … }

static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
		struct amd_pp_simple_clock_info *info)
{ … }

static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
		enum pp_clock_type type, uint32_t mask)
{ … }

static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
		enum pp_clock_type type, char *buf)
{ … }

static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
				PHM_PerformanceLevelDesignation designation, uint32_t index,
				PHM_PerformanceLevel *level)
{ … }

static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
	const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
{ … }

#define MEM_FREQ_LOW_LATENCY …
#define MEM_FREQ_HIGH_LATENCY …
#define MEM_LATENCY_HIGH …
#define MEM_LATENCY_LOW …
#define MEM_LATENCY_ERR …


static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
		uint32_t clock)
{ … }

static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
		enum amd_pp_clock_type type,
		struct pp_clock_levels_with_latency *clocks)
{ … }

static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
		enum amd_pp_clock_type type,
		struct pp_clock_levels_with_voltage *clocks)
{ … }



static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
{ … }

static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
			  void *value, int *size)
{ … }

static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
		void *clock_ranges)
{ … }

static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
{ … }

static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
{ … }

static int conv_power_profile_to_pplib_workload(int power_profile)
{ … }

static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
{ … }

static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
{ … }

static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
{ … }

static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
{ … }

static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
					enum PP_OD_DPM_TABLE_COMMAND type,
					long *input, uint32_t size)
{ … }

static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
{ … }

static const struct pp_hwmgr_func smu10_hwmgr_funcs = …;

int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
{ … }
linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c
