linux/arch/x86/include/asm/special_insns.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_SPECIAL_INSNS_H
#define _ASM_X86_SPECIAL_INSNS_H

#ifdef __KERNEL__
#include <asm/nops.h>
#include <asm/processor-flags.h>

#include <linux/errno.h>
#include <linux/irqflags.h>
#include <linux/jump_label.h>

/*
 * The compiler should not reorder volatile asm statements with respect to each
 * other: they should execute in program order. However GCC 4.9.x and 5.x have
 * a bug (which was fixed in 8.1, 7.3 and 6.5) where they might reorder
 * volatile asm. The write functions are not affected since they have memory
 * clobbers preventing reordering. To prevent reads from being reordered with
 * respect to writes, use a dummy memory operand.
 */

#define __FORCE_ORDER …

void native_write_cr0(unsigned long val);

static inline unsigned long native_read_cr0(void)
{ … }

static __always_inline unsigned long native_read_cr2(void)
{ … }

static __always_inline void native_write_cr2(unsigned long val)
{ … }

static inline unsigned long __native_read_cr3(void)
{ … }

static inline void native_write_cr3(unsigned long val)
{ … }

static inline unsigned long native_read_cr4(void)
{ … }

void native_write_cr4(unsigned long val);

#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
static inline u32 rdpkru(void)
{ … }

static inline void wrpkru(u32 pkru)
{ … }

#else
static inline u32 rdpkru(void)
{
	return 0;
}

static inline void wrpkru(u32 pkru)
{
}
#endif

static __always_inline void native_wbinvd(void)
{ … }

static inline unsigned long __read_cr4(void)
{ … }

#ifdef CONFIG_PARAVIRT_XXL
#include <asm/paravirt.h>
#else

static inline unsigned long read_cr0(void)
{
	return native_read_cr0();
}

static inline void write_cr0(unsigned long x)
{
	native_write_cr0(x);
}

static __always_inline unsigned long read_cr2(void)
{
	return native_read_cr2();
}

static __always_inline void write_cr2(unsigned long x)
{
	native_write_cr2(x);
}

/*
 * Careful!  CR3 contains more than just an address.  You probably want
 * read_cr3_pa() instead.
 */
static inline unsigned long __read_cr3(void)
{
	return __native_read_cr3();
}

static inline void write_cr3(unsigned long x)
{
	native_write_cr3(x);
}

static inline void __write_cr4(unsigned long x)
{
	native_write_cr4(x);
}

static __always_inline void wbinvd(void)
{
	native_wbinvd();
}

#endif /* CONFIG_PARAVIRT_XXL */

static __always_inline void clflush(volatile void *__p)
{ … }

static inline void clflushopt(volatile void *__p)
{ … }

static inline void clwb(volatile void *__p)
{ … }

#ifdef CONFIG_X86_USER_SHADOW_STACK
static inline int write_user_shstk_64(u64 __user *addr, u64 val)
{ … }
#endif /* CONFIG_X86_USER_SHADOW_STACK */

#define nop() …

static inline void serialize(void)
{ … }

/* The dst parameter must be 64-bytes aligned */
static inline void movdir64b(void *dst, const void *src)
{ … }

static inline void movdir64b_io(void __iomem *dst, const void *src)
{ … }

/**
 * enqcmds - Enqueue a command in supervisor (CPL0) mode
 * @dst: destination, in MMIO space (must be 512-bit aligned)
 * @src: 512 bits memory operand
 *
 * The ENQCMDS instruction allows software to write a 512-bit command to
 * a 512-bit-aligned special MMIO region that supports the instruction.
 * A return status is loaded into the ZF flag in the RFLAGS register.
 * ZF = 0 equates to success, and ZF = 1 indicates retry or error.
 *
 * This function issues the ENQCMDS instruction to submit data from
 * kernel space to MMIO space, in a unit of 512 bits. Order of data access
 * is not guaranteed, nor is a memory barrier performed afterwards. It
 * returns 0 on success and -EAGAIN on failure.
 *
 * Warning: Do not use this helper unless your driver has checked that the
 * ENQCMDS instruction is supported on the platform and the device accepts
 * ENQCMDS.
 */
static inline int enqcmds(void __iomem *dst, const void *src)
{ … }

static __always_inline void tile_release(void)
{ … }

#endif /* __KERNEL__ */

#endif /* _ASM_X86_SPECIAL_INSNS_H */