/* SPDX-License-Identifier: GPL-2.0 */ /* * FPU data structures: */ #ifndef _ASM_X86_FPU_TYPES_H #define _ASM_X86_FPU_TYPES_H #include <asm/page_types.h> /* * The legacy x87 FPU state format, as saved by FSAVE and * restored by the FRSTOR instructions: */ struct fregs_state { … }; /* * The legacy fx SSE/MMX FPU state format, as saved by FXSAVE and * restored by the FXRSTOR instructions. It's similar to the FSAVE * format, but differs in some areas, plus has extensions at * the end for the XMM registers. */ struct fxregs_state { … } __attribute__((aligned …)); /* Default value for fxregs_state.mxcsr: */ #define MXCSR_DEFAULT … /* Copy both mxcsr & mxcsr_flags with a single u64 memcpy: */ #define MXCSR_AND_FLAGS_SIZE … /* * Software based FPU emulation state. This is arbitrary really, * it matches the x87 format to make it easier to understand: */ struct swregs_state { … }; /* * List of XSAVE features Linux knows about: */ enum xfeature { … }; #define XFEATURE_MASK_FP … #define XFEATURE_MASK_SSE … #define XFEATURE_MASK_YMM … #define XFEATURE_MASK_BNDREGS … #define XFEATURE_MASK_BNDCSR … #define XFEATURE_MASK_OPMASK … #define XFEATURE_MASK_ZMM_Hi256 … #define XFEATURE_MASK_Hi16_ZMM … #define XFEATURE_MASK_PT … #define XFEATURE_MASK_PKRU … #define XFEATURE_MASK_PASID … #define XFEATURE_MASK_CET_USER … #define XFEATURE_MASK_CET_KERNEL … #define XFEATURE_MASK_LBR … #define XFEATURE_MASK_XTILE_CFG … #define XFEATURE_MASK_XTILE_DATA … #define XFEATURE_MASK_FPSSE … #define XFEATURE_MASK_AVX512 … #ifdef CONFIG_X86_64 #define XFEATURE_MASK_XTILE … #else #define XFEATURE_MASK_XTILE … #endif #define FIRST_EXTENDED_XFEATURE … struct reg_128_bit { … }; struct reg_256_bit { … }; struct reg_512_bit { … }; struct reg_1024_byte { … }; /* * State component 2: * * There are 16x 256-bit AVX registers named YMM0-YMM15. * The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15) * and are stored in 'struct fxregs_state::xmm_space[]' in the * "legacy" area. * * The high 128 bits are stored here. */ struct ymmh_struct { … } __packed; /* Intel MPX support: */ struct mpx_bndreg { … } __packed; /* * State component 3 is used for the 4 128-bit bounds registers */ struct mpx_bndreg_state { … } __packed; /* * State component 4 is used for the 64-bit user-mode MPX * configuration register BNDCFGU and the 64-bit MPX status * register BNDSTATUS. We call the pair "BNDCSR". */ struct mpx_bndcsr { … } __packed; /* * The BNDCSR state is padded out to be 64-bytes in size. */ struct mpx_bndcsr_state { … } __packed; /* AVX-512 Components: */ /* * State component 5 is used for the 8 64-bit opmask registers * k0-k7 (opmask state). */ struct avx_512_opmask_state { … } __packed; /* * State component 6 is used for the upper 256 bits of the * registers ZMM0-ZMM15. These 16 256-bit values are denoted * ZMM0_H-ZMM15_H (ZMM_Hi256 state). */ struct avx_512_zmm_uppers_state { … } __packed; /* * State component 7 is used for the 16 512-bit registers * ZMM16-ZMM31 (Hi16_ZMM state). */ struct avx_512_hi16_state { … } __packed; /* * State component 9: 32-bit PKRU register. The state is * 8 bytes long but only 4 bytes is used currently. */ struct pkru_state { … } __packed; /* * State component 11 is Control-flow Enforcement user states */ struct cet_user_state { … }; /* * State component 15: Architectural LBR configuration state. * The size of Arch LBR state depends on the number of LBRs (lbr_depth). */ struct lbr_entry { … }; struct arch_lbr_state { … }; /* * State component 17: 64-byte tile configuration register. */ struct xtile_cfg { … } __packed; /* * State component 18: 1KB tile data register. * Each register represents 16 64-byte rows of the matrix * data. But the number of registers depends on the actual * implementation. */ struct xtile_data { … } __packed; /* * State component 10 is supervisor state used for context-switching the * PASID state. */ struct ia32_pasid_state { … } __packed; struct xstate_header { … } __attribute__((packed)); /* * xstate_header.xcomp_bv[63] indicates that the extended_state_area * is in compacted format. */ #define XCOMP_BV_COMPACTED_FORMAT … /* * This is our most modern FPU state format, as saved by the XSAVE * and restored by the XRSTOR instructions. * * It consists of a legacy fxregs portion, an xstate header and * subsequent areas as defined by the xstate header. Not all CPUs * support all the extensions, so the size of the extended area * can vary quite a bit between CPUs. */ struct xregs_state { … } __attribute__ ((packed, aligned …)); /* * This is a union of all the possible FPU state formats * put together, so that we can pick the right one runtime. * * The size of the structure is determined by the largest * member - which is the xsave area. The padding is there * to ensure that statically-allocated task_structs (just * the init_task today) have enough space. */ fpregs_state; struct fpstate { … } __aligned(…); #define FPU_GUEST_PERM_LOCKED … struct fpu_state_perm { … }; /* * Highest level per task FPU state data structure that * contains the FPU register state plus various FPU * state fields: */ struct fpu { … }; /* * Guest pseudo FPU container */ struct fpu_guest { … }; /* * FPU state configuration data. Initialized at boot time. Read only after init. */ struct fpu_state_config { … }; /* FPU state configuration information */ extern struct fpu_state_config fpu_kernel_cfg, fpu_user_cfg; #endif /* _ASM_X86_FPU_TYPES_H */
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