/* * Copyright 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * */ #include <linux/delay.h> #include <linux/module.h> #include <linux/slab.h> #include "hwmgr.h" #include "amd_powerplay.h" #include "vega12_smumgr.h" #include "hardwaremanager.h" #include "ppatomfwctrl.h" #include "atomfirmware.h" #include "cgs_common.h" #include "vega12_inc.h" #include "pppcielanes.h" #include "vega12_hwmgr.h" #include "vega12_processpptables.h" #include "vega12_pptable.h" #include "vega12_thermal.h" #include "vega12_ppsmc.h" #include "pp_debug.h" #include "amd_pcie_helpers.h" #include "ppinterrupt.h" #include "pp_overdriver.h" #include "pp_thermal.h" #include "vega12_baco.h" #define smnPCIE_LC_SPEED_CNTL … #define smnPCIE_LC_LINK_WIDTH_CNTL … #define LINK_WIDTH_MAX … #define LINK_SPEED_MAX … static const int link_width[] = …; static const int link_speed[] = …; static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, uint32_t *clock, PPCLK_e clock_select, bool max); static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr) { … } static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr) { … } static int vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr) { … } static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) { … } static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { … } static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { … } static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr) { … } static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr) { … } /* * @fn vega12_init_dpm_state * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff. * * @param dpm_state - the address of the DPM Table to initiailize. * @return None. */ static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state) { … } static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr) { … } static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, PPCLK_e clk_id, uint32_t *num_of_levels) { … } static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, PPCLK_e clkID, uint32_t index, uint32_t *clock) { … } static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) { … } /* * This function is to initialize all DPM state tables * for SMU based on the dependency table. * Dynamic state patching function will then trim these * state tables to the allowed range based * on the power policy or external client requests, * such as UVD request, etc. */ static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) { … } #if 0 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr) { struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table); uint32_t min_level; hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE; hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE; /* Optimize compute power profile: Use only highest * 2 power levels (if more than 2 are available) */ if (dpm_table->count > 2) min_level = dpm_table->count - 2; else if (dpm_table->count == 2) min_level = 1; else min_level = 0; hwmgr->default_compute_power_profile.min_sclk = dpm_table->dpm_levels[min_level].value; hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile; hwmgr->compute_power_profile = hwmgr->default_compute_power_profile; return 0; } #endif /** * vega12_init_smc_table - Initializes the SMC table and uploads it * * @hwmgr: the address of the powerplay hardware manager. * return: always 0 */ static int vega12_init_smc_table(struct pp_hwmgr *hwmgr) { … } static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr) { … } static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr) { … } static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr) { … } static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr) { … } static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr) { … } static int vega12_odn_initialize_default_settings( struct pp_hwmgr *hwmgr) { … } static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, uint32_t adjust_percent) { … } static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr) { … } static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, PPCLK_e clkid, struct vega12_clock_range *clock) { … } static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr) { … } static void vega12_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) { … } static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr) { … } static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps) { … } static uint32_t vega12_find_lowest_dpm_level( struct vega12_single_dpm_table *table) { … } static uint32_t vega12_find_highest_dpm_level( struct vega12_single_dpm_table *table) { … } static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr) { … } static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr) { … } int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) { … } static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { … } static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { … } static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table, bool bypass_cache) { … } static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) { … } static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq) { … } static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq) { … } static int vega12_get_current_activity_percent( struct pp_hwmgr *hwmgr, int idx, uint32_t *activity_percent) { … } static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx, void *value, int *size) { … } static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_disp) { … } static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr, struct pp_display_clock_request *clock_req) { … } static int vega12_notify_smc_display_config_after_ps_adjustment( struct pp_hwmgr *hwmgr) { … } static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr) { … } static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr) { … } static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { … } static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) { … } static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) { … } static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) { … } static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr) { … } static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *info) { … } static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr, uint32_t *clock, PPCLK_e clock_select, bool max) { … } static int vega12_get_sclks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clock) { … } static int vega12_get_memclocks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int vega12_get_socclocks(struct pp_hwmgr *hwmgr, struct pp_clock_levels_with_latency *clocks) { … } static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct pp_clock_levels_with_latency *clocks) { … } static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct pp_clock_levels_with_voltage *clocks) { … } static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, void *clock_ranges) { … } static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask) { … } static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf) { … } static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks) { … } static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr) { … } static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr) { … } static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr) { … } static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr) { … } static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf) { … } static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr) { … } static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr, struct vega12_single_dpm_table *dpm_table) { … } static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { … } static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { … } static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) { … } static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate) { … } static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate) { … } static bool vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) { … } static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr) { … } static int vega12_power_off_asic(struct pp_hwmgr *hwmgr) { … } #if 0 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr, uint32_t *sclk_idx, uint32_t *mclk_idx, uint32_t min_sclk, uint32_t min_mclk) { struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); struct vega12_dpm_table *dpm_table = &(data->dpm_table); uint32_t i; for (i = 0; i < dpm_table->gfx_table.count; i++) { if (dpm_table->gfx_table.dpm_levels[i].enabled && dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) { *sclk_idx = i; break; } } for (i = 0; i < dpm_table->mem_table.count; i++) { if (dpm_table->mem_table.dpm_levels[i].enabled && dpm_table->mem_table.dpm_levels[i].value >= min_mclk) { *mclk_idx = i; break; } } } #endif #if 0 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr, struct amd_pp_profile *request) { return 0; } static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr) { struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); struct vega12_single_dpm_table *golden_sclk_table = &(data->golden_dpm_table.gfx_table); int value = sclk_table->dpm_levels[sclk_table->count - 1].value; int golden_value = golden_sclk_table->dpm_levels [golden_sclk_table->count - 1].value; value -= golden_value; value = DIV_ROUND_UP(value * 100, golden_value); return value; } static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) { return 0; } static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr) { struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend); struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); struct vega12_single_dpm_table *golden_mclk_table = &(data->golden_dpm_table.mem_table); int value = mclk_table->dpm_levels[mclk_table->count - 1].value; int golden_value = golden_mclk_table->dpm_levels [golden_mclk_table->count - 1].value; value -= golden_value; value = DIV_ROUND_UP(value * 100, golden_value); return value; } static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) { return 0; } #endif static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, uint32_t virtual_addr_low, uint32_t virtual_addr_hi, uint32_t mc_addr_low, uint32_t mc_addr_hi, uint32_t size) { … } static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *thermal_data) { … } static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) { … } static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr) { … } static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) { … } static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, PHM_PerformanceLevelDesignation designation, uint32_t index, PHM_PerformanceLevel *level) { … } static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state) { … } static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) { … } static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr, void **table) { … } static const struct pp_hwmgr_func vega12_hwmgr_funcs = …; int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) { … }
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