#ifndef ADRENO_COMMON_XML #define ADRENO_COMMON_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum chip { … }; enum adreno_pa_su_sc_draw { … }; enum adreno_compare_func { … }; enum adreno_stencil_op { … }; enum adreno_rb_blend_factor { … }; enum adreno_rb_surface_endian { … }; enum adreno_rb_dither_mode { … }; enum adreno_rb_depth_format { … }; enum adreno_rb_copy_control_mode { … }; enum a3xx_rop_code { … }; enum a3xx_render_mode { … }; enum a3xx_msaa_samples { … }; enum a3xx_threadmode { … }; enum a3xx_instrbuffermode { … }; enum a3xx_threadsize { … }; enum a3xx_color_swap { … }; enum a3xx_rb_blend_opcode { … }; enum a4xx_tess_spacing { … }; enum a5xx_address_mode { … }; enum a5xx_line_mode { … }; enum a6xx_tex_prefetch_cmd { … }; #define REG_AXXX_CP_RB_BASE … #define REG_AXXX_CP_RB_CNTL … #define AXXX_CP_RB_CNTL_BUFSZ__MASK … #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT … static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) { … } #define AXXX_CP_RB_CNTL_BLKSZ__MASK … #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT … static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) { … } #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK … #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT … static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) { … } #define AXXX_CP_RB_CNTL_POLL_EN … #define AXXX_CP_RB_CNTL_NO_UPDATE … #define AXXX_CP_RB_CNTL_RPTR_WR_EN … #define REG_AXXX_CP_RB_RPTR_ADDR … #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK … #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT … static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) { … } #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK … #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT … static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) { … } #define REG_AXXX_CP_RB_RPTR … #define REG_AXXX_CP_RB_WPTR … #define REG_AXXX_CP_RB_WPTR_DELAY … #define REG_AXXX_CP_RB_RPTR_WR … #define REG_AXXX_CP_RB_WPTR_BASE … #define REG_AXXX_CP_QUEUE_THRESHOLDS … #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK … #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT … static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) { … } #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK … #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT … static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) { … } #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK … #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT … static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) { … } #define REG_AXXX_CP_MEQ_THRESHOLDS … #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK … #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT … static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) { … } #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK … #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT … static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) { … } #define REG_AXXX_CP_CSQ_AVAIL … #define AXXX_CP_CSQ_AVAIL_RING__MASK … #define AXXX_CP_CSQ_AVAIL_RING__SHIFT … static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) { … } #define AXXX_CP_CSQ_AVAIL_IB1__MASK … #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT … static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) { … } #define AXXX_CP_CSQ_AVAIL_IB2__MASK … #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT … static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) { … } #define REG_AXXX_CP_STQ_AVAIL … #define AXXX_CP_STQ_AVAIL_ST__MASK … #define AXXX_CP_STQ_AVAIL_ST__SHIFT … static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) { … } #define REG_AXXX_CP_MEQ_AVAIL … #define AXXX_CP_MEQ_AVAIL_MEQ__MASK … #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT … static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) { … } #define REG_AXXX_SCRATCH_UMSK … #define AXXX_SCRATCH_UMSK_UMSK__MASK … #define AXXX_SCRATCH_UMSK_UMSK__SHIFT … static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) { … } #define AXXX_SCRATCH_UMSK_SWAP__MASK … #define AXXX_SCRATCH_UMSK_SWAP__SHIFT … static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) { … } #define REG_AXXX_SCRATCH_ADDR … #define REG_AXXX_CP_ME_RDADDR … #define REG_AXXX_CP_STATE_DEBUG_INDEX … #define REG_AXXX_CP_STATE_DEBUG_DATA … #define REG_AXXX_CP_INT_CNTL … #define AXXX_CP_INT_CNTL_SW_INT_MASK … #define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK … #define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK … #define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK … #define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK … #define AXXX_CP_INT_CNTL_IB_ERROR_MASK … #define AXXX_CP_INT_CNTL_IB2_INT_MASK … #define AXXX_CP_INT_CNTL_IB1_INT_MASK … #define AXXX_CP_INT_CNTL_RB_INT_MASK … #define REG_AXXX_CP_INT_STATUS … #define REG_AXXX_CP_INT_ACK … #define REG_AXXX_CP_ME_CNTL … #define AXXX_CP_ME_CNTL_BUSY … #define AXXX_CP_ME_CNTL_HALT … #define REG_AXXX_CP_ME_STATUS … #define REG_AXXX_CP_ME_RAM_WADDR … #define REG_AXXX_CP_ME_RAM_RADDR … #define REG_AXXX_CP_ME_RAM_DATA … #define REG_AXXX_CP_DEBUG … #define AXXX_CP_DEBUG_PREDICATE_DISABLE … #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE … #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE … #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS … #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE … #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE … #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL … #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE … #define REG_AXXX_CP_CSQ_RB_STAT … #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK … #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT … static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) { … } #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK … #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT … static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) { … } #define REG_AXXX_CP_CSQ_IB1_STAT … #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK … #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT … static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) { … } #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK … #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT … static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) { … } #define REG_AXXX_CP_CSQ_IB2_STAT … #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK … #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT … static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) { … } #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK … #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT … static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) { … } #define REG_AXXX_CP_NON_PREFETCH_CNTRS … #define REG_AXXX_CP_STQ_ST_STAT … #define REG_AXXX_CP_ST_BASE … #define REG_AXXX_CP_ST_BUFSZ … #define REG_AXXX_CP_MEQ_STAT … #define REG_AXXX_CP_MIU_TAG_STAT … #define REG_AXXX_CP_BIN_MASK_LO … #define REG_AXXX_CP_BIN_MASK_HI … #define REG_AXXX_CP_BIN_SELECT_LO … #define REG_AXXX_CP_BIN_SELECT_HI … #define REG_AXXX_CP_IB1_BASE … #define REG_AXXX_CP_IB1_BUFSZ … #define REG_AXXX_CP_IB2_BASE … #define REG_AXXX_CP_IB2_BUFSZ … #define REG_AXXX_CP_STAT … #define AXXX_CP_STAT_CP_BUSY … #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY … #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY … #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY … #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY … #define AXXX_CP_STAT_ME_BUSY … #define AXXX_CP_STAT_MIU_WR_C_BUSY … #define AXXX_CP_STAT_CP_3D_BUSY … #define AXXX_CP_STAT_CP_NRT_BUSY … #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY … #define AXXX_CP_STAT_RCIU_ME_BUSY … #define AXXX_CP_STAT_RCIU_PFP_BUSY … #define AXXX_CP_STAT_MEQ_RING_BUSY … #define AXXX_CP_STAT_PFP_BUSY … #define AXXX_CP_STAT_ST_QUEUE_BUSY … #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY … #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY … #define AXXX_CP_STAT_RING_QUEUE_BUSY … #define AXXX_CP_STAT_CSF_BUSY … #define AXXX_CP_STAT_CSF_ST_BUSY … #define AXXX_CP_STAT_EVENT_BUSY … #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY … #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY … #define AXXX_CP_STAT_CSF_RING_BUSY … #define AXXX_CP_STAT_RCIU_BUSY … #define AXXX_CP_STAT_RBIU_BUSY … #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY … #define AXXX_CP_STAT_MIU_RD_REQ_BUSY … #define AXXX_CP_STAT_MIU_WR_BUSY … #define REG_AXXX_CP_SCRATCH_REG0 … #define REG_AXXX_CP_SCRATCH_REG1 … #define REG_AXXX_CP_SCRATCH_REG2 … #define REG_AXXX_CP_SCRATCH_REG3 … #define REG_AXXX_CP_SCRATCH_REG4 … #define REG_AXXX_CP_SCRATCH_REG5 … #define REG_AXXX_CP_SCRATCH_REG6 … #define REG_AXXX_CP_SCRATCH_REG7 … #define REG_AXXX_CP_ME_VS_EVENT_SRC … #define REG_AXXX_CP_ME_VS_EVENT_ADDR … #define REG_AXXX_CP_ME_VS_EVENT_DATA … #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM … #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM … #define REG_AXXX_CP_ME_PS_EVENT_SRC … #define REG_AXXX_CP_ME_PS_EVENT_ADDR … #define REG_AXXX_CP_ME_PS_EVENT_DATA … #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM … #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM … #define REG_AXXX_CP_ME_CF_EVENT_SRC … #define REG_AXXX_CP_ME_CF_EVENT_ADDR … #define REG_AXXX_CP_ME_CF_EVENT_DATA … #define REG_AXXX_CP_ME_NRT_ADDR … #define REG_AXXX_CP_ME_NRT_DATA … #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC … #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR … #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA … #ifdef __cplusplus #endif #endif /* ADRENO_COMMON_XML */
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