#ifndef ADRENO_PM4_XML #define ADRENO_PM4_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml ( 85907 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum vgt_event_type { … }; enum pc_di_primtype { … }; enum pc_di_src_sel { … }; enum pc_di_face_cull_sel { … }; enum pc_di_index_size { … }; enum pc_di_vis_cull_mode { … }; enum adreno_pm4_packet_type { … }; enum adreno_pm4_type3_packets { … }; enum adreno_state_block { … }; enum adreno_state_type { … }; enum adreno_state_src { … }; enum a4xx_state_block { … }; enum a4xx_state_type { … }; enum a4xx_state_src { … }; enum a6xx_state_block { … }; enum a6xx_state_type { … }; enum a6xx_state_src { … }; enum a4xx_index_size { … }; enum a6xx_patch_type { … }; enum a6xx_draw_indirect_opcode { … }; enum cp_draw_pred_src { … }; enum cp_draw_pred_test { … }; enum cp_cond_function { … }; enum poll_memory_type { … }; enum render_mode_cmd { … }; enum event_write_src { … }; enum event_write_dst { … }; enum cp_blit_cmd { … }; enum a6xx_marker { … }; enum pseudo_reg { … }; enum source_type { … }; enum compare_mode { … }; enum ctxswitch_ib { … }; enum reg_tracker { … }; enum ts_wait_value_src { … }; enum ts_wait_type { … }; enum pipe_count_op { … }; enum timestamp_op { … }; enum cp_thread { … }; #define REG_CP_LOAD_STATE_0 … #define CP_LOAD_STATE_0_DST_OFF__MASK … #define CP_LOAD_STATE_0_DST_OFF__SHIFT … static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) { … } #define CP_LOAD_STATE_0_STATE_SRC__MASK … #define CP_LOAD_STATE_0_STATE_SRC__SHIFT … static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) { … } #define CP_LOAD_STATE_0_STATE_BLOCK__MASK … #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT … static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) { … } #define CP_LOAD_STATE_0_NUM_UNIT__MASK … #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT … static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) { … } #define REG_CP_LOAD_STATE_1 … #define CP_LOAD_STATE_1_STATE_TYPE__MASK … #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT … static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) { … } #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK … #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT … static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) { … } #define REG_CP_LOAD_STATE4_0 … #define CP_LOAD_STATE4_0_DST_OFF__MASK … #define CP_LOAD_STATE4_0_DST_OFF__SHIFT … static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) { … } #define CP_LOAD_STATE4_0_STATE_SRC__MASK … #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT … static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) { … } #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK … #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT … static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) { … } #define CP_LOAD_STATE4_0_NUM_UNIT__MASK … #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT … static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) { … } #define REG_CP_LOAD_STATE4_1 … #define CP_LOAD_STATE4_1_STATE_TYPE__MASK … #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT … static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) { … } #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK … #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT … static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) { … } #define REG_CP_LOAD_STATE4_2 … #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK … #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT … static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) { … } #define REG_CP_LOAD_STATE6_0 … #define CP_LOAD_STATE6_0_DST_OFF__MASK … #define CP_LOAD_STATE6_0_DST_OFF__SHIFT … static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) { … } #define CP_LOAD_STATE6_0_STATE_TYPE__MASK … #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT … static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) { … } #define CP_LOAD_STATE6_0_STATE_SRC__MASK … #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT … static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) { … } #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK … #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT … static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) { … } #define CP_LOAD_STATE6_0_NUM_UNIT__MASK … #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT … static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) { … } #define REG_CP_LOAD_STATE6_1 … #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK … #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT … static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) { … } #define REG_CP_LOAD_STATE6_2 … #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK … #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT … static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) { … } #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR … #define REG_CP_DRAW_INDX_0 … #define CP_DRAW_INDX_0_VIZ_QUERY__MASK … #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT … static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) { … } #define REG_CP_DRAW_INDX_1 … #define CP_DRAW_INDX_1_PRIM_TYPE__MASK … #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT … static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) { … } #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK … #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT … static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define CP_DRAW_INDX_1_VIS_CULL__MASK … #define CP_DRAW_INDX_1_VIS_CULL__SHIFT … static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define CP_DRAW_INDX_1_INDEX_SIZE__MASK … #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT … static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) { … } #define CP_DRAW_INDX_1_NOT_EOP … #define CP_DRAW_INDX_1_SMALL_INDEX … #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE … #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK … #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT … static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) { … } #define REG_CP_DRAW_INDX_2 … #define CP_DRAW_INDX_2_NUM_INDICES__MASK … #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT … static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) { … } #define REG_CP_DRAW_INDX_3 … #define CP_DRAW_INDX_3_INDX_BASE__MASK … #define CP_DRAW_INDX_3_INDX_BASE__SHIFT … static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) { … } #define REG_CP_DRAW_INDX_4 … #define CP_DRAW_INDX_4_INDX_SIZE__MASK … #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT … static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) { … } #define REG_CP_DRAW_INDX_2_0 … #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK … #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT … static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) { … } #define REG_CP_DRAW_INDX_2_1 … #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK … #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT … static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) { … } #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK … #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT … static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define CP_DRAW_INDX_2_1_VIS_CULL__MASK … #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT … static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK … #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT … static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) { … } #define CP_DRAW_INDX_2_1_NOT_EOP … #define CP_DRAW_INDX_2_1_SMALL_INDEX … #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE … #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK … #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT … static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) { … } #define REG_CP_DRAW_INDX_2_2 … #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK … #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT … static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) { … } #define REG_CP_DRAW_INDX_OFFSET_0 … #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK … #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) { … } #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK … #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK … #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK … #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) { … } #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK … #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) { … } #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE … #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE … #define REG_CP_DRAW_INDX_OFFSET_1 … #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK … #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) { … } #define REG_CP_DRAW_INDX_OFFSET_2 … #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK … #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) { … } #define REG_CP_DRAW_INDX_OFFSET_3 … #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK … #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_OFFSET_4 … #define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK … #define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_OFFSET_5 … #define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK … #define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE … #define REG_A5XX_CP_DRAW_INDX_OFFSET_6 … #define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK … #define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) { … } #define REG_CP_DRAW_INDX_OFFSET_4 … #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK … #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint64_t val) { … } #define REG_CP_DRAW_INDX_OFFSET_5 … #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK … #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT … static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) { … } #define REG_A4XX_CP_DRAW_INDIRECT_0 … #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK … #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) { … } #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK … #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK … #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK … #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) { … } #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK … #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) { … } #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE … #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE … #define REG_A4XX_CP_DRAW_INDIRECT_1 … #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK … #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDIRECT_1 … #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK … #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDIRECT_2 … #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK … #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT … #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 … #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) { … } #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) { … } #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) { … } #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE … #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE … #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 … #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) { … } #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 … #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) { … } #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 … #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK … #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT … static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 … #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK … #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 … #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK … #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE … #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 … #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK … #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 … #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK … #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 … #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK … #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT … static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) { … } #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT … #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 … #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK … #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT … static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val) { … } #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK … #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT … static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK … #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT … static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK … #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT … static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val) { … } #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK … #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT … static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val) { … } #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE … #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE … #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 … #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK … #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT … static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val) { … } #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK … #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT … static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) { … } #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT … #define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT … #define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE … #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX … #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES … #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT … #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE … #define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT … #define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT … #define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE … #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX … #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES … #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT … #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT … #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE … #define REG_CP_DRAW_AUTO_0 … #define CP_DRAW_AUTO_0_PRIM_TYPE__MASK … #define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT … static inline uint32_t CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val) { … } #define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK … #define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT … static inline uint32_t CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define CP_DRAW_AUTO_0_VIS_CULL__MASK … #define CP_DRAW_AUTO_0_VIS_CULL__SHIFT … static inline uint32_t CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define CP_DRAW_AUTO_0_INDEX_SIZE__MASK … #define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT … static inline uint32_t CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val) { … } #define CP_DRAW_AUTO_0_PATCH_TYPE__MASK … #define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT … static inline uint32_t CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val) { … } #define CP_DRAW_AUTO_0_GS_ENABLE … #define CP_DRAW_AUTO_0_TESS_ENABLE … #define REG_CP_DRAW_AUTO_1 … #define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK … #define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT … static inline uint32_t CP_DRAW_AUTO_1_NUM_INSTANCES(uint32_t val) { … } #define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE … #define REG_CP_DRAW_AUTO_4 … #define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK … #define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT … static inline uint32_t CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(uint32_t val) { … } #define REG_CP_DRAW_AUTO_5 … #define CP_DRAW_AUTO_5_STRIDE__MASK … #define CP_DRAW_AUTO_5_STRIDE__SHIFT … static inline uint32_t CP_DRAW_AUTO_5_STRIDE(uint32_t val) { … } #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 … #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE … #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 … #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE … #define REG_CP_DRAW_PRED_SET_0 … #define CP_DRAW_PRED_SET_0_SRC__MASK … #define CP_DRAW_PRED_SET_0_SRC__SHIFT … static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val) { … } #define CP_DRAW_PRED_SET_0_TEST__MASK … #define CP_DRAW_PRED_SET_0_TEST__SHIFT … static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) { … } #define REG_CP_DRAW_PRED_SET_MEM_ADDR … #define REG_CP_SET_DRAW_STATE_(i0) … static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { … } #define CP_SET_DRAW_STATE__0_COUNT__MASK … #define CP_SET_DRAW_STATE__0_COUNT__SHIFT … static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) { … } #define CP_SET_DRAW_STATE__0_DIRTY … #define CP_SET_DRAW_STATE__0_DISABLE … #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS … #define CP_SET_DRAW_STATE__0_LOAD_IMMED … #define CP_SET_DRAW_STATE__0_BINNING … #define CP_SET_DRAW_STATE__0_GMEM … #define CP_SET_DRAW_STATE__0_SYSMEM … #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK … #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT … static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) { … } static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { … } #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK … #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT … static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) { … } static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { … } #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK … #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT … static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) { … } #define REG_CP_SET_BIN_0 … #define REG_CP_SET_BIN_1 … #define CP_SET_BIN_1_X1__MASK … #define CP_SET_BIN_1_X1__SHIFT … static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) { … } #define CP_SET_BIN_1_Y1__MASK … #define CP_SET_BIN_1_Y1__SHIFT … static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) { … } #define REG_CP_SET_BIN_2 … #define CP_SET_BIN_2_X2__MASK … #define CP_SET_BIN_2_X2__SHIFT … static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) { … } #define CP_SET_BIN_2_Y2__MASK … #define CP_SET_BIN_2_Y2__SHIFT … static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) { … } #define REG_CP_SET_BIN_DATA_0 … #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK … #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT … static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) { … } #define REG_CP_SET_BIN_DATA_1 … #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK … #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT … static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_0 … #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK … #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) { … } #define CP_SET_BIN_DATA5_0_VSC_N__MASK … #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_1 … #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK … #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_2 … #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK … #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_3 … #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK … #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_4 … #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK … #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_5 … #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK … #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_6 … #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK … #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_7 … #define REG_CP_SET_BIN_DATA5_9 … #define REG_CP_SET_BIN_DATA5_OFFSET_0 … #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK … #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val) { … } #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK … #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_OFFSET_1 … #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK … #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_OFFSET_2 … #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK … #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val) { … } #define REG_CP_SET_BIN_DATA5_OFFSET_3 … #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK … #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT … static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val) { … } #define REG_CP_REG_RMW_0 … #define CP_REG_RMW_0_DST_REG__MASK … #define CP_REG_RMW_0_DST_REG__SHIFT … static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val) { … } #define CP_REG_RMW_0_ROTATE__MASK … #define CP_REG_RMW_0_ROTATE__SHIFT … static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val) { … } #define CP_REG_RMW_0_SRC1_ADD … #define CP_REG_RMW_0_SRC1_IS_REG … #define CP_REG_RMW_0_SRC0_IS_REG … #define REG_CP_REG_RMW_1 … #define CP_REG_RMW_1_SRC0__MASK … #define CP_REG_RMW_1_SRC0__SHIFT … static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val) { … } #define REG_CP_REG_RMW_2 … #define CP_REG_RMW_2_SRC1__MASK … #define CP_REG_RMW_2_SRC1__SHIFT … static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val) { … } #define REG_CP_REG_TO_MEM_0 … #define CP_REG_TO_MEM_0_REG__MASK … #define CP_REG_TO_MEM_0_REG__SHIFT … static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) { … } #define CP_REG_TO_MEM_0_CNT__MASK … #define CP_REG_TO_MEM_0_CNT__SHIFT … static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) { … } #define CP_REG_TO_MEM_0_64B … #define CP_REG_TO_MEM_0_ACCUMULATE … #define REG_CP_REG_TO_MEM_1 … #define CP_REG_TO_MEM_1_DEST__MASK … #define CP_REG_TO_MEM_1_DEST__SHIFT … static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) { … } #define REG_CP_REG_TO_MEM_2 … #define CP_REG_TO_MEM_2_DEST_HI__MASK … #define CP_REG_TO_MEM_2_DEST_HI__SHIFT … static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) { … } #define REG_CP_REG_TO_MEM_OFFSET_REG_0 … #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK … #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val) { … } #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK … #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val) { … } #define CP_REG_TO_MEM_OFFSET_REG_0_64B … #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE … #define REG_CP_REG_TO_MEM_OFFSET_REG_1 … #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK … #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val) { … } #define REG_CP_REG_TO_MEM_OFFSET_REG_2 … #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK … #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val) { … } #define REG_CP_REG_TO_MEM_OFFSET_REG_3 … #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK … #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val) { … } #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH … #define REG_CP_REG_TO_MEM_OFFSET_MEM_0 … #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK … #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val) { … } #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK … #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val) { … } #define CP_REG_TO_MEM_OFFSET_MEM_0_64B … #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE … #define REG_CP_REG_TO_MEM_OFFSET_MEM_1 … #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK … #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val) { … } #define REG_CP_REG_TO_MEM_OFFSET_MEM_2 … #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK … #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val) { … } #define REG_CP_REG_TO_MEM_OFFSET_MEM_3 … #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK … #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val) { … } #define REG_CP_REG_TO_MEM_OFFSET_MEM_4 … #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK … #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT … static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val) { … } #define REG_CP_MEM_TO_REG_0 … #define CP_MEM_TO_REG_0_REG__MASK … #define CP_MEM_TO_REG_0_REG__SHIFT … static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) { … } #define CP_MEM_TO_REG_0_CNT__MASK … #define CP_MEM_TO_REG_0_CNT__SHIFT … static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) { … } #define CP_MEM_TO_REG_0_SHIFT_BY_2 … #define CP_MEM_TO_REG_0_UNK31 … #define REG_CP_MEM_TO_REG_1 … #define CP_MEM_TO_REG_1_SRC__MASK … #define CP_MEM_TO_REG_1_SRC__SHIFT … static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) { … } #define REG_CP_MEM_TO_REG_2 … #define CP_MEM_TO_REG_2_SRC_HI__MASK … #define CP_MEM_TO_REG_2_SRC_HI__SHIFT … static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) { … } #define REG_CP_MEM_TO_MEM_0 … #define CP_MEM_TO_MEM_0_NEG_A … #define CP_MEM_TO_MEM_0_NEG_B … #define CP_MEM_TO_MEM_0_NEG_C … #define CP_MEM_TO_MEM_0_DOUBLE … #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES … #define CP_MEM_TO_MEM_0_UNK31 … #define REG_CP_MEMCPY_0 … #define CP_MEMCPY_0_DWORDS__MASK … #define CP_MEMCPY_0_DWORDS__SHIFT … static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val) { … } #define REG_CP_MEMCPY_1 … #define CP_MEMCPY_1_SRC_LO__MASK … #define CP_MEMCPY_1_SRC_LO__SHIFT … static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val) { … } #define REG_CP_MEMCPY_2 … #define CP_MEMCPY_2_SRC_HI__MASK … #define CP_MEMCPY_2_SRC_HI__SHIFT … static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val) { … } #define REG_CP_MEMCPY_3 … #define CP_MEMCPY_3_DST_LO__MASK … #define CP_MEMCPY_3_DST_LO__SHIFT … static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val) { … } #define REG_CP_MEMCPY_4 … #define CP_MEMCPY_4_DST_HI__MASK … #define CP_MEMCPY_4_DST_HI__SHIFT … static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val) { … } #define REG_CP_REG_TO_SCRATCH_0 … #define CP_REG_TO_SCRATCH_0_REG__MASK … #define CP_REG_TO_SCRATCH_0_REG__SHIFT … static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val) { … } #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK … #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT … static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val) { … } #define CP_REG_TO_SCRATCH_0_CNT__MASK … #define CP_REG_TO_SCRATCH_0_CNT__SHIFT … static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val) { … } #define REG_CP_SCRATCH_TO_REG_0 … #define CP_SCRATCH_TO_REG_0_REG__MASK … #define CP_SCRATCH_TO_REG_0_REG__SHIFT … static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val) { … } #define CP_SCRATCH_TO_REG_0_UNK18 … #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK … #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT … static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val) { … } #define CP_SCRATCH_TO_REG_0_CNT__MASK … #define CP_SCRATCH_TO_REG_0_CNT__SHIFT … static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val) { … } #define REG_CP_SCRATCH_WRITE_0 … #define CP_SCRATCH_WRITE_0_SCRATCH__MASK … #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT … static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val) { … } #define REG_CP_MEM_WRITE_0 … #define CP_MEM_WRITE_0_ADDR_LO__MASK … #define CP_MEM_WRITE_0_ADDR_LO__SHIFT … static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val) { … } #define REG_CP_MEM_WRITE_1 … #define CP_MEM_WRITE_1_ADDR_HI__MASK … #define CP_MEM_WRITE_1_ADDR_HI__SHIFT … static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val) { … } #define REG_CP_COND_WRITE_0 … #define CP_COND_WRITE_0_FUNCTION__MASK … #define CP_COND_WRITE_0_FUNCTION__SHIFT … static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) { … } #define CP_COND_WRITE_0_POLL_MEMORY … #define CP_COND_WRITE_0_WRITE_MEMORY … #define REG_CP_COND_WRITE_1 … #define CP_COND_WRITE_1_POLL_ADDR__MASK … #define CP_COND_WRITE_1_POLL_ADDR__SHIFT … static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) { … } #define REG_CP_COND_WRITE_2 … #define CP_COND_WRITE_2_REF__MASK … #define CP_COND_WRITE_2_REF__SHIFT … static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) { … } #define REG_CP_COND_WRITE_3 … #define CP_COND_WRITE_3_MASK__MASK … #define CP_COND_WRITE_3_MASK__SHIFT … static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) { … } #define REG_CP_COND_WRITE_4 … #define CP_COND_WRITE_4_WRITE_ADDR__MASK … #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT … static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) { … } #define REG_CP_COND_WRITE_5 … #define CP_COND_WRITE_5_WRITE_DATA__MASK … #define CP_COND_WRITE_5_WRITE_DATA__SHIFT … static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) { … } #define REG_CP_COND_WRITE5_0 … #define CP_COND_WRITE5_0_FUNCTION__MASK … #define CP_COND_WRITE5_0_FUNCTION__SHIFT … static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) { … } #define CP_COND_WRITE5_0_SIGNED_COMPARE … #define CP_COND_WRITE5_0_POLL__MASK … #define CP_COND_WRITE5_0_POLL__SHIFT … static inline uint32_t CP_COND_WRITE5_0_POLL(enum poll_memory_type val) { … } #define CP_COND_WRITE5_0_WRITE_MEMORY … #define REG_CP_COND_WRITE5_1 … #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK … #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT … static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) { … } #define REG_CP_COND_WRITE5_2 … #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK … #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT … static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) { … } #define REG_CP_COND_WRITE5_3 … #define CP_COND_WRITE5_3_REF__MASK … #define CP_COND_WRITE5_3_REF__SHIFT … static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) { … } #define REG_CP_COND_WRITE5_4 … #define CP_COND_WRITE5_4_MASK__MASK … #define CP_COND_WRITE5_4_MASK__SHIFT … static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) { … } #define REG_CP_COND_WRITE5_5 … #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK … #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT … static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) { … } #define REG_CP_COND_WRITE5_6 … #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK … #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT … static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) { … } #define REG_CP_COND_WRITE5_7 … #define CP_COND_WRITE5_7_WRITE_DATA__MASK … #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT … static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) { … } #define REG_CP_WAIT_MEM_GTE_0 … #define CP_WAIT_MEM_GTE_0_RESERVED__MASK … #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT … static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val) { … } #define REG_CP_WAIT_MEM_GTE_1 … #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK … #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT … static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val) { … } #define REG_CP_WAIT_MEM_GTE_2 … #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK … #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT … static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val) { … } #define REG_CP_WAIT_MEM_GTE_3 … #define CP_WAIT_MEM_GTE_3_REF__MASK … #define CP_WAIT_MEM_GTE_3_REF__SHIFT … static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val) { … } #define REG_CP_WAIT_REG_MEM_0 … #define CP_WAIT_REG_MEM_0_FUNCTION__MASK … #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT … static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) { … } #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE … #define CP_WAIT_REG_MEM_0_POLL__MASK … #define CP_WAIT_REG_MEM_0_POLL__SHIFT … static inline uint32_t CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val) { … } #define CP_WAIT_REG_MEM_0_WRITE_MEMORY … #define REG_CP_WAIT_REG_MEM_1 … #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK … #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT … static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val) { … } #define REG_CP_WAIT_REG_MEM_2 … #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK … #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT … static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val) { … } #define REG_CP_WAIT_REG_MEM_3 … #define CP_WAIT_REG_MEM_3_REF__MASK … #define CP_WAIT_REG_MEM_3_REF__SHIFT … static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val) { … } #define REG_CP_WAIT_REG_MEM_4 … #define CP_WAIT_REG_MEM_4_MASK__MASK … #define CP_WAIT_REG_MEM_4_MASK__SHIFT … static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val) { … } #define REG_CP_WAIT_REG_MEM_5 … #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK … #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT … static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val) { … } #define REG_CP_WAIT_TWO_REGS_0 … #define CP_WAIT_TWO_REGS_0_REG0__MASK … #define CP_WAIT_TWO_REGS_0_REG0__SHIFT … static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val) { … } #define REG_CP_WAIT_TWO_REGS_1 … #define CP_WAIT_TWO_REGS_1_REG1__MASK … #define CP_WAIT_TWO_REGS_1_REG1__SHIFT … static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val) { … } #define REG_CP_WAIT_TWO_REGS_2 … #define CP_WAIT_TWO_REGS_2_REF__MASK … #define CP_WAIT_TWO_REGS_2_REF__SHIFT … static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val) { … } #define REG_CP_DISPATCH_COMPUTE_0 … #define REG_CP_DISPATCH_COMPUTE_1 … #define CP_DISPATCH_COMPUTE_1_X__MASK … #define CP_DISPATCH_COMPUTE_1_X__SHIFT … static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) { … } #define REG_CP_DISPATCH_COMPUTE_2 … #define CP_DISPATCH_COMPUTE_2_Y__MASK … #define CP_DISPATCH_COMPUTE_2_Y__SHIFT … static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) { … } #define REG_CP_DISPATCH_COMPUTE_3 … #define CP_DISPATCH_COMPUTE_3_Z__MASK … #define CP_DISPATCH_COMPUTE_3_Z__SHIFT … static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) { … } #define REG_CP_SET_RENDER_MODE_0 … #define CP_SET_RENDER_MODE_0_MODE__MASK … #define CP_SET_RENDER_MODE_0_MODE__SHIFT … static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) { … } #define REG_CP_SET_RENDER_MODE_1 … #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK … #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT … static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) { … } #define REG_CP_SET_RENDER_MODE_2 … #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK … #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT … static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) { … } #define REG_CP_SET_RENDER_MODE_3 … #define CP_SET_RENDER_MODE_3_VSC_ENABLE … #define CP_SET_RENDER_MODE_3_GMEM_ENABLE … #define REG_CP_SET_RENDER_MODE_4 … #define REG_CP_SET_RENDER_MODE_5 … #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK … #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT … static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) { … } #define REG_CP_SET_RENDER_MODE_6 … #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK … #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT … static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) { … } #define REG_CP_SET_RENDER_MODE_7 … #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK … #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT … static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) { … } #define REG_CP_COMPUTE_CHECKPOINT_0 … #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK … #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT … static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) { … } #define REG_CP_COMPUTE_CHECKPOINT_1 … #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK … #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT … static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) { … } #define REG_CP_COMPUTE_CHECKPOINT_2 … #define REG_CP_COMPUTE_CHECKPOINT_3 … #define REG_CP_COMPUTE_CHECKPOINT_4 … #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK … #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT … static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val) { … } #define REG_CP_COMPUTE_CHECKPOINT_5 … #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK … #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT … static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) { … } #define REG_CP_COMPUTE_CHECKPOINT_6 … #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK … #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT … static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) { … } #define REG_CP_COMPUTE_CHECKPOINT_7 … #define REG_CP_PERFCOUNTER_ACTION_0 … #define REG_CP_PERFCOUNTER_ACTION_1 … #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK … #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT … static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) { … } #define REG_CP_PERFCOUNTER_ACTION_2 … #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK … #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT … static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) { … } #define REG_CP_EVENT_WRITE_0 … #define CP_EVENT_WRITE_0_EVENT__MASK … #define CP_EVENT_WRITE_0_EVENT__SHIFT … static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) { … } #define CP_EVENT_WRITE_0_TIMESTAMP … #define CP_EVENT_WRITE_0_IRQ … #define REG_CP_EVENT_WRITE_1 … #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK … #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT … static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) { … } #define REG_CP_EVENT_WRITE_2 … #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK … #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT … static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) { … } #define REG_CP_EVENT_WRITE_3 … #define REG_CP_EVENT_WRITE7_0 … #define CP_EVENT_WRITE7_0_EVENT__MASK … #define CP_EVENT_WRITE7_0_EVENT__SHIFT … static inline uint32_t CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val) { … } #define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT … #define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET … #define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT_DIFF … #define CP_EVENT_WRITE7_0_INC_BV_COUNT … #define CP_EVENT_WRITE7_0_INC_BR_COUNT … #define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE … #define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE … #define CP_EVENT_WRITE7_0_WRITE_SRC__MASK … #define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT … static inline uint32_t CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val) { … } #define CP_EVENT_WRITE7_0_WRITE_DST__MASK … #define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT … static inline uint32_t CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val) { … } #define CP_EVENT_WRITE7_0_WRITE_ENABLED … #define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 … #define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK … #define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT … static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(uint32_t val) { … } #define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 … #define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK … #define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT … static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(uint32_t val) { … } #define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 … #define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK … #define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT … static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) { … } #define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 … #define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK … #define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT … static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) { … } #define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 … #define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK … #define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT … static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(uint32_t val) { … } #define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 … #define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK … #define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT … static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) { … } #define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 … #define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK … #define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT … static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) { … } #define REG_CP_BLIT_0 … #define CP_BLIT_0_OP__MASK … #define CP_BLIT_0_OP__SHIFT … static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) { … } #define REG_CP_BLIT_1 … #define CP_BLIT_1_SRC_X1__MASK … #define CP_BLIT_1_SRC_X1__SHIFT … static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) { … } #define CP_BLIT_1_SRC_Y1__MASK … #define CP_BLIT_1_SRC_Y1__SHIFT … static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) { … } #define REG_CP_BLIT_2 … #define CP_BLIT_2_SRC_X2__MASK … #define CP_BLIT_2_SRC_X2__SHIFT … static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) { … } #define CP_BLIT_2_SRC_Y2__MASK … #define CP_BLIT_2_SRC_Y2__SHIFT … static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) { … } #define REG_CP_BLIT_3 … #define CP_BLIT_3_DST_X1__MASK … #define CP_BLIT_3_DST_X1__SHIFT … static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) { … } #define CP_BLIT_3_DST_Y1__MASK … #define CP_BLIT_3_DST_Y1__SHIFT … static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) { … } #define REG_CP_BLIT_4 … #define CP_BLIT_4_DST_X2__MASK … #define CP_BLIT_4_DST_X2__SHIFT … static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) { … } #define CP_BLIT_4_DST_Y2__MASK … #define CP_BLIT_4_DST_Y2__SHIFT … static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) { … } #define REG_CP_EXEC_CS_0 … #define REG_CP_EXEC_CS_1 … #define CP_EXEC_CS_1_NGROUPS_X__MASK … #define CP_EXEC_CS_1_NGROUPS_X__SHIFT … static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) { … } #define REG_CP_EXEC_CS_2 … #define CP_EXEC_CS_2_NGROUPS_Y__MASK … #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT … static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) { … } #define REG_CP_EXEC_CS_3 … #define CP_EXEC_CS_3_NGROUPS_Z__MASK … #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT … static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) { … } #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 … #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 … #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK … #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT … static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) { … } #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 … #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK … #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT … static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) { … } #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK … #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT … static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) { … } #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK … #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT … static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) { … } #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 … #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK … #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT … static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) { … } #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 … #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK … #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT … static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) { … } #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 … #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK … #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT … static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) { … } #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK … #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT … static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) { … } #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK … #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT … static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) { … } #define REG_A6XX_CP_SET_MARKER_0 … #define A6XX_CP_SET_MARKER_0_MODE__MASK … #define A6XX_CP_SET_MARKER_0_MODE__SHIFT … static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val) { … } #define A6XX_CP_SET_MARKER_0_MARKER__MASK … #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT … static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val) { … } #define REG_A6XX_CP_SET_PSEUDO_REG_(i0) … static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { … } #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK … #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT … static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) { … } static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { … } #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK … #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT … static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) { … } static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { … } #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK … #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT … static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) { … } #define REG_A6XX_CP_REG_TEST_0 … #define A6XX_CP_REG_TEST_0_REG__MASK … #define A6XX_CP_REG_TEST_0_REG__SHIFT … static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val) { … } #define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK … #define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT … static inline uint32_t A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(uint32_t val) { … } #define A6XX_CP_REG_TEST_0_SOURCE__MASK … #define A6XX_CP_REG_TEST_0_SOURCE__SHIFT … static inline uint32_t A6XX_CP_REG_TEST_0_SOURCE(enum source_type val) { … } #define A6XX_CP_REG_TEST_0_BIT__MASK … #define A6XX_CP_REG_TEST_0_BIT__SHIFT … static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val) { … } #define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME … #define A6XX_CP_REG_TEST_0_PRED_BIT__MASK … #define A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT … static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val) { … } #define A6XX_CP_REG_TEST_0_PRED_UPDATE … #define REG_A6XX_CP_REG_TEST_PRED_MASK … #define REG_A6XX_CP_REG_TEST_PRED_VAL … #define REG_CP_COND_REG_EXEC_0 … #define CP_COND_REG_EXEC_0_REG0__MASK … #define CP_COND_REG_EXEC_0_REG0__SHIFT … static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val) { … } #define CP_COND_REG_EXEC_0_PRED_BIT__MASK … #define CP_COND_REG_EXEC_0_PRED_BIT__SHIFT … static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val) { … } #define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME … #define CP_COND_REG_EXEC_0_ONCHIP_MEM … #define CP_COND_REG_EXEC_0_BINNING … #define CP_COND_REG_EXEC_0_GMEM … #define CP_COND_REG_EXEC_0_SYSMEM … #define CP_COND_REG_EXEC_0_BV … #define CP_COND_REG_EXEC_0_BR … #define CP_COND_REG_EXEC_0_LPAC … #define CP_COND_REG_EXEC_0_MODE__MASK … #define CP_COND_REG_EXEC_0_MODE__SHIFT … static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) { … } #define REG_PRED_TEST_CP_COND_REG_EXEC_1 … #define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK … #define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT … static inline uint32_t PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) { … } #define REG_REG_COMPARE_CP_COND_REG_EXEC_1 … #define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK … #define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT … static inline uint32_t REG_COMPARE_CP_COND_REG_EXEC_1_REG1(uint32_t val) { … } #define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM … #define REG_RENDER_MODE_CP_COND_REG_EXEC_1 … #define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK … #define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT … static inline uint32_t RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) { … } #define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 … #define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK … #define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT … static inline uint32_t REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(uint32_t val) { … } #define REG_THREAD_MODE_CP_COND_REG_EXEC_1 … #define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK … #define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT … static inline uint32_t THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) { … } #define REG_CP_COND_REG_EXEC_2 … #define CP_COND_REG_EXEC_2_DWORDS__MASK … #define CP_COND_REG_EXEC_2_DWORDS__SHIFT … static inline uint32_t CP_COND_REG_EXEC_2_DWORDS(uint32_t val) { … } #define REG_CP_COND_EXEC_0 … #define CP_COND_EXEC_0_ADDR0_LO__MASK … #define CP_COND_EXEC_0_ADDR0_LO__SHIFT … static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val) { … } #define REG_CP_COND_EXEC_1 … #define CP_COND_EXEC_1_ADDR0_HI__MASK … #define CP_COND_EXEC_1_ADDR0_HI__SHIFT … static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val) { … } #define REG_CP_COND_EXEC_2 … #define CP_COND_EXEC_2_ADDR1_LO__MASK … #define CP_COND_EXEC_2_ADDR1_LO__SHIFT … static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val) { … } #define REG_CP_COND_EXEC_3 … #define CP_COND_EXEC_3_ADDR1_HI__MASK … #define CP_COND_EXEC_3_ADDR1_HI__SHIFT … static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val) { … } #define REG_CP_COND_EXEC_4 … #define CP_COND_EXEC_4_REF__MASK … #define CP_COND_EXEC_4_REF__SHIFT … static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val) { … } #define REG_CP_COND_EXEC_5 … #define CP_COND_EXEC_5_DWORDS__MASK … #define CP_COND_EXEC_5_DWORDS__SHIFT … static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val) { … } #define REG_CP_SET_CTXSWITCH_IB_0 … #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK … #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT … static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val) { … } #define REG_CP_SET_CTXSWITCH_IB_1 … #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK … #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT … static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val) { … } #define REG_CP_SET_CTXSWITCH_IB_2 … #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK … #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT … static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val) { … } #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK … #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT … static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val) { … } #define REG_CP_REG_WRITE_0 … #define CP_REG_WRITE_0_TRACKER__MASK … #define CP_REG_WRITE_0_TRACKER__SHIFT … static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val) { … } #define REG_CP_REG_WRITE_1 … #define REG_CP_REG_WRITE_2 … #define REG_CP_SMMU_TABLE_UPDATE_0 … #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK … #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT … static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val) { … } #define REG_CP_SMMU_TABLE_UPDATE_1 … #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK … #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT … static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val) { … } #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK … #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT … static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val) { … } #define REG_CP_SMMU_TABLE_UPDATE_2 … #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK … #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT … static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val) { … } #define REG_CP_SMMU_TABLE_UPDATE_3 … #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK … #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT … static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) { … } #define REG_CP_START_BIN_BIN_COUNT … #define REG_CP_START_BIN_PREFIX_ADDR … #define REG_CP_START_BIN_PREFIX_DWORDS … #define REG_CP_START_BIN_BODY_DWORDS … #define REG_CP_WAIT_TIMESTAMP_0 … #define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK … #define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT … static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val) { … } #define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK … #define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT … static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val) { … } #define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR … #define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 … #define REG_CP_WAIT_TIMESTAMP_SRC_0 … #define REG_CP_WAIT_TIMESTAMP_SRC_1 … #define REG_CP_BV_BR_COUNT_OPS_0 … #define CP_BV_BR_COUNT_OPS_0_OP__MASK … #define CP_BV_BR_COUNT_OPS_0_OP__SHIFT … static inline uint32_t CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val) { … } #define REG_CP_BV_BR_COUNT_OPS_1 … #define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK … #define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT … static inline uint32_t CP_BV_BR_COUNT_OPS_1_BR_OFFSET(uint32_t val) { … } #define REG_CP_MODIFY_TIMESTAMP_0 … #define CP_MODIFY_TIMESTAMP_0_ADD__MASK … #define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT … static inline uint32_t CP_MODIFY_TIMESTAMP_0_ADD(uint32_t val) { … } #define CP_MODIFY_TIMESTAMP_0_OP__MASK … #define CP_MODIFY_TIMESTAMP_0_OP__SHIFT … static inline uint32_t CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val) { … } #define REG_CP_MEM_TO_SCRATCH_MEM_0 … #define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK … #define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT … static inline uint32_t CP_MEM_TO_SCRATCH_MEM_0_CNT(uint32_t val) { … } #define REG_CP_MEM_TO_SCRATCH_MEM_1 … #define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK … #define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT … static inline uint32_t CP_MEM_TO_SCRATCH_MEM_1_OFFSET(uint32_t val) { … } #define REG_CP_MEM_TO_SCRATCH_MEM_2 … #define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK … #define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT … static inline uint32_t CP_MEM_TO_SCRATCH_MEM_2_SRC(uint32_t val) { … } #define REG_CP_MEM_TO_SCRATCH_MEM_3 … #define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK … #define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT … static inline uint32_t CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(uint32_t val) { … } #define REG_CP_THREAD_CONTROL_0 … #define CP_THREAD_CONTROL_0_THREAD__MASK … #define CP_THREAD_CONTROL_0_THREAD__SHIFT … static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val) { … } #define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE … #define CP_THREAD_CONTROL_0_SYNC_THREADS … #define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE … #define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 … #define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK … #define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT … static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(uint32_t val) { … } #define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK … #define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT … static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(uint32_t val) { … } #define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 … #define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK … #define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT … static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(uint32_t val) { … } #define REG_CP_RESET_CONTEXT_STATE_0 … #define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS … #define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE … #define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS … #ifdef __cplusplus #endif #endif /* ADRENO_PM4_XML */
Codebase Browser
linux