#ifndef A6XX_XML #define A6XX_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/a6xx.xml ( 245646 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml ( 85907 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum a6xx_tile_mode { … }; enum a6xx_format { … }; enum a6xx_polygon_mode { … }; enum a6xx_depth_format { … }; enum a6xx_shader_id { … }; enum a7xx_statetype_id { … }; enum a6xx_debugbus_id { … }; enum a7xx_state_location { … }; enum a7xx_pipe { … }; enum a7xx_cluster { … }; enum a7xx_debugbus_id { … }; enum a6xx_cp_perfcounter_select { … }; enum a6xx_rbbm_perfcounter_select { … }; enum a6xx_pc_perfcounter_select { … }; enum a6xx_vfd_perfcounter_select { … }; enum a6xx_hlsq_perfcounter_select { … }; enum a6xx_vpc_perfcounter_select { … }; enum a6xx_tse_perfcounter_select { … }; enum a6xx_ras_perfcounter_select { … }; enum a6xx_uche_perfcounter_select { … }; enum a6xx_tp_perfcounter_select { … }; enum a6xx_sp_perfcounter_select { … }; enum a6xx_rb_perfcounter_select { … }; enum a6xx_vsc_perfcounter_select { … }; enum a6xx_ccu_perfcounter_select { … }; enum a6xx_lrz_perfcounter_select { … }; enum a6xx_cmp_perfcounter_select { … }; enum a6xx_2d_ifmt { … }; enum a6xx_ztest_mode { … }; enum a6xx_tess_spacing { … }; enum a6xx_tess_output { … }; enum a6xx_sequenced_thread_dist { … }; enum a6xx_single_prim_mode { … }; enum a6xx_raster_mode { … }; enum a6xx_raster_direction { … }; enum a6xx_render_mode { … }; enum a6xx_buffers_location { … }; enum a6xx_lrz_dir_status { … }; enum a6xx_fragcoord_sample_mode { … }; enum a6xx_rotation { … }; enum a6xx_ccu_cache_size { … }; enum a6xx_varying_interp_mode { … }; enum a6xx_varying_ps_repl_mode { … }; enum a6xx_threadsize { … }; enum a6xx_bindless_descriptor_size { … }; enum a6xx_isam_mode { … }; enum a7xx_cs_yalign { … }; enum a6xx_tex_filter { … }; enum a6xx_tex_clamp { … }; enum a6xx_tex_aniso { … }; enum a6xx_reduction_mode { … }; enum a6xx_tex_swiz { … }; enum a6xx_tex_type { … }; #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE … #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR … #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 … #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 … #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW … #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR … #define A6XX_RBBM_INT_0_MASK_CP_SW … #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR … #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS … #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS … #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS … #define A6XX_RBBM_INT_0_MASK_CP_IB2 … #define A6XX_RBBM_INT_0_MASK_CP_IB1 … #define A6XX_RBBM_INT_0_MASK_CP_RB … #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT … #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC … #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS … #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS … #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS … #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC … #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW … #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT … #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS … #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR … #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 … #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 … #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR … #define A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION … #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ … #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG … #define A6XX_CP_INT_CP_OPCODE_ERROR … #define A6XX_CP_INT_CP_UCODE_ERROR … #define A6XX_CP_INT_CP_HW_FAULT_ERROR … #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR … #define A6XX_CP_INT_CP_AHB_ERROR … #define A6XX_CP_INT_CP_VSD_PARITY_ERROR … #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR … #define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC … #define A6XX_CP_INT_CP_UCODE_ERROR_LPAC … #define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC … #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC … #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC … #define A6XX_CP_INT_CP_OPCODE_ERROR_BV … #define A6XX_CP_INT_CP_UCODE_ERROR_BV … #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV … #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV … #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV … #define REG_A6XX_CP_RB_BASE … #define REG_A6XX_CP_RB_CNTL … #define REG_A6XX_CP_RB_RPTR_ADDR … #define REG_A6XX_CP_RB_RPTR … #define REG_A6XX_CP_RB_WPTR … #define REG_A6XX_CP_SQE_CNTL … #define REG_A6XX_CP_CP2GMU_STATUS … #define A6XX_CP_CP2GMU_STATUS_IFPC … #define REG_A6XX_CP_HW_FAULT … #define REG_A6XX_CP_INTERRUPT_STATUS … #define REG_A6XX_CP_PROTECT_STATUS … #define REG_A6XX_CP_STATUS_1 … #define REG_A6XX_CP_SQE_INSTR_BASE … #define REG_A6XX_CP_MISC_CNTL … #define REG_A6XX_CP_APRIV_CNTL … #define A6XX_CP_APRIV_CNTL_CDWRITE … #define A6XX_CP_APRIV_CNTL_CDREAD … #define A6XX_CP_APRIV_CNTL_RBRPWB … #define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL … #define A6XX_CP_APRIV_CNTL_RBFETCH … #define A6XX_CP_APRIV_CNTL_ICACHE … #define REG_A6XX_CP_PREEMPT_THRESHOLD … #define REG_A6XX_CP_ROQ_THRESHOLDS_1 … #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK … #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT … static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) { … } #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK … #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT … static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) { … } #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK … #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT … static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) { … } #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK … #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT … static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) { … } #define REG_A6XX_CP_ROQ_THRESHOLDS_2 … #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK … #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT … static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) { … } #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK … #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT … static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) { … } #define REG_A6XX_CP_MEM_POOL_SIZE … #define REG_A6XX_CP_CHICKEN_DBG … #define REG_A6XX_CP_ADDR_MODE_CNTL … #define REG_A6XX_CP_DBG_ECO_CNTL … #define REG_A6XX_CP_PROTECT_CNTL … #define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE … #define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN … #define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN … #define REG_A6XX_CP_SCRATCH(i0) … static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { … } #define REG_A6XX_CP_PROTECT(i0) … static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { … } #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK … #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT … static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) { … } #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK … #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT … static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) { … } #define A6XX_CP_PROTECT_REG_READ … #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL … #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO … #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR … #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR … #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR … #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS … #define REG_A6XX_CP_PERFCTR_CP_SEL(i0) … #define REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0) … #define REG_A6XX_CP_CRASH_SCRIPT_BASE … #define REG_A6XX_CP_CRASH_DUMP_CNTL … #define REG_A6XX_CP_CRASH_DUMP_STATUS … #define REG_A6XX_CP_SQE_STAT_ADDR … #define REG_A6XX_CP_SQE_STAT_DATA … #define REG_A6XX_CP_DRAW_STATE_ADDR … #define REG_A6XX_CP_DRAW_STATE_DATA … #define REG_A6XX_CP_ROQ_DBG_ADDR … #define REG_A6XX_CP_ROQ_DBG_DATA … #define REG_A6XX_CP_MEM_POOL_DBG_ADDR … #define REG_A6XX_CP_MEM_POOL_DBG_DATA … #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR … #define REG_A6XX_CP_SQE_UCODE_DBG_DATA … #define REG_A6XX_CP_IB1_BASE … #define REG_A6XX_CP_IB1_REM_SIZE … #define REG_A6XX_CP_IB2_BASE … #define REG_A6XX_CP_IB2_REM_SIZE … #define REG_A6XX_CP_SDS_BASE … #define REG_A6XX_CP_SDS_REM_SIZE … #define REG_A6XX_CP_MRB_BASE … #define REG_A6XX_CP_MRB_REM_SIZE … #define REG_A6XX_CP_VSD_BASE … #define REG_A6XX_CP_ROQ_RB_STAT … #define A6XX_CP_ROQ_RB_STAT_RPTR__MASK … #define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val) { … } #define A6XX_CP_ROQ_RB_STAT_WPTR__MASK … #define A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val) { … } #define REG_A6XX_CP_ROQ_IB1_STAT … #define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK … #define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val) { … } #define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK … #define A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val) { … } #define REG_A6XX_CP_ROQ_IB2_STAT … #define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK … #define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val) { … } #define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK … #define A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val) { … } #define REG_A6XX_CP_ROQ_SDS_STAT … #define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK … #define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val) { … } #define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK … #define A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val) { … } #define REG_A6XX_CP_ROQ_MRB_STAT … #define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK … #define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val) { … } #define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK … #define A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val) { … } #define REG_A6XX_CP_ROQ_VSD_STAT … #define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK … #define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val) { … } #define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK … #define A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT … static inline uint32_t A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val) { … } #define REG_A6XX_CP_IB1_DWORDS … #define REG_A6XX_CP_IB2_DWORDS … #define REG_A6XX_CP_SDS_DWORDS … #define REG_A6XX_CP_MRB_DWORDS … #define REG_A6XX_CP_VSD_DWORDS … #define REG_A6XX_CP_ROQ_AVAIL_RB … #define A6XX_CP_ROQ_AVAIL_RB_REM__MASK … #define A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT … static inline uint32_t A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val) { … } #define REG_A6XX_CP_ROQ_AVAIL_IB1 … #define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK … #define A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT … static inline uint32_t A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val) { … } #define REG_A6XX_CP_ROQ_AVAIL_IB2 … #define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK … #define A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT … static inline uint32_t A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val) { … } #define REG_A6XX_CP_ROQ_AVAIL_SDS … #define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK … #define A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT … static inline uint32_t A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val) { … } #define REG_A6XX_CP_ROQ_AVAIL_MRB … #define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK … #define A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT … static inline uint32_t A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val) { … } #define REG_A6XX_CP_ROQ_AVAIL_VSD … #define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK … #define A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT … static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) { … } #define REG_A6XX_CP_ALWAYS_ON_COUNTER … #define REG_A6XX_CP_AHB_CNTL … #define REG_A6XX_CP_APERTURE_CNTL_HOST … #define REG_A7XX_CP_APERTURE_CNTL_HOST … #define A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK … #define A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT … static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val) { … } #define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK … #define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT … static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val) { … } #define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK … #define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT … static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(uint32_t val) { … } #define REG_A6XX_CP_APERTURE_CNTL_CD … #define REG_A7XX_CP_APERTURE_CNTL_CD … #define A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK … #define A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT … static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val) { … } #define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK … #define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT … static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val) { … } #define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK … #define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT … static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CONTEXT(uint32_t val) { … } #define REG_A7XX_CP_BV_PROTECT_STATUS … #define REG_A7XX_CP_BV_HW_FAULT … #define REG_A7XX_CP_BV_DRAW_STATE_ADDR … #define REG_A7XX_CP_BV_DRAW_STATE_DATA … #define REG_A7XX_CP_BV_ROQ_DBG_ADDR … #define REG_A7XX_CP_BV_ROQ_DBG_DATA … #define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR … #define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA … #define REG_A7XX_CP_BV_SQE_STAT_ADDR … #define REG_A7XX_CP_BV_SQE_STAT_DATA … #define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR … #define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA … #define REG_A7XX_CP_BV_RB_RPTR_ADDR … #define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR … #define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA … #define REG_A7XX_CP_BV_APRIV_CNTL … #define REG_A7XX_CP_BV_CHICKEN_DBG … #define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR … #define REG_A7XX_CP_LPAC_DRAW_STATE_DATA … #define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR … #define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR … #define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA … #define REG_A7XX_CP_SQE_AC_STAT_ADDR … #define REG_A7XX_CP_SQE_AC_STAT_DATA … #define REG_A7XX_CP_LPAC_APRIV_CNTL … #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE … #define REG_A7XX_CP_LPAC_ROQ_DBG_DATA … #define REG_A7XX_CP_LPAC_FIFO_DBG_DATA … #define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR … #define REG_A6XX_CP_LPAC_SQE_CNTL … #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE … #define REG_A7XX_CP_AQE_INSTR_BASE_0 … #define REG_A7XX_CP_AQE_INSTR_BASE_1 … #define REG_A7XX_CP_AQE_APRIV_CNTL … #define REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 … #define REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 … #define REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 … #define REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 … #define REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 … #define REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 … #define REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 … #define REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 … #define REG_A7XX_CP_AQE_STAT_ADDR_0 … #define REG_A7XX_CP_AQE_STAT_ADDR_1 … #define REG_A7XX_CP_AQE_STAT_DATA_0 … #define REG_A7XX_CP_AQE_STAT_DATA_1 … #define REG_A6XX_VSC_ADDR_MODE_CNTL … #define REG_A6XX_RBBM_GPR0_CNTL … #define REG_A6XX_RBBM_INT_0_STATUS … #define REG_A6XX_RBBM_STATUS … #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB … #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP … #define A6XX_RBBM_STATUS_HLSQ_BUSY … #define A6XX_RBBM_STATUS_VSC_BUSY … #define A6XX_RBBM_STATUS_TPL1_BUSY … #define A6XX_RBBM_STATUS_SP_BUSY … #define A6XX_RBBM_STATUS_UCHE_BUSY … #define A6XX_RBBM_STATUS_VPC_BUSY … #define A6XX_RBBM_STATUS_VFD_BUSY … #define A6XX_RBBM_STATUS_TESS_BUSY … #define A6XX_RBBM_STATUS_PC_VSD_BUSY … #define A6XX_RBBM_STATUS_PC_DCALL_BUSY … #define A6XX_RBBM_STATUS_COM_DCOM_BUSY … #define A6XX_RBBM_STATUS_LRZ_BUSY … #define A6XX_RBBM_STATUS_A2D_BUSY … #define A6XX_RBBM_STATUS_CCU_BUSY … #define A6XX_RBBM_STATUS_RB_BUSY … #define A6XX_RBBM_STATUS_RAS_BUSY … #define A6XX_RBBM_STATUS_TSE_BUSY … #define A6XX_RBBM_STATUS_VBIF_BUSY … #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY … #define A6XX_RBBM_STATUS_CP_BUSY … #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER … #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER … #define REG_A6XX_RBBM_STATUS1 … #define REG_A6XX_RBBM_STATUS2 … #define REG_A6XX_RBBM_STATUS3 … #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT … #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS … #define REG_A7XX_RBBM_CLOCK_MODE_CP … #define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ … #define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS … #define REG_A7XX_RBBM_CLOCK_MODE2_GRAS … #define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD … #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC … #define REG_A7XX_RBBM_SW_FUSE_INT_STATUS … #define REG_A7XX_RBBM_SW_FUSE_INT_MASK … #define REG_A6XX_RBBM_PERFCTR_CP(i0) … #define REG_A6XX_RBBM_PERFCTR_RBBM(i0) … #define REG_A6XX_RBBM_PERFCTR_PC(i0) … #define REG_A6XX_RBBM_PERFCTR_VFD(i0) … #define REG_A6XX_RBBM_PERFCTR_HLSQ(i0) … #define REG_A6XX_RBBM_PERFCTR_VPC(i0) … #define REG_A6XX_RBBM_PERFCTR_CCU(i0) … #define REG_A6XX_RBBM_PERFCTR_TSE(i0) … #define REG_A6XX_RBBM_PERFCTR_RAS(i0) … #define REG_A6XX_RBBM_PERFCTR_UCHE(i0) … #define REG_A6XX_RBBM_PERFCTR_TP(i0) … #define REG_A6XX_RBBM_PERFCTR_SP(i0) … #define REG_A6XX_RBBM_PERFCTR_RB(i0) … #define REG_A6XX_RBBM_PERFCTR_VSC(i0) … #define REG_A6XX_RBBM_PERFCTR_LRZ(i0) … #define REG_A6XX_RBBM_PERFCTR_CMP(i0) … #define REG_A7XX_RBBM_PERFCTR_CP(i0) … #define REG_A7XX_RBBM_PERFCTR_RBBM(i0) … #define REG_A7XX_RBBM_PERFCTR_PC(i0) … #define REG_A7XX_RBBM_PERFCTR_VFD(i0) … #define REG_A7XX_RBBM_PERFCTR_HLSQ(i0) … #define REG_A7XX_RBBM_PERFCTR_VPC(i0) … #define REG_A7XX_RBBM_PERFCTR_CCU(i0) … #define REG_A7XX_RBBM_PERFCTR_TSE(i0) … #define REG_A7XX_RBBM_PERFCTR_RAS(i0) … #define REG_A7XX_RBBM_PERFCTR_UCHE(i0) … #define REG_A7XX_RBBM_PERFCTR_TP(i0) … #define REG_A7XX_RBBM_PERFCTR_SP(i0) … #define REG_A7XX_RBBM_PERFCTR_RB(i0) … #define REG_A7XX_RBBM_PERFCTR_VSC(i0) … #define REG_A7XX_RBBM_PERFCTR_LRZ(i0) … #define REG_A7XX_RBBM_PERFCTR_CMP(i0) … #define REG_A7XX_RBBM_PERFCTR_UFC(i0) … #define REG_A7XX_RBBM_PERFCTR2_HLSQ(i0) … #define REG_A7XX_RBBM_PERFCTR2_CP(i0) … #define REG_A7XX_RBBM_PERFCTR2_SP(i0) … #define REG_A7XX_RBBM_PERFCTR2_TP(i0) … #define REG_A7XX_RBBM_PERFCTR2_UFC(i0) … #define REG_A7XX_RBBM_PERFCTR_BV_PC(i0) … #define REG_A7XX_RBBM_PERFCTR_BV_VFD(i0) … #define REG_A7XX_RBBM_PERFCTR_BV_VPC(i0) … #define REG_A7XX_RBBM_PERFCTR_BV_TSE(i0) … #define REG_A7XX_RBBM_PERFCTR_BV_RAS(i0) … #define REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0) … #define REG_A6XX_RBBM_PERFCTR_CNTL … #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 … #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 … #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 … #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 … #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO … #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI … #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0) … #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED … #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD … #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS … #define REG_A6XX_RBBM_ISDB_CNT … #define REG_A7XX_RBBM_NC_MODE_CNTL … #define REG_A7XX_RBBM_SNAPSHOT_STATUS … #define REG_A6XX_RBBM_PRIMCTR_0_LO … #define REG_A6XX_RBBM_PRIMCTR_0_HI … #define REG_A6XX_RBBM_PRIMCTR_1_LO … #define REG_A6XX_RBBM_PRIMCTR_1_HI … #define REG_A6XX_RBBM_PRIMCTR_2_LO … #define REG_A6XX_RBBM_PRIMCTR_2_HI … #define REG_A6XX_RBBM_PRIMCTR_3_LO … #define REG_A6XX_RBBM_PRIMCTR_3_HI … #define REG_A6XX_RBBM_PRIMCTR_4_LO … #define REG_A6XX_RBBM_PRIMCTR_4_HI … #define REG_A6XX_RBBM_PRIMCTR_5_LO … #define REG_A6XX_RBBM_PRIMCTR_5_HI … #define REG_A6XX_RBBM_PRIMCTR_6_LO … #define REG_A6XX_RBBM_PRIMCTR_6_HI … #define REG_A6XX_RBBM_PRIMCTR_7_LO … #define REG_A6XX_RBBM_PRIMCTR_7_HI … #define REG_A6XX_RBBM_PRIMCTR_8_LO … #define REG_A6XX_RBBM_PRIMCTR_8_HI … #define REG_A6XX_RBBM_PRIMCTR_9_LO … #define REG_A6XX_RBBM_PRIMCTR_9_HI … #define REG_A6XX_RBBM_PRIMCTR_10_LO … #define REG_A6XX_RBBM_PRIMCTR_10_HI … #define REG_A6XX_RBBM_SECVID_TRUST_CNTL … #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE … #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE … #define REG_A6XX_RBBM_SECVID_TSB_CNTL … #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL … #define REG_A7XX_RBBM_SECVID_TSB_STATUS … #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL … #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL … #define REG_A6XX_RBBM_GBIF_HALT … #define REG_A6XX_RBBM_GBIF_HALT_ACK … #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD … #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE … #define REG_A7XX_RBBM_GBIF_HALT … #define REG_A7XX_RBBM_GBIF_HALT_ACK … #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL … #define REG_A6XX_RBBM_INT_CLEAR_CMD … #define REG_A6XX_RBBM_INT_0_MASK … #define REG_A7XX_RBBM_INT_2_MASK … #define REG_A6XX_RBBM_SP_HYST_CNT … #define REG_A6XX_RBBM_SW_RESET_CMD … #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT … #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD … #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 … #define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL … #define REG_A6XX_RBBM_CLOCK_CNTL … #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 … #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 … #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 … #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 … #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 … #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 … #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 … #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 … #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 … #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 … #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 … #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 … #define REG_A6XX_RBBM_CLOCK_HYST_SP0 … #define REG_A6XX_RBBM_CLOCK_HYST_SP1 … #define REG_A6XX_RBBM_CLOCK_HYST_SP2 … #define REG_A6XX_RBBM_CLOCK_HYST_SP3 … #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 … #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 … #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 … #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 … #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 … #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 … #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 … #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 … #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 … #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 … #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 … #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 … #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 … #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 … #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 … #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 … #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 … #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 … #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 … #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 … #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 … #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 … #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 … #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 … #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 … #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 … #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 … #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 … #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 … #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 … #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 … #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 … #define REG_A6XX_RBBM_CLOCK_HYST_TP0 … #define REG_A6XX_RBBM_CLOCK_HYST_TP1 … #define REG_A6XX_RBBM_CLOCK_HYST_TP2 … #define REG_A6XX_RBBM_CLOCK_HYST_TP3 … #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 … #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 … #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 … #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 … #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 … #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 … #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 … #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 … #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 … #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 … #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 … #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 … #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 … #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 … #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 … #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 … #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 … #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 … #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 … #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 … #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 … #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 … #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 … #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 … #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 … #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 … #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 … #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 … #define REG_A6XX_RBBM_CLOCK_CNTL_RAC … #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC … #define REG_A6XX_RBBM_CLOCK_DELAY_RAC … #define REG_A6XX_RBBM_CLOCK_HYST_RAC … #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM … #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM … #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM … #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE … #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE … #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE … #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE … #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE … #define REG_A6XX_RBBM_CLOCK_HYST_UCHE … #define REG_A6XX_RBBM_CLOCK_MODE_VFD … #define REG_A6XX_RBBM_CLOCK_DELAY_VFD … #define REG_A6XX_RBBM_CLOCK_HYST_VFD … #define REG_A6XX_RBBM_CLOCK_MODE_GPC … #define REG_A6XX_RBBM_CLOCK_DELAY_GPC … #define REG_A6XX_RBBM_CLOCK_HYST_GPC … #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 … #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX … #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX … #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX … #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ … #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ … #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ … #define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD … #define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD … #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE … #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE … #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE … #define REG_A7XX_RBBM_CGC_P2S_STATUS … #define A7XX_RBBM_CGC_P2S_STATUS_TXDONE … #define REG_A6XX_RBBM_CLOCK_CNTL_FCHE … #define REG_A6XX_RBBM_CLOCK_DELAY_FCHE … #define REG_A6XX_RBBM_CLOCK_HYST_FCHE … #define REG_A6XX_RBBM_CLOCK_CNTL_MHUB … #define REG_A6XX_RBBM_CLOCK_DELAY_MHUB … #define REG_A6XX_RBBM_CLOCK_HYST_MHUB … #define REG_A6XX_RBBM_CLOCK_DELAY_GLC … #define REG_A6XX_RBBM_CLOCK_HYST_GLC … #define REG_A6XX_RBBM_CLOCK_CNTL_GLC … #define REG_A7XX_RBBM_CLOCK_HYST2_VFD … #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL … #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A … #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B … #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C … #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D … #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK … #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK … #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) { … } #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT … #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK … #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK … #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK … #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) { … } #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM … #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK … #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) { … } #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 … #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 … #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 … #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 … #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 … #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 … #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 … #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 … #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) { … } #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) { … } #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK … #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT … static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) { … } #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 … #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 … #define REG_A6XX_VSC_PERFCTR_VSC_SEL(i0) … #define REG_A7XX_VSC_UNKNOWN_0CD8 … #define A7XX_VSC_UNKNOWN_0CD8_BINNING … #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE … #define REG_A6XX_HLSQ_DBG_READ_SEL … #define REG_A6XX_UCHE_ADDR_MODE_CNTL … #define REG_A6XX_UCHE_MODE_CNTL … #define REG_A6XX_UCHE_WRITE_RANGE_MAX … #define REG_A6XX_UCHE_WRITE_THRU_BASE … #define REG_A6XX_UCHE_TRAP_BASE … #define REG_A6XX_UCHE_GMEM_RANGE_MIN … #define REG_A6XX_UCHE_GMEM_RANGE_MAX … #define REG_A6XX_UCHE_CACHE_WAYS … #define REG_A6XX_UCHE_FILTER_CNTL … #define REG_A6XX_UCHE_CLIENT_PF … #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK … #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT … static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) { … } #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0) … #define REG_A6XX_UCHE_GBIF_GX_CONFIG … #define REG_A6XX_UCHE_CMDQ_CONFIG … #define REG_A6XX_VBIF_VERSION … #define REG_A6XX_VBIF_CLKON … #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS … #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN … #define REG_A6XX_VBIF_XIN_HALT_CTRL0 … #define REG_A6XX_VBIF_XIN_HALT_CTRL1 … #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL … #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 … #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 … #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK … #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT … static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) { … } #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 … #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 … #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK … #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT … static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) { … } #define REG_A6XX_VBIF_TEST_BUS_OUT … #define REG_A6XX_VBIF_PERF_CNT_SEL0 … #define REG_A6XX_VBIF_PERF_CNT_SEL1 … #define REG_A6XX_VBIF_PERF_CNT_SEL2 … #define REG_A6XX_VBIF_PERF_CNT_SEL3 … #define REG_A6XX_VBIF_PERF_CNT_LOW0 … #define REG_A6XX_VBIF_PERF_CNT_LOW1 … #define REG_A6XX_VBIF_PERF_CNT_LOW2 … #define REG_A6XX_VBIF_PERF_CNT_LOW3 … #define REG_A6XX_VBIF_PERF_CNT_HIGH0 … #define REG_A6XX_VBIF_PERF_CNT_HIGH1 … #define REG_A6XX_VBIF_PERF_CNT_HIGH2 … #define REG_A6XX_VBIF_PERF_CNT_HIGH3 … #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 … #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 … #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 … #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 … #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 … #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 … #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 … #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 … #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 … #define REG_A6XX_GBIF_SCACHE_CNTL0 … #define REG_A6XX_GBIF_SCACHE_CNTL1 … #define REG_A6XX_GBIF_QSB_SIDE0 … #define REG_A6XX_GBIF_QSB_SIDE1 … #define REG_A6XX_GBIF_QSB_SIDE2 … #define REG_A6XX_GBIF_QSB_SIDE3 … #define REG_A6XX_GBIF_HALT … #define REG_A6XX_GBIF_HALT_ACK … #define REG_A6XX_GBIF_PERF_PWR_CNT_EN … #define REG_A6XX_GBIF_PERF_PWR_CNT_CLR … #define REG_A6XX_GBIF_PERF_CNT_SEL … #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL … #define REG_A6XX_GBIF_PERF_CNT_LOW0 … #define REG_A6XX_GBIF_PERF_CNT_LOW1 … #define REG_A6XX_GBIF_PERF_CNT_LOW2 … #define REG_A6XX_GBIF_PERF_CNT_LOW3 … #define REG_A6XX_GBIF_PERF_CNT_HIGH0 … #define REG_A6XX_GBIF_PERF_CNT_HIGH1 … #define REG_A6XX_GBIF_PERF_CNT_HIGH2 … #define REG_A6XX_GBIF_PERF_CNT_HIGH3 … #define REG_A6XX_GBIF_PWR_CNT_LOW0 … #define REG_A6XX_GBIF_PWR_CNT_LOW1 … #define REG_A6XX_GBIF_PWR_CNT_LOW2 … #define REG_A6XX_GBIF_PWR_CNT_HIGH0 … #define REG_A6XX_GBIF_PWR_CNT_HIGH1 … #define REG_A6XX_GBIF_PWR_CNT_HIGH2 … #define REG_A6XX_VSC_DBG_ECO_CNTL … #define REG_A6XX_VSC_BIN_SIZE … #define A6XX_VSC_BIN_SIZE_WIDTH__MASK … #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT … static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { … } #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK … #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT … static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { … } #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS … #define REG_A6XX_VSC_BIN_COUNT … #define A6XX_VSC_BIN_COUNT_NX__MASK … #define A6XX_VSC_BIN_COUNT_NX__SHIFT … static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) { … } #define A6XX_VSC_BIN_COUNT_NY__MASK … #define A6XX_VSC_BIN_COUNT_NY__SHIFT … static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) { … } #define REG_A6XX_VSC_PIPE_CONFIG(i0) … static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { … } #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK … #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT … static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) { … } #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK … #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT … static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) { … } #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK … #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT … static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) { … } #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK … #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT … static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) { … } #define REG_A6XX_VSC_PRIM_STRM_ADDRESS … #define REG_A6XX_VSC_PRIM_STRM_PITCH … #define REG_A6XX_VSC_PRIM_STRM_LIMIT … #define REG_A6XX_VSC_DRAW_STRM_ADDRESS … #define REG_A6XX_VSC_DRAW_STRM_PITCH … #define REG_A6XX_VSC_DRAW_STRM_LIMIT … #define REG_A6XX_VSC_STATE(i0) … static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { … } #define REG_A6XX_VSC_PRIM_STRM_SIZE(i0) … static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { … } #define REG_A6XX_VSC_DRAW_STRM_SIZE(i0) … static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { … } #define REG_A7XX_VSC_UNKNOWN_0D08 … #define REG_A7XX_UCHE_UNKNOWN_0E10 … #define REG_A7XX_UCHE_UNKNOWN_0E11 … #define REG_A6XX_UCHE_UNKNOWN_0E12 … #define REG_A6XX_GRAS_CL_CNTL … #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE … #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE … #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE … #define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE … #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z … #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE … #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE … #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE … #define REG_A6XX_GRAS_VS_CL_CNTL … #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK … #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK … #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT … static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) { … } #define REG_A6XX_GRAS_DS_CL_CNTL … #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK … #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK … #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT … static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) { … } #define REG_A6XX_GRAS_GS_CL_CNTL … #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK … #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK … #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT … static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) { … } #define REG_A6XX_GRAS_MAX_LAYER_INDEX … #define REG_A6XX_GRAS_CNTL … #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL … #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID … #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE … #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL … #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID … #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE … #define A6XX_GRAS_CNTL_COORD_MASK__MASK … #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT … static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) { … } #define A6XX_GRAS_CNTL_UNK10 … #define A6XX_GRAS_CNTL_UNK11 … #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ … #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK … #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT … static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) { … } #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK … #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT … static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) { … } #define REG_A7XX_GRAS_UNKNOWN_8007 … #define REG_A7XX_GRAS_UNKNOWN_8008 … #define REG_A7XX_GRAS_UNKNOWN_8009 … #define REG_A7XX_GRAS_UNKNOWN_800A … #define REG_A7XX_GRAS_UNKNOWN_800B … #define REG_A7XX_GRAS_UNKNOWN_800C … #define REG_A6XX_GRAS_CL_VPORT(i0) … static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { … } #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK … #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT … static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) { … } static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { … } #define A6XX_GRAS_CL_VPORT_XSCALE__MASK … #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT … static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) { … } static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { … } #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK … #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT … static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) { … } static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { … } #define A6XX_GRAS_CL_VPORT_YSCALE__MASK … #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT … static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) { … } static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { … } #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK … #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT … static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) { … } static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { … } #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK … #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT … static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) { … } #define REG_A6XX_GRAS_CL_Z_CLAMP(i0) … static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { … } #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK … #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT … static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) { … } static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { … } #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK … #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT … static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) { … } #define REG_A6XX_GRAS_SU_CNTL … #define A6XX_GRAS_SU_CNTL_CULL_FRONT … #define A6XX_GRAS_SU_CNTL_CULL_BACK … #define A6XX_GRAS_SU_CNTL_FRONT_CW … #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK … #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT … static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) { … } #define A6XX_GRAS_SU_CNTL_POLY_OFFSET … #define A6XX_GRAS_SU_CNTL_UNK12 … #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK … #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT … static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) { … } #define A6XX_GRAS_SU_CNTL_UNK15__MASK … #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT … static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) { … } #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE … #define A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR … #define A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR … #define A6XX_GRAS_SU_CNTL_UNK20__MASK … #define A6XX_GRAS_SU_CNTL_UNK20__SHIFT … static inline uint32_t A6XX_GRAS_SU_CNTL_UNK20(uint32_t val) { … } #define REG_A6XX_GRAS_SU_POINT_MINMAX … #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK … #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT … static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) { … } #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK … #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT … static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) { … } #define REG_A6XX_GRAS_SU_POINT_SIZE … #define A6XX_GRAS_SU_POINT_SIZE__MASK … #define A6XX_GRAS_SU_POINT_SIZE__SHIFT … static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) { … } #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL … #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK … #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT … static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) { … } #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE … #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK … #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT … static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) { … } #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET … #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK … #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT … static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) { … } #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP … #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK … #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT … static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) { … } #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO … #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK … #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) { … } #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 … #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL … #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN … #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK … #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT … static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) { … } #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN … #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK … #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT … static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) { … } #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL … #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 … #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN … #define REG_A6XX_GRAS_VS_LAYER_CNTL … #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER … #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW … #define REG_A6XX_GRAS_GS_LAYER_CNTL … #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER … #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW … #define REG_A6XX_GRAS_DS_LAYER_CNTL … #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER … #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW … #define REG_A6XX_GRAS_SC_CNTL … #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK … #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT … static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) { … } #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK … #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT … static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) { … } #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK … #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT … static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) { … } #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK … #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT … static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) { … } #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK … #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT … static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) { … } #define A6XX_GRAS_SC_CNTL_UNK9 … #define A6XX_GRAS_SC_CNTL_ROTATION__MASK … #define A6XX_GRAS_SC_CNTL_ROTATION__SHIFT … static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) { … } #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN … #define REG_A6XX_GRAS_BIN_CONTROL … #define A6XX_GRAS_BIN_CONTROL_BINW__MASK … #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT … static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) { … } #define A6XX_GRAS_BIN_CONTROL_BINH__MASK … #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT … static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) { … } #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK … #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT … static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) { … } #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS … #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK … #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT … static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) { … } #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK … #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT … static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) { … } #define A6XX_GRAS_BIN_CONTROL_UNK27 … #define REG_A6XX_GRAS_RAS_MSAA_CNTL … #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK … #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2 … #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3 … #define REG_A6XX_GRAS_DEST_MSAA_CNTL … #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK … #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE … #define REG_A6XX_GRAS_SAMPLE_CONFIG … #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 … #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE … #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { … } #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { … } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK … #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT … static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { … } #define REG_A7XX_GRAS_UNKNOWN_80A7 … #define REG_A6XX_GRAS_UNKNOWN_80AF … #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0) … static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { … } #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK … #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT … static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) { … } #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK … #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT … static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) { … } static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { … } #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK … #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT … static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) { … } #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK … #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT … static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0) … static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { … } #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK … #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT … static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) { … } #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK … #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT … static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) { … } static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { … } #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK … #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT … static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) { … } #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK … #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT … static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL … #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK … #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT … static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) { … } #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK … #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT … static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR … #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK … #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT … static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) { … } #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK … #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT … static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A7XX_GRAS_UNKNOWN_80F4 … #define REG_A7XX_GRAS_UNKNOWN_80F5 … #define REG_A7XX_GRAS_UNKNOWN_80F6 … #define REG_A7XX_GRAS_UNKNOWN_80F8 … #define REG_A7XX_GRAS_UNKNOWN_80F9 … #define REG_A7XX_GRAS_UNKNOWN_80FA … #define REG_A6XX_GRAS_LRZ_CNTL … #define A6XX_GRAS_LRZ_CNTL_ENABLE … #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE … #define A6XX_GRAS_LRZ_CNTL_GREATER … #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE … #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE … #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE … #define A6XX_GRAS_LRZ_CNTL_DIR__MASK … #define A6XX_GRAS_LRZ_CNTL_DIR__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) { … } #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE … #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR … #define A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK … #define A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val) { … } #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL … #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID … #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK … #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) { … } #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 … #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK … #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) { … } #define REG_A6XX_GRAS_LRZ_BUFFER_BASE … #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH … #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK … #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) { … } #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK … #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE … #define REG_A6XX_GRAS_SAMPLE_CNTL … #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE … #define REG_A6XX_GRAS_LRZ_DEPTH_VIEW … #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK … #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val) { … } #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK … #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val) { … } #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK … #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT … static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) { … } #define REG_A7XX_GRAS_UNKNOWN_810B … #define REG_A6XX_GRAS_UNKNOWN_8110 … #define REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 … #define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK … #define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT … static inline uint32_t A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val) { … } #define REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO … #define REG_A7XX_GRAS_UNKNOWN_8120 … #define REG_A7XX_GRAS_UNKNOWN_8121 … #define REG_A6XX_GRAS_2D_BLIT_CNTL … #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK … #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT … static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) { … } #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN … #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK … #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT … static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) { … } #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR … #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK … #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR … #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK … #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT … static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) { … } #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 … #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK … #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT … static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) { … } #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK … #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT … static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) { … } #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK … #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT … static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) { … } #define A6XX_GRAS_2D_BLIT_CNTL_UNK30 … #define REG_A6XX_GRAS_2D_SRC_TL_X … #define A6XX_GRAS_2D_SRC_TL_X__MASK … #define A6XX_GRAS_2D_SRC_TL_X__SHIFT … static inline uint32_t A6XX_GRAS_2D_SRC_TL_X(int32_t val) { … } #define REG_A6XX_GRAS_2D_SRC_BR_X … #define A6XX_GRAS_2D_SRC_BR_X__MASK … #define A6XX_GRAS_2D_SRC_BR_X__SHIFT … static inline uint32_t A6XX_GRAS_2D_SRC_BR_X(int32_t val) { … } #define REG_A6XX_GRAS_2D_SRC_TL_Y … #define A6XX_GRAS_2D_SRC_TL_Y__MASK … #define A6XX_GRAS_2D_SRC_TL_Y__SHIFT … static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y(int32_t val) { … } #define REG_A6XX_GRAS_2D_SRC_BR_Y … #define A6XX_GRAS_2D_SRC_BR_Y__MASK … #define A6XX_GRAS_2D_SRC_BR_Y__SHIFT … static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y(int32_t val) { … } #define REG_A6XX_GRAS_2D_DST_TL … #define A6XX_GRAS_2D_DST_TL_X__MASK … #define A6XX_GRAS_2D_DST_TL_X__SHIFT … static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) { … } #define A6XX_GRAS_2D_DST_TL_Y__MASK … #define A6XX_GRAS_2D_DST_TL_Y__SHIFT … static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) { … } #define REG_A6XX_GRAS_2D_DST_BR … #define A6XX_GRAS_2D_DST_BR_X__MASK … #define A6XX_GRAS_2D_DST_BR_X__SHIFT … static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) { … } #define A6XX_GRAS_2D_DST_BR_Y__MASK … #define A6XX_GRAS_2D_DST_BR_Y__SHIFT … static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) { … } #define REG_A6XX_GRAS_2D_UNKNOWN_8407 … #define REG_A6XX_GRAS_2D_UNKNOWN_8408 … #define REG_A6XX_GRAS_2D_UNKNOWN_8409 … #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 … #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK … #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT … static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) { … } #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK … #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT … static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) { … } #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 … #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK … #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT … static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) { … } #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK … #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT … static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) { … } #define REG_A6XX_GRAS_DBG_ECO_CNTL … #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 … #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS … #define REG_A6XX_GRAS_ADDR_MODE_CNTL … #define REG_A7XX_GRAS_NC_MODE_CNTL … #define REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0) … #define REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0) … #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0) … #define REG_A6XX_RB_BIN_CONTROL … #define A6XX_RB_BIN_CONTROL_BINW__MASK … #define A6XX_RB_BIN_CONTROL_BINW__SHIFT … static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) { … } #define A6XX_RB_BIN_CONTROL_BINH__MASK … #define A6XX_RB_BIN_CONTROL_BINH__SHIFT … static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) { … } #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK … #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT … static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) { … } #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS … #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK … #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT … static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) { … } #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK … #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT … static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) { … } #define REG_A7XX_RB_BIN_CONTROL … #define A7XX_RB_BIN_CONTROL_BINW__MASK … #define A7XX_RB_BIN_CONTROL_BINW__SHIFT … static inline uint32_t A7XX_RB_BIN_CONTROL_BINW(uint32_t val) { … } #define A7XX_RB_BIN_CONTROL_BINH__MASK … #define A7XX_RB_BIN_CONTROL_BINH__SHIFT … static inline uint32_t A7XX_RB_BIN_CONTROL_BINH(uint32_t val) { … } #define A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK … #define A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT … static inline uint32_t A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) { … } #define A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS … #define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK … #define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT … static inline uint32_t A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) { … } #define REG_A6XX_RB_RENDER_CNTL … #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK … #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT … static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) { … } #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN … #define A6XX_RB_RENDER_CNTL_BINNING … #define A6XX_RB_RENDER_CNTL_UNK8__MASK … #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT … static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) { … } #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK … #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT … static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) { … } #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK … #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT … static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) { … } #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN … #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN … #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH … #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK … #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT … static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) { … } #define REG_A7XX_RB_RENDER_CNTL … #define A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN … #define A7XX_RB_RENDER_CNTL_BINNING … #define A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK … #define A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT … static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) { … } #define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK … #define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT … static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) { … } #define A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN … #define A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN … #define REG_A7XX_GRAS_SU_RENDER_CNTL … #define A7XX_GRAS_SU_RENDER_CNTL_BINNING … #define REG_A6XX_RB_RAS_MSAA_CNTL … #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK … #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_RB_RAS_MSAA_CNTL_UNK2 … #define A6XX_RB_RAS_MSAA_CNTL_UNK3 … #define REG_A6XX_RB_DEST_MSAA_CNTL … #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK … #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE … #define REG_A6XX_RB_SAMPLE_CONFIG … #define A6XX_RB_SAMPLE_CONFIG_UNK0 … #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE … #define REG_A6XX_RB_SAMPLE_LOCATION_0 … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { … } #define REG_A6XX_RB_SAMPLE_LOCATION_1 … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { … } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK … #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT … static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { … } #define REG_A6XX_RB_RENDER_CONTROL0 … #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL … #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID … #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE … #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL … #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID … #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE … #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK … #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT … static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) { … } #define A6XX_RB_RENDER_CONTROL0_UNK10 … #define REG_A6XX_RB_RENDER_CONTROL1 … #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK … #define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE … #define A6XX_RB_RENDER_CONTROL1_FACENESS … #define A6XX_RB_RENDER_CONTROL1_SAMPLEID … #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK … #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT … static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) { … } #define A6XX_RB_RENDER_CONTROL1_CENTERRHW … #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN … #define A6XX_RB_RENDER_CONTROL1_FOVEATION … #define REG_A6XX_RB_FS_OUTPUT_CNTL0 … #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE … #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z … #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK … #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF … #define REG_A6XX_RB_FS_OUTPUT_CNTL1 … #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK … #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT … static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) { … } #define REG_A6XX_RB_RENDER_COMPONENTS … #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) { … } #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) { … } #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) { … } #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) { … } #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) { … } #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) { … } #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) { … } #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK … #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT … static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) { … } #define REG_A6XX_RB_DITHER_CNTL … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) { … } #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) { … } #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) { … } #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) { … } #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) { … } #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) { … } #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) { … } #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK … #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT … static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) { … } #define REG_A6XX_RB_SRGB_CNTL … #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 … #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 … #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 … #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 … #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 … #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 … #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 … #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 … #define REG_A6XX_RB_SAMPLE_CNTL … #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE … #define REG_A6XX_RB_UNKNOWN_8811 … #define REG_A7XX_RB_UNKNOWN_8812 … #define REG_A6XX_RB_UNKNOWN_8818 … #define REG_A6XX_RB_UNKNOWN_8819 … #define REG_A6XX_RB_UNKNOWN_881A … #define REG_A6XX_RB_UNKNOWN_881B … #define REG_A6XX_RB_UNKNOWN_881C … #define REG_A6XX_RB_UNKNOWN_881D … #define REG_A6XX_RB_UNKNOWN_881E … #define REG_A6XX_RB_MRT(i0) … static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { … } #define A6XX_RB_MRT_CONTROL_BLEND … #define A6XX_RB_MRT_CONTROL_BLEND2 … #define A6XX_RB_MRT_CONTROL_ROP_ENABLE … #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK … #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT … static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) { … } #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK … #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT … static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) { … } static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { … } #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK … #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT … static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK … #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT … static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK … #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT … static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK … #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT … static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK … #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT … static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK … #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT … static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { … } #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK … #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK … #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT … static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) { … } #define A6XX_RB_MRT_BUF_INFO_UNK10 … #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK … #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } static inline uint32_t REG_A7XX_RB_MRT_BUF_INFO(uint32_t i0) { … } #define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK … #define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) { … } #define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK … #define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT … static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) { … } #define A7XX_RB_MRT_BUF_INFO_UNK10 … #define A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN … #define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK … #define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { … } #define A6XX_RB_MRT_PITCH__MASK … #define A6XX_RB_MRT_PITCH__SHIFT … static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) { … } static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { … } #define A6XX_RB_MRT_ARRAY_PITCH__MASK … #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) { … } static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { … } static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { … } #define REG_A6XX_RB_BLEND_RED_F32 … #define A6XX_RB_BLEND_RED_F32__MASK … #define A6XX_RB_BLEND_RED_F32__SHIFT … static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) { … } #define REG_A6XX_RB_BLEND_GREEN_F32 … #define A6XX_RB_BLEND_GREEN_F32__MASK … #define A6XX_RB_BLEND_GREEN_F32__SHIFT … static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) { … } #define REG_A6XX_RB_BLEND_BLUE_F32 … #define A6XX_RB_BLEND_BLUE_F32__MASK … #define A6XX_RB_BLEND_BLUE_F32__SHIFT … static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) { … } #define REG_A6XX_RB_BLEND_ALPHA_F32 … #define A6XX_RB_BLEND_ALPHA_F32__MASK … #define A6XX_RB_BLEND_ALPHA_F32__SHIFT … static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) { … } #define REG_A6XX_RB_ALPHA_CONTROL … #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK … #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT … static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) { … } #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST … #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK … #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT … static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) { … } #define REG_A6XX_RB_BLEND_CNTL … #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK … #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT … static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) { … } #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND … #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE … #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE … #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE … #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK … #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT … static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) { … } #define REG_A6XX_RB_DEPTH_PLANE_CNTL … #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK … #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT … static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) { … } #define REG_A6XX_RB_DEPTH_CNTL … #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE … #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE … #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK … #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT … static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) { … } #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE … #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE … #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE … #define REG_A6XX_GRAS_SU_DEPTH_CNTL … #define A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE … #define REG_A6XX_RB_DEPTH_BUFFER_INFO … #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK … #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) { … } #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK … #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT … static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) { … } #define REG_A7XX_RB_DEPTH_BUFFER_INFO … #define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK … #define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) { … } #define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK … #define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT … static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) { … } #define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK … #define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT … static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val) { … } #define A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN … #define REG_A6XX_RB_DEPTH_BUFFER_PITCH … #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK … #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT … static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) { … } #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH … #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK … #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_RB_DEPTH_BUFFER_BASE … #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM … #define REG_A6XX_RB_Z_BOUNDS_MIN … #define A6XX_RB_Z_BOUNDS_MIN__MASK … #define A6XX_RB_Z_BOUNDS_MIN__SHIFT … static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) { … } #define REG_A6XX_RB_Z_BOUNDS_MAX … #define A6XX_RB_Z_BOUNDS_MAX__MASK … #define A6XX_RB_Z_BOUNDS_MAX__SHIFT … static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) { … } #define REG_A6XX_RB_STENCIL_CONTROL … #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE … #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF … #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ … #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK … #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) { … } #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK … #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) { … } #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK … #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) { … } #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK … #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) { … } #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK … #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) { … } #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK … #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) { … } #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK … #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) { … } #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK … #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT … static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) { … } #define REG_A6XX_GRAS_SU_STENCIL_CNTL … #define A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE … #define REG_A6XX_RB_STENCIL_INFO … #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL … #define A6XX_RB_STENCIL_INFO_UNK1 … #define REG_A7XX_RB_STENCIL_INFO … #define A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL … #define A7XX_RB_STENCIL_INFO_UNK1 … #define A7XX_RB_STENCIL_INFO_TILEMODE__MASK … #define A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT … static inline uint32_t A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val) { … } #define REG_A6XX_RB_STENCIL_BUFFER_PITCH … #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK … #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT … static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) { … } #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH … #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK … #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_RB_STENCIL_BUFFER_BASE … #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM … #define REG_A6XX_RB_STENCILREF … #define A6XX_RB_STENCILREF_REF__MASK … #define A6XX_RB_STENCILREF_REF__SHIFT … static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) { … } #define A6XX_RB_STENCILREF_BFREF__MASK … #define A6XX_RB_STENCILREF_BFREF__SHIFT … static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) { … } #define REG_A6XX_RB_STENCILMASK … #define A6XX_RB_STENCILMASK_MASK__MASK … #define A6XX_RB_STENCILMASK_MASK__SHIFT … static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) { … } #define A6XX_RB_STENCILMASK_BFMASK__MASK … #define A6XX_RB_STENCILMASK_BFMASK__SHIFT … static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) { … } #define REG_A6XX_RB_STENCILWRMASK … #define A6XX_RB_STENCILWRMASK_WRMASK__MASK … #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT … static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) { … } #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK … #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT … static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) { … } #define REG_A6XX_RB_WINDOW_OFFSET … #define A6XX_RB_WINDOW_OFFSET_X__MASK … #define A6XX_RB_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) { … } #define A6XX_RB_WINDOW_OFFSET_Y__MASK … #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) { … } #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL … #define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE … #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY … #define REG_A6XX_RB_LRZ_CNTL … #define A6XX_RB_LRZ_CNTL_ENABLE … #define REG_A7XX_RB_UNKNOWN_8899 … #define REG_A6XX_RB_Z_CLAMP_MIN … #define A6XX_RB_Z_CLAMP_MIN__MASK … #define A6XX_RB_Z_CLAMP_MIN__SHIFT … static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) { … } #define REG_A6XX_RB_Z_CLAMP_MAX … #define A6XX_RB_Z_CLAMP_MAX__MASK … #define A6XX_RB_Z_CLAMP_MAX__SHIFT … static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) { … } #define REG_A6XX_RB_UNKNOWN_88D0 … #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK … #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT … static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) { … } #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK … #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT … static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) { … } #define REG_A6XX_RB_BLIT_SCISSOR_TL … #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK … #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT … static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) { … } #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK … #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT … static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A6XX_RB_BLIT_SCISSOR_BR … #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK … #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT … static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) { … } #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK … #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT … static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A6XX_RB_BIN_CONTROL2 … #define A6XX_RB_BIN_CONTROL2_BINW__MASK … #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT … static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) { … } #define A6XX_RB_BIN_CONTROL2_BINH__MASK … #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT … static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) { … } #define REG_A6XX_RB_WINDOW_OFFSET2 … #define A6XX_RB_WINDOW_OFFSET2_X__MASK … #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT … static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) { … } #define A6XX_RB_WINDOW_OFFSET2_Y__MASK … #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT … static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) { … } #define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL … #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK … #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define REG_A6XX_RB_BLIT_BASE_GMEM … #define REG_A6XX_RB_BLIT_DST_INFO … #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK … #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT … static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) { … } #define A6XX_RB_BLIT_DST_INFO_FLAGS … #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK … #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT … static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK … #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK … #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_RB_BLIT_DST_INFO_UNK15 … #define REG_A6XX_RB_BLIT_DST … #define REG_A6XX_RB_BLIT_DST_PITCH … #define A6XX_RB_BLIT_DST_PITCH__MASK … #define A6XX_RB_BLIT_DST_PITCH__SHIFT … static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) { … } #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH … #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK … #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_RB_BLIT_FLAG_DST … #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH … #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK … #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT … static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) { … } #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK … #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 … #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 … #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 … #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 … #define REG_A6XX_RB_BLIT_INFO … #define A6XX_RB_BLIT_INFO_UNK0 … #define A6XX_RB_BLIT_INFO_GMEM … #define A6XX_RB_BLIT_INFO_SAMPLE_0 … #define A6XX_RB_BLIT_INFO_DEPTH … #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK … #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT … static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) { … } #define A6XX_RB_BLIT_INFO_LAST__MASK … #define A6XX_RB_BLIT_INFO_LAST__SHIFT … static inline uint32_t A6XX_RB_BLIT_INFO_LAST(uint32_t val) { … } #define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK … #define A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT … static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) { … } #define REG_A7XX_RB_UNKNOWN_88E4 … #define A7XX_RB_UNKNOWN_88E4_UNK0 … #define REG_A7XX_RB_CCU_CNTL2 … #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK … #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT … static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(uint32_t val) { … } #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK … #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT … static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(uint32_t val) { … } #define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK … #define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT … static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) { … } #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK … #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT … static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(uint32_t val) { … } #define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK … #define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT … static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) { … } #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK … #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT … static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET(uint32_t val) { … } #define REG_A6XX_RB_UNKNOWN_88F0 … #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE … #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH … #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK … #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT … static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { … } #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK … #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_RB_UNKNOWN_88F4 … #define REG_A7XX_RB_UNKNOWN_88F5 … #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE … #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH … #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK … #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT … static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { … } #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK … #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT … static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) { … } #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK … #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_RB_MRT_FLAG_BUFFER(i0) … static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { … } static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { … } #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK … #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT … static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { … } #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK … #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_RB_SAMPLE_COUNT_ADDR … #define REG_A6XX_RB_UNKNOWN_8A00 … #define REG_A6XX_RB_UNKNOWN_8A10 … #define REG_A6XX_RB_UNKNOWN_8A20 … #define REG_A6XX_RB_UNKNOWN_8A30 … #define REG_A6XX_RB_2D_BLIT_CNTL … #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK … #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT … static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) { … } #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN … #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK … #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT … static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) { … } #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR … #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK … #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_RB_2D_BLIT_CNTL_SCISSOR … #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK … #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT … static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) { … } #define A6XX_RB_2D_BLIT_CNTL_D24S8 … #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK … #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT … static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) { … } #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK … #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT … static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) { … } #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK … #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT … static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) { … } #define A6XX_RB_2D_BLIT_CNTL_UNK30 … #define REG_A6XX_RB_2D_UNKNOWN_8C01 … #define REG_A6XX_RB_2D_DST_INFO … #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK … #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK … #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT … static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) { … } #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK … #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A6XX_RB_2D_DST_INFO_FLAGS … #define A6XX_RB_2D_DST_INFO_SRGB … #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK … #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT … static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_RB_2D_DST_INFO_FILTER … #define A6XX_RB_2D_DST_INFO_UNK17 … #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE … #define A6XX_RB_2D_DST_INFO_UNK19 … #define A6XX_RB_2D_DST_INFO_UNK20 … #define A6XX_RB_2D_DST_INFO_UNK21 … #define A6XX_RB_2D_DST_INFO_UNK22 … #define A6XX_RB_2D_DST_INFO_UNK23__MASK … #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT … static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) { … } #define A6XX_RB_2D_DST_INFO_UNK28 … #define REG_A6XX_RB_2D_DST … #define REG_A6XX_RB_2D_DST_PITCH … #define A6XX_RB_2D_DST_PITCH__MASK … #define A6XX_RB_2D_DST_PITCH__SHIFT … static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) { … } #define REG_A6XX_RB_2D_DST_PLANE1 … #define REG_A6XX_RB_2D_DST_PLANE_PITCH … #define A6XX_RB_2D_DST_PLANE_PITCH__MASK … #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT … static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) { … } #define REG_A6XX_RB_2D_DST_PLANE2 … #define REG_A6XX_RB_2D_DST_FLAGS … #define REG_A6XX_RB_2D_DST_FLAGS_PITCH … #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK … #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT … static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) { … } #define REG_A6XX_RB_2D_DST_FLAGS_PLANE … #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH … #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK … #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT … static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) { … } #define REG_A6XX_RB_2D_SRC_SOLID_C0 … #define REG_A6XX_RB_2D_SRC_SOLID_C1 … #define REG_A6XX_RB_2D_SRC_SOLID_C2 … #define REG_A6XX_RB_2D_SRC_SOLID_C3 … #define REG_A6XX_RB_UNKNOWN_8E01 … #define REG_A6XX_RB_DBG_ECO_CNTL … #define REG_A6XX_RB_ADDR_MODE_CNTL … #define REG_A7XX_RB_UNKNOWN_8E06 … #define REG_A6XX_RB_CCU_CNTL … #define A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE … #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE … #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK … #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT … static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val) { … } #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK … #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT … static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) { … } #define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK … #define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT … static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) { … } #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK … #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT … static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) { … } #define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK … #define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT … static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) { … } #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK … #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT … static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) { … } #define REG_A7XX_RB_CCU_CNTL … #define A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE … #define A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE … #define REG_A6XX_RB_NC_MODE_CNTL … #define A6XX_RB_NC_MODE_CNTL_MODE … #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK … #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT … static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) { … } #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH … #define A6XX_RB_NC_MODE_CNTL_AMSBC … #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK … #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT … static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) { … } #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR … #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK … #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT … static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) { … } #define REG_A7XX_RB_UNKNOWN_8E09 … #define REG_A6XX_RB_PERFCTR_RB_SEL(i0) … #define REG_A6XX_RB_PERFCTR_CCU_SEL(i0) … #define REG_A6XX_RB_CMP_DBG_ECO_CNTL … #define REG_A6XX_RB_PERFCTR_CMP_SEL(i0) … #define REG_A7XX_RB_PERFCTR_UFC_SEL(i0) … #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST … #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD … #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE … #define REG_A6XX_RB_UNKNOWN_8E51 … #define REG_A7XX_RB_UNKNOWN_8E79 … #define REG_A6XX_VPC_GS_PARAM … #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK … #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT … static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) { … } #define REG_A6XX_VPC_VS_CLIP_CNTL … #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK … #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK … #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT … static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) { … } #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK … #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT … static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) { … } #define REG_A6XX_VPC_GS_CLIP_CNTL … #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK … #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK … #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT … static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) { … } #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK … #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT … static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) { … } #define REG_A6XX_VPC_DS_CLIP_CNTL … #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK … #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK … #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT … static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) { … } #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK … #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT … static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) { … } #define REG_A6XX_VPC_VS_CLIP_CNTL_V2 … #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK … #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT … static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) { … } #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK … #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT … static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) { … } #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK … #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT … static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) { … } #define REG_A6XX_VPC_GS_CLIP_CNTL_V2 … #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK … #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT … static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) { … } #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK … #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT … static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) { … } #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK … #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT … static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) { … } #define REG_A6XX_VPC_DS_CLIP_CNTL_V2 … #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK … #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT … static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) { … } #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK … #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT … static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) { … } #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK … #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT … static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) { … } #define REG_A6XX_VPC_VS_LAYER_CNTL … #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK … #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT … static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) { … } #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK … #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT … static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) { … } #define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK … #define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT … static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) { … } #define REG_A6XX_VPC_GS_LAYER_CNTL … #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK … #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT … static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) { … } #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK … #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT … static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) { … } #define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK … #define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT … static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) { … } #define REG_A6XX_VPC_DS_LAYER_CNTL … #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK … #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT … static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) { … } #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK … #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT … static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) { … } #define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK … #define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT … static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) { … } #define REG_A6XX_VPC_VS_LAYER_CNTL_V2 … #define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK … #define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT … static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) { … } #define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK … #define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT … static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) { … } #define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK … #define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT … static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) { … } #define REG_A6XX_VPC_GS_LAYER_CNTL_V2 … #define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK … #define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT … static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) { … } #define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK … #define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT … static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) { … } #define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK … #define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT … static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) { … } #define REG_A6XX_VPC_DS_LAYER_CNTL_V2 … #define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK … #define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT … static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) { … } #define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK … #define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT … static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) { … } #define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK … #define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT … static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) { … } #define REG_A6XX_VPC_UNKNOWN_9107 … #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD … #define A6XX_VPC_UNKNOWN_9107_UNK2 … #define REG_A6XX_VPC_POLYGON_MODE … #define A6XX_VPC_POLYGON_MODE_MODE__MASK … #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT … static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) { … } #define REG_A7XX_VPC_PRIMITIVE_CNTL_0 … #define A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART … #define A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST … #define A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING … #define A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 … #define REG_A7XX_VPC_PRIMITIVE_CNTL_5 … #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK … #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT … static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) { … } #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK … #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT … static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) { … } #define A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN … #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK … #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT … static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) { … } #define A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 … #define REG_A7XX_VPC_MULTIVIEW_MASK … #define REG_A7XX_VPC_MULTIVIEW_CNTL … #define A7XX_VPC_MULTIVIEW_CNTL_ENABLE … #define A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS … #define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK … #define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT … static inline uint32_t A7XX_VPC_MULTIVIEW_CNTL_VIEWS(uint32_t val) { … } #define REG_A6XX_VPC_VARYING_INTERP(i0) … static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { … } #define REG_A6XX_VPC_VARYING_PS_REPL(i0) … static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { … } #define REG_A6XX_VPC_UNKNOWN_9210 … #define REG_A6XX_VPC_UNKNOWN_9211 … #define REG_A6XX_VPC_VAR(i0) … static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { … } #define REG_A6XX_VPC_SO_CNTL … #define A6XX_VPC_SO_CNTL_ADDR__MASK … #define A6XX_VPC_SO_CNTL_ADDR__SHIFT … static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) { … } #define A6XX_VPC_SO_CNTL_RESET … #define REG_A6XX_VPC_SO_PROG … #define A6XX_VPC_SO_PROG_A_BUF__MASK … #define A6XX_VPC_SO_PROG_A_BUF__SHIFT … static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) { … } #define A6XX_VPC_SO_PROG_A_OFF__MASK … #define A6XX_VPC_SO_PROG_A_OFF__SHIFT … static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) { … } #define A6XX_VPC_SO_PROG_A_EN … #define A6XX_VPC_SO_PROG_B_BUF__MASK … #define A6XX_VPC_SO_PROG_B_BUF__SHIFT … static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) { … } #define A6XX_VPC_SO_PROG_B_OFF__MASK … #define A6XX_VPC_SO_PROG_B_OFF__SHIFT … static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) { … } #define A6XX_VPC_SO_PROG_B_EN … #define REG_A6XX_VPC_SO_STREAM_COUNTS … #define REG_A6XX_VPC_SO(i0) … static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { … } static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { … } static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { … } static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { … } static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { … } #define REG_A6XX_VPC_POINT_COORD_INVERT … #define A6XX_VPC_POINT_COORD_INVERT_INVERT … #define REG_A6XX_VPC_UNKNOWN_9300 … #define REG_A6XX_VPC_VS_PACK … #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK … #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) { … } #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK … #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT … static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) { … } #define A6XX_VPC_VS_PACK_PSIZELOC__MASK … #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT … static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) { … } #define A6XX_VPC_VS_PACK_EXTRAPOS__MASK … #define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT … static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val) { … } #define REG_A6XX_VPC_GS_PACK … #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK … #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) { … } #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK … #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT … static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) { … } #define A6XX_VPC_GS_PACK_PSIZELOC__MASK … #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT … static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) { … } #define A6XX_VPC_GS_PACK_EXTRAPOS__MASK … #define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT … static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val) { … } #define REG_A6XX_VPC_DS_PACK … #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK … #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) { … } #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK … #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT … static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) { … } #define A6XX_VPC_DS_PACK_PSIZELOC__MASK … #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT … static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) { … } #define A6XX_VPC_DS_PACK_EXTRAPOS__MASK … #define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT … static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val) { … } #define REG_A6XX_VPC_CNTL_0 … #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK … #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT … static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) { … } #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK … #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT … static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) { … } #define A6XX_VPC_CNTL_0_VARYING … #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK … #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT … static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) { … } #define REG_A6XX_VPC_SO_STREAM_CNTL … #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK … #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT … static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) { … } #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK … #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT … static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) { … } #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK … #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT … static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) { … } #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK … #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT … static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) { … } #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK … #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT … static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) { … } #define REG_A6XX_VPC_SO_DISABLE … #define A6XX_VPC_SO_DISABLE_DISABLE … #define REG_A7XX_VPC_POLYGON_MODE2 … #define A7XX_VPC_POLYGON_MODE2_MODE__MASK … #define A7XX_VPC_POLYGON_MODE2_MODE__SHIFT … static inline uint32_t A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val) { … } #define REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM … #define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK … #define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT … static inline uint32_t A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) { … } #define REG_A7XX_VPC_ATTR_BUF_BASE_GMEM … #define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK … #define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT … static inline uint32_t A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(uint32_t val) { … } #define REG_A7XX_PC_ATTR_BUF_SIZE_GMEM … #define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK … #define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT … static inline uint32_t A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) { … } #define REG_A6XX_VPC_DBG_ECO_CNTL … #define REG_A6XX_VPC_ADDR_MODE_CNTL … #define REG_A6XX_VPC_UNKNOWN_9602 … #define REG_A6XX_VPC_UNKNOWN_9603 … #define REG_A6XX_VPC_PERFCTR_VPC_SEL(i0) … #define REG_A7XX_VPC_PERFCTR_VPC_SEL(i0) … #define REG_A6XX_PC_TESS_NUM_VERTEX … #define REG_A6XX_PC_HS_INPUT_SIZE … #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK … #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT … static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) { … } #define A6XX_PC_HS_INPUT_SIZE_UNK13 … #define REG_A6XX_PC_TESS_CNTL … #define A6XX_PC_TESS_CNTL_SPACING__MASK … #define A6XX_PC_TESS_CNTL_SPACING__SHIFT … static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) { … } #define A6XX_PC_TESS_CNTL_OUTPUT__MASK … #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT … static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) { … } #define REG_A6XX_PC_RESTART_INDEX … #define REG_A6XX_PC_MODE_CNTL … #define REG_A6XX_PC_POWER_CNTL … #define REG_A6XX_PC_PS_CNTL … #define A6XX_PC_PS_CNTL_PRIMITIVEIDEN … #define REG_A6XX_PC_SO_STREAM_CNTL … #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK … #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT … static inline uint32_t A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) { … } #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL … #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN … #define REG_A6XX_PC_DRAW_CMD … #define A6XX_PC_DRAW_CMD_STATE_ID__MASK … #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) { … } #define REG_A6XX_PC_DISPATCH_CMD … #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK … #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) { … } #define REG_A6XX_PC_EVENT_CMD … #define A6XX_PC_EVENT_CMD_STATE_ID__MASK … #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) { … } #define A6XX_PC_EVENT_CMD_EVENT__MASK … #define A6XX_PC_EVENT_CMD_EVENT__SHIFT … static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) { … } #define REG_A6XX_PC_MARKER … #define REG_A6XX_PC_POLYGON_MODE … #define A6XX_PC_POLYGON_MODE_MODE__MASK … #define A6XX_PC_POLYGON_MODE_MODE__SHIFT … static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) { … } #define REG_A7XX_PC_POLYGON_MODE … #define A7XX_PC_POLYGON_MODE_MODE__MASK … #define A7XX_PC_POLYGON_MODE_MODE__SHIFT … static inline uint32_t A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) { … } #define REG_A6XX_PC_RASTER_CNTL … #define A6XX_PC_RASTER_CNTL_STREAM__MASK … #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT … static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) { … } #define A6XX_PC_RASTER_CNTL_DISCARD … #define REG_A7XX_PC_RASTER_CNTL … #define A7XX_PC_RASTER_CNTL_STREAM__MASK … #define A7XX_PC_RASTER_CNTL_STREAM__SHIFT … static inline uint32_t A7XX_PC_RASTER_CNTL_STREAM(uint32_t val) { … } #define A7XX_PC_RASTER_CNTL_DISCARD … #define REG_A7XX_PC_RASTER_CNTL_V2 … #define A7XX_PC_RASTER_CNTL_V2_STREAM__MASK … #define A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT … static inline uint32_t A7XX_PC_RASTER_CNTL_V2_STREAM(uint32_t val) { … } #define A7XX_PC_RASTER_CNTL_V2_DISCARD … #define REG_A7XX_PC_TESS_PARAM_SIZE … #define REG_A7XX_PC_TESS_FACTOR_SIZE … #define REG_A6XX_PC_PRIMITIVE_CNTL_0 … #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART … #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST … #define A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING … #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 … #define REG_A6XX_PC_VS_OUT_CNTL … #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK … #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) { … } #define A6XX_PC_VS_OUT_CNTL_PSIZE … #define A6XX_PC_VS_OUT_CNTL_LAYER … #define A6XX_PC_VS_OUT_CNTL_VIEW … #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID … #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK … #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_PC_VS_OUT_CNTL_SHADINGRATE … #define REG_A6XX_PC_GS_OUT_CNTL … #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK … #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) { … } #define A6XX_PC_GS_OUT_CNTL_PSIZE … #define A6XX_PC_GS_OUT_CNTL_LAYER … #define A6XX_PC_GS_OUT_CNTL_VIEW … #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID … #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK … #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_PC_GS_OUT_CNTL_SHADINGRATE … #define REG_A6XX_PC_HS_OUT_CNTL … #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK … #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) { … } #define A6XX_PC_HS_OUT_CNTL_PSIZE … #define A6XX_PC_HS_OUT_CNTL_LAYER … #define A6XX_PC_HS_OUT_CNTL_VIEW … #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID … #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK … #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_PC_HS_OUT_CNTL_SHADINGRATE … #define REG_A6XX_PC_DS_OUT_CNTL … #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK … #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) { … } #define A6XX_PC_DS_OUT_CNTL_PSIZE … #define A6XX_PC_DS_OUT_CNTL_LAYER … #define A6XX_PC_DS_OUT_CNTL_VIEW … #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID … #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK … #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT … static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) { … } #define A6XX_PC_DS_OUT_CNTL_SHADINGRATE … #define REG_A6XX_PC_PRIMITIVE_CNTL_5 … #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK … #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT … static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) { … } #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK … #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT … static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) { … } #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN … #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK … #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT … static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) { … } #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18 … #define REG_A6XX_PC_PRIMITIVE_CNTL_6 … #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK … #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT … static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) { … } #define REG_A6XX_PC_MULTIVIEW_CNTL … #define A6XX_PC_MULTIVIEW_CNTL_ENABLE … #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS … #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK … #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT … static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) { … } #define REG_A6XX_PC_MULTIVIEW_MASK … #define REG_A6XX_PC_2D_EVENT_CMD … #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK … #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT … static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) { … } #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK … #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) { … } #define REG_A6XX_PC_DBG_ECO_CNTL … #define REG_A6XX_PC_ADDR_MODE_CNTL … #define REG_A6XX_PC_DRAW_INDX_BASE … #define REG_A6XX_PC_DRAW_FIRST_INDX … #define REG_A6XX_PC_DRAW_MAX_INDICES … #define REG_A6XX_PC_TESSFACTOR_ADDR … #define REG_A7XX_PC_TESSFACTOR_ADDR … #define REG_A6XX_PC_DRAW_INITIATOR … #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK … #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT … static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) { … } #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK … #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT … static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK … #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT … static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK … #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT … static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) { … } #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK … #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT … static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) { … } #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE … #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE … #define REG_A6XX_PC_DRAW_NUM_INSTANCES … #define REG_A6XX_PC_DRAW_NUM_INDICES … #define REG_A6XX_PC_VSTREAM_CONTROL … #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK … #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT … static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) { … } #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK … #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT … static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) { … } #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK … #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT … static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) { … } #define REG_A6XX_PC_BIN_PRIM_STRM … #define REG_A6XX_PC_BIN_DRAW_STRM … #define REG_A6XX_PC_VISIBILITY_OVERRIDE … #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE … #define REG_A7XX_PC_UNKNOWN_9E24 … #define REG_A6XX_PC_PERFCTR_PC_SEL(i0) … #define REG_A7XX_PC_PERFCTR_PC_SEL(i0) … #define REG_A6XX_PC_UNKNOWN_9E72 … #define REG_A6XX_VFD_CONTROL_0 … #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK … #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) { … } #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK … #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) { … } #define REG_A6XX_VFD_CONTROL_1 … #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK … #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) { … } #define A6XX_VFD_CONTROL_1_REGID4INST__MASK … #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) { … } #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK … #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) { … } #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK … #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) { … } #define REG_A6XX_VFD_CONTROL_2 … #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK … #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) { … } #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK … #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) { … } #define REG_A6XX_VFD_CONTROL_3 … #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK … #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) { … } #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK … #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) { … } #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK … #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) { … } #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK … #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) { … } #define REG_A6XX_VFD_CONTROL_4 … #define A6XX_VFD_CONTROL_4_UNK0__MASK … #define A6XX_VFD_CONTROL_4_UNK0__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) { … } #define REG_A6XX_VFD_CONTROL_5 … #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK … #define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val) { … } #define A6XX_VFD_CONTROL_5_UNK8__MASK … #define A6XX_VFD_CONTROL_5_UNK8__SHIFT … static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) { … } #define REG_A6XX_VFD_CONTROL_6 … #define A6XX_VFD_CONTROL_6_PRIMID4PSEN … #define REG_A6XX_VFD_MODE_CNTL … #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK … #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT … static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) { … } #define REG_A6XX_VFD_MULTIVIEW_CNTL … #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE … #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS … #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK … #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT … static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) { … } #define REG_A6XX_VFD_ADD_OFFSET … #define A6XX_VFD_ADD_OFFSET_VERTEX … #define A6XX_VFD_ADD_OFFSET_INSTANCE … #define REG_A6XX_VFD_INDEX_OFFSET … #define REG_A6XX_VFD_INSTANCE_START_OFFSET … #define REG_A6XX_VFD_FETCH(i0) … static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { … } static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { … } static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { … } #define REG_A6XX_VFD_DECODE(i0) … static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { … } #define A6XX_VFD_DECODE_INSTR_IDX__MASK … #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT … static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) { … } #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK … #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT … static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) { … } #define A6XX_VFD_DECODE_INSTR_INSTANCED … #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK … #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT … static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) { … } #define A6XX_VFD_DECODE_INSTR_SWAP__MASK … #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT … static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) { … } #define A6XX_VFD_DECODE_INSTR_UNK30 … #define A6XX_VFD_DECODE_INSTR_FLOAT … static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { … } #define REG_A6XX_VFD_DEST_CNTL(i0) … static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { … } #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK … #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT … static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) { … } #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK … #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT … static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) { … } #define REG_A6XX_VFD_POWER_CNTL … #define REG_A7XX_VFD_UNKNOWN_A600 … #define REG_A6XX_VFD_ADDR_MODE_CNTL … #define REG_A6XX_VFD_PERFCTR_VFD_SEL(i0) … #define REG_A7XX_VFD_PERFCTR_VFD_SEL(i0) … #define REG_A6XX_SP_VS_CTRL_REG0 … #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK … #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_VS_CTRL_REG0_UNK13 … #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK … #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS … #define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE … #define REG_A6XX_SP_VS_BRANCH_COND … #define REG_A6XX_SP_VS_PRIMITIVE_CNTL … #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK … #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT … static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) { … } #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK … #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT … static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) { … } #define REG_A6XX_SP_VS_OUT(i0) … static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { … } #define A6XX_SP_VS_OUT_REG_A_REGID__MASK … #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) { … } #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK … #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A6XX_SP_VS_OUT_REG_B_REGID__MASK … #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) { … } #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK … #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A6XX_SP_VS_VPC_DST(i0) … static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { … } #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK … #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK … #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK … #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK … #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET … #define REG_A6XX_SP_VS_OBJ_START … #define REG_A6XX_SP_VS_PVT_MEM_PARAM … #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A6XX_SP_VS_PVT_MEM_ADDR … #define REG_A6XX_SP_VS_PVT_MEM_SIZE … #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT … #define REG_A6XX_SP_VS_TEX_COUNT … #define REG_A6XX_SP_VS_CONFIG … #define A6XX_SP_VS_CONFIG_BINDLESS_TEX … #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP … #define A6XX_SP_VS_CONFIG_BINDLESS_IBO … #define A6XX_SP_VS_CONFIG_BINDLESS_UBO … #define A6XX_SP_VS_CONFIG_ENABLED … #define A6XX_SP_VS_CONFIG_NTEX__MASK … #define A6XX_SP_VS_CONFIG_NTEX__SHIFT … static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) { … } #define A6XX_SP_VS_CONFIG_NSAMP__MASK … #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT … static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) { … } #define A6XX_SP_VS_CONFIG_NIBO__MASK … #define A6XX_SP_VS_CONFIG_NIBO__SHIFT … static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) { … } #define REG_A6XX_SP_VS_INSTRLEN … #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET … #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK … #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT … static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { … } #define REG_A7XX_SP_VS_VGPR_CONFIG … #define REG_A6XX_SP_HS_CTRL_REG0 … #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK … #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_HS_CTRL_REG0_UNK13 … #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK … #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE … #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE … #define REG_A6XX_SP_HS_BRANCH_COND … #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET … #define REG_A6XX_SP_HS_OBJ_START … #define REG_A6XX_SP_HS_PVT_MEM_PARAM … #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A6XX_SP_HS_PVT_MEM_ADDR … #define REG_A6XX_SP_HS_PVT_MEM_SIZE … #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT … #define REG_A6XX_SP_HS_TEX_COUNT … #define REG_A6XX_SP_HS_CONFIG … #define A6XX_SP_HS_CONFIG_BINDLESS_TEX … #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP … #define A6XX_SP_HS_CONFIG_BINDLESS_IBO … #define A6XX_SP_HS_CONFIG_BINDLESS_UBO … #define A6XX_SP_HS_CONFIG_ENABLED … #define A6XX_SP_HS_CONFIG_NTEX__MASK … #define A6XX_SP_HS_CONFIG_NTEX__SHIFT … static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) { … } #define A6XX_SP_HS_CONFIG_NSAMP__MASK … #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT … static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) { … } #define A6XX_SP_HS_CONFIG_NIBO__MASK … #define A6XX_SP_HS_CONFIG_NIBO__SHIFT … static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) { … } #define REG_A6XX_SP_HS_INSTRLEN … #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET … #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK … #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT … static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { … } #define REG_A7XX_SP_HS_VGPR_CONFIG … #define REG_A6XX_SP_DS_CTRL_REG0 … #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK … #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_DS_CTRL_REG0_UNK13 … #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK … #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE … #define REG_A6XX_SP_DS_BRANCH_COND … #define REG_A6XX_SP_DS_PRIMITIVE_CNTL … #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK … #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT … static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) { … } #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK … #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT … static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) { … } #define REG_A6XX_SP_DS_OUT(i0) … static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { … } #define A6XX_SP_DS_OUT_REG_A_REGID__MASK … #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) { … } #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK … #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A6XX_SP_DS_OUT_REG_B_REGID__MASK … #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) { … } #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK … #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A6XX_SP_DS_VPC_DST(i0) … static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { … } #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK … #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK … #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK … #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK … #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET … #define REG_A6XX_SP_DS_OBJ_START … #define REG_A6XX_SP_DS_PVT_MEM_PARAM … #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A6XX_SP_DS_PVT_MEM_ADDR … #define REG_A6XX_SP_DS_PVT_MEM_SIZE … #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT … #define REG_A6XX_SP_DS_TEX_COUNT … #define REG_A6XX_SP_DS_CONFIG … #define A6XX_SP_DS_CONFIG_BINDLESS_TEX … #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP … #define A6XX_SP_DS_CONFIG_BINDLESS_IBO … #define A6XX_SP_DS_CONFIG_BINDLESS_UBO … #define A6XX_SP_DS_CONFIG_ENABLED … #define A6XX_SP_DS_CONFIG_NTEX__MASK … #define A6XX_SP_DS_CONFIG_NTEX__SHIFT … static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) { … } #define A6XX_SP_DS_CONFIG_NSAMP__MASK … #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT … static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) { … } #define A6XX_SP_DS_CONFIG_NIBO__MASK … #define A6XX_SP_DS_CONFIG_NIBO__SHIFT … static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) { … } #define REG_A6XX_SP_DS_INSTRLEN … #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET … #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK … #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT … static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { … } #define REG_A7XX_SP_DS_VGPR_CONFIG … #define REG_A6XX_SP_GS_CTRL_REG0 … #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK … #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_GS_CTRL_REG0_UNK13 … #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK … #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE … #define REG_A6XX_SP_GS_PRIM_SIZE … #define REG_A6XX_SP_GS_BRANCH_COND … #define REG_A6XX_SP_GS_PRIMITIVE_CNTL … #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK … #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT … static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) { … } #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK … #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT … static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) { … } #define REG_A6XX_SP_GS_OUT(i0) … static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { … } #define A6XX_SP_GS_OUT_REG_A_REGID__MASK … #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) { … } #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK … #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A6XX_SP_GS_OUT_REG_B_REGID__MASK … #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) { … } #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK … #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A6XX_SP_GS_VPC_DST(i0) … static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { … } #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK … #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK … #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK … #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK … #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET … #define REG_A6XX_SP_GS_OBJ_START … #define REG_A6XX_SP_GS_PVT_MEM_PARAM … #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A6XX_SP_GS_PVT_MEM_ADDR … #define REG_A6XX_SP_GS_PVT_MEM_SIZE … #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT … #define REG_A6XX_SP_GS_TEX_COUNT … #define REG_A6XX_SP_GS_CONFIG … #define A6XX_SP_GS_CONFIG_BINDLESS_TEX … #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP … #define A6XX_SP_GS_CONFIG_BINDLESS_IBO … #define A6XX_SP_GS_CONFIG_BINDLESS_UBO … #define A6XX_SP_GS_CONFIG_ENABLED … #define A6XX_SP_GS_CONFIG_NTEX__MASK … #define A6XX_SP_GS_CONFIG_NTEX__SHIFT … static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) { … } #define A6XX_SP_GS_CONFIG_NSAMP__MASK … #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT … static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) { … } #define A6XX_SP_GS_CONFIG_NIBO__MASK … #define A6XX_SP_GS_CONFIG_NIBO__SHIFT … static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) { … } #define REG_A6XX_SP_GS_INSTRLEN … #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET … #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK … #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT … static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { … } #define REG_A7XX_SP_GS_VGPR_CONFIG … #define REG_A6XX_SP_VS_TEX_SAMP … #define REG_A6XX_SP_HS_TEX_SAMP … #define REG_A6XX_SP_DS_TEX_SAMP … #define REG_A6XX_SP_GS_TEX_SAMP … #define REG_A6XX_SP_VS_TEX_CONST … #define REG_A6XX_SP_HS_TEX_CONST … #define REG_A6XX_SP_DS_TEX_CONST … #define REG_A6XX_SP_GS_TEX_CONST … #define REG_A6XX_SP_FS_CTRL_REG0 … #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK … #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_FS_CTRL_REG0_UNK13 … #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK … #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK … #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) { … } #define A6XX_SP_FS_CTRL_REG0_UNK21 … #define A6XX_SP_FS_CTRL_REG0_VARYING … #define A6XX_SP_FS_CTRL_REG0_LODPIXMASK … #define A6XX_SP_FS_CTRL_REG0_UNK24 … #define A6XX_SP_FS_CTRL_REG0_UNK25 … #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE … #define A6XX_SP_FS_CTRL_REG0_UNK27 … #define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE … #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS … #define REG_A6XX_SP_FS_BRANCH_COND … #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET … #define REG_A6XX_SP_FS_OBJ_START … #define REG_A6XX_SP_FS_PVT_MEM_PARAM … #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A6XX_SP_FS_PVT_MEM_ADDR … #define REG_A6XX_SP_FS_PVT_MEM_SIZE … #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT … #define REG_A6XX_SP_BLEND_CNTL … #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK … #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT … static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) { … } #define A6XX_SP_BLEND_CNTL_UNK8 … #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE … #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE … #define REG_A6XX_SP_SRGB_CNTL … #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 … #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 … #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 … #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 … #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 … #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 … #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 … #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 … #define REG_A6XX_SP_FS_RENDER_COMPONENTS … #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) { … } #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) { … } #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) { … } #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) { … } #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) { … } #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) { … } #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) { … } #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK … #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT … static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) { … } #define REG_A6XX_SP_FS_OUTPUT_CNTL0 … #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE … #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK … #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT … static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) { … } #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK … #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT … static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) { … } #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK … #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT … static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) { … } #define REG_A6XX_SP_FS_OUTPUT_CNTL1 … #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK … #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT … static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) { … } #define REG_A6XX_SP_FS_OUTPUT(i0) … static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { … } #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK … #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT … static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) { … } #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION … #define REG_A6XX_SP_FS_MRT(i0) … static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { … } #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK … #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_SP_FS_MRT_REG_COLOR_SINT … #define A6XX_SP_FS_MRT_REG_COLOR_UINT … #define A6XX_SP_FS_MRT_REG_UNK10 … #define REG_A6XX_SP_FS_PREFETCH_CNTL … #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK … #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) { … } #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE … #define A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD … #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT … #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK … #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(uint32_t val) { … } #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK … #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(uint32_t val) { … } #define REG_A6XX_SP_FS_PREFETCH(i0) … static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { … } #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK … #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) { … } #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK … #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) { … } #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK … #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) { … } #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK … #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) { … } #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK … #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) { … } #define A6XX_SP_FS_PREFETCH_CMD_HALF … #define A6XX_SP_FS_PREFETCH_CMD_UNK27 … #define A6XX_SP_FS_PREFETCH_CMD_BINDLESS … #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK … #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT … static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) { … } #define REG_A7XX_SP_FS_PREFETCH(i0) … static inline uint32_t REG_A7XX_SP_FS_PREFETCH_CMD(uint32_t i0) { … } #define A7XX_SP_FS_PREFETCH_CMD_SRC__MASK … #define A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT … static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) { … } #define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK … #define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT … static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) { … } #define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK … #define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT … static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) { … } #define A7XX_SP_FS_PREFETCH_CMD_DST__MASK … #define A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT … static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) { … } #define A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK … #define A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT … static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) { … } #define A7XX_SP_FS_PREFETCH_CMD_HALF … #define A7XX_SP_FS_PREFETCH_CMD_BINDLESS … #define A7XX_SP_FS_PREFETCH_CMD_CMD__MASK … #define A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT … static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) { … } #define REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0) … static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { … } #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK … #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT … static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) { … } #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK … #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT … static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) { … } #define REG_A6XX_SP_FS_TEX_COUNT … #define REG_A6XX_SP_UNKNOWN_A9A8 … #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET … #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK … #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT … static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { … } #define REG_A6XX_SP_CS_CTRL_REG0 … #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK … #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A6XX_SP_CS_CTRL_REG0_UNK13 … #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK … #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT … static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) { … } #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK … #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) { … } #define A6XX_SP_CS_CTRL_REG0_UNK21 … #define A6XX_SP_CS_CTRL_REG0_UNK22 … #define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE … #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS … #define REG_A6XX_SP_CS_UNKNOWN_A9B1 … #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK … #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT … static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) { … } #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 … #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 … #define REG_A6XX_SP_CS_BRANCH_COND … #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET … #define REG_A6XX_SP_CS_OBJ_START … #define REG_A6XX_SP_CS_PVT_MEM_PARAM … #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK … #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT … static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { … } #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK … #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A6XX_SP_CS_PVT_MEM_ADDR … #define REG_A6XX_SP_CS_PVT_MEM_SIZE … #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK … #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT … static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { … } #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT … #define REG_A6XX_SP_CS_TEX_COUNT … #define REG_A6XX_SP_CS_CONFIG … #define A6XX_SP_CS_CONFIG_BINDLESS_TEX … #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP … #define A6XX_SP_CS_CONFIG_BINDLESS_IBO … #define A6XX_SP_CS_CONFIG_BINDLESS_UBO … #define A6XX_SP_CS_CONFIG_ENABLED … #define A6XX_SP_CS_CONFIG_NTEX__MASK … #define A6XX_SP_CS_CONFIG_NTEX__SHIFT … static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) { … } #define A6XX_SP_CS_CONFIG_NSAMP__MASK … #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT … static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) { … } #define A6XX_SP_CS_CONFIG_NIBO__MASK … #define A6XX_SP_CS_CONFIG_NIBO__SHIFT … static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) { … } #define REG_A6XX_SP_CS_INSTRLEN … #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET … #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK … #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT … static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { … } #define REG_A7XX_SP_CS_UNKNOWN_A9BE … #define REG_A7XX_SP_CS_VGPR_CONFIG … #define REG_A6XX_SP_CS_CNTL_0 … #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK … #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT … static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) { … } #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK … #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT … static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) { … } #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK … #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT … static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) { … } #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK … #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT … static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) { … } #define REG_A6XX_SP_CS_CNTL_1 … #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK … #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT … static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) { … } #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE … #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK … #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT … static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) { … } #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR … #define REG_A7XX_SP_CS_CNTL_1 … #define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK … #define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT … static inline uint32_t A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) { … } #define A7XX_SP_CS_CNTL_1_THREADSIZE__MASK … #define A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT … static inline uint32_t A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) { … } #define A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR … #define A7XX_SP_CS_CNTL_1_UNK15 … #define REG_A6XX_SP_FS_TEX_SAMP … #define REG_A6XX_SP_CS_TEX_SAMP … #define REG_A6XX_SP_FS_TEX_CONST … #define REG_A6XX_SP_CS_TEX_CONST … #define REG_A6XX_SP_CS_BINDLESS_BASE(i0) … static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { … } #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK … #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT … static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { … } #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK … #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT … static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { … } #define REG_A7XX_SP_CS_BINDLESS_BASE(i0) … static inline uint32_t REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { … } #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK … #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT … static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { … } #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK … #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT … static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { … } #define REG_A6XX_SP_CS_IBO … #define REG_A6XX_SP_CS_IBO_COUNT … #define REG_A7XX_SP_FS_VGPR_CONFIG … #define REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL … #define A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED … #define REG_A7XX_SP_PS_ALIASED_COMPONENTS … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT0(uint32_t val) { … } #define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT1(uint32_t val) { … } #define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT2(uint32_t val) { … } #define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT3(uint32_t val) { … } #define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT4(uint32_t val) { … } #define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT5(uint32_t val) { … } #define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT6(uint32_t val) { … } #define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK … #define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT … static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT7(uint32_t val) { … } #define REG_A6XX_SP_UNKNOWN_AAF2 … #define REG_A6XX_SP_MODE_CONTROL … #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE … #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK … #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT … static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) { … } #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE … #define REG_A7XX_SP_UNKNOWN_AB01 … #define REG_A7XX_SP_UNKNOWN_AB02 … #define REG_A6XX_SP_FS_CONFIG … #define A6XX_SP_FS_CONFIG_BINDLESS_TEX … #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP … #define A6XX_SP_FS_CONFIG_BINDLESS_IBO … #define A6XX_SP_FS_CONFIG_BINDLESS_UBO … #define A6XX_SP_FS_CONFIG_ENABLED … #define A6XX_SP_FS_CONFIG_NTEX__MASK … #define A6XX_SP_FS_CONFIG_NTEX__SHIFT … static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) { … } #define A6XX_SP_FS_CONFIG_NSAMP__MASK … #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT … static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) { … } #define A6XX_SP_FS_CONFIG_NIBO__MASK … #define A6XX_SP_FS_CONFIG_NIBO__SHIFT … static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) { … } #define REG_A6XX_SP_FS_INSTRLEN … #define REG_A6XX_SP_BINDLESS_BASE(i0) … static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { … } #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK … #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT … static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { … } #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK … #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT … static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { … } #define REG_A7XX_SP_BINDLESS_BASE(i0) … static inline uint32_t REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { … } #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK … #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT … static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { … } #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK … #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT … static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { … } #define REG_A6XX_SP_IBO … #define REG_A6XX_SP_IBO_COUNT … #define REG_A7XX_SP_UNKNOWN_AB22 … #define REG_A6XX_SP_2D_DST_FORMAT … #define A6XX_SP_2D_DST_FORMAT_NORM … #define A6XX_SP_2D_DST_FORMAT_SINT … #define A6XX_SP_2D_DST_FORMAT_UINT … #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK … #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_SP_2D_DST_FORMAT_SRGB … #define A6XX_SP_2D_DST_FORMAT_MASK__MASK … #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT … static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) { … } #define REG_A7XX_SP_2D_DST_FORMAT … #define A7XX_SP_2D_DST_FORMAT_NORM … #define A7XX_SP_2D_DST_FORMAT_SINT … #define A7XX_SP_2D_DST_FORMAT_UINT … #define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK … #define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT … static inline uint32_t A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) { … } #define A7XX_SP_2D_DST_FORMAT_SRGB … #define A7XX_SP_2D_DST_FORMAT_MASK__MASK … #define A7XX_SP_2D_DST_FORMAT_MASK__SHIFT … static inline uint32_t A7XX_SP_2D_DST_FORMAT_MASK(uint32_t val) { … } #define REG_A6XX_SP_DBG_ECO_CNTL … #define REG_A6XX_SP_ADDR_MODE_CNTL … #define REG_A6XX_SP_NC_MODE_CNTL … #define REG_A6XX_SP_CHICKEN_BITS … #define REG_A6XX_SP_FLOAT_CNTL … #define A6XX_SP_FLOAT_CNTL_F16_NO_INF … #define REG_A7XX_SP_UNKNOWN_AE06 … #define REG_A7XX_SP_UNKNOWN_AE08 … #define REG_A7XX_SP_UNKNOWN_AE09 … #define REG_A7XX_SP_UNKNOWN_AE0A … #define REG_A6XX_SP_PERFCTR_ENABLE … #define A6XX_SP_PERFCTR_ENABLE_VS … #define A6XX_SP_PERFCTR_ENABLE_HS … #define A6XX_SP_PERFCTR_ENABLE_DS … #define A6XX_SP_PERFCTR_ENABLE_GS … #define A6XX_SP_PERFCTR_ENABLE_FS … #define A6XX_SP_PERFCTR_ENABLE_CS … #define REG_A6XX_SP_PERFCTR_SP_SEL(i0) … #define REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0) … #define REG_A7XX_SP_UNKNOWN_AE6A … #define REG_A7XX_SP_UNKNOWN_AE6B … #define REG_A7XX_SP_UNKNOWN_AE6C … #define REG_A7XX_SP_READ_SEL … #define A7XX_SP_READ_SEL_LOCATION__MASK … #define A7XX_SP_READ_SEL_LOCATION__SHIFT … static inline uint32_t A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val) { … } #define A7XX_SP_READ_SEL_PIPE__MASK … #define A7XX_SP_READ_SEL_PIPE__SHIFT … static inline uint32_t A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val) { … } #define A7XX_SP_READ_SEL_STATETYPE__MASK … #define A7XX_SP_READ_SEL_STATETYPE__SHIFT … static inline uint32_t A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val) { … } #define A7XX_SP_READ_SEL_USPTP__MASK … #define A7XX_SP_READ_SEL_USPTP__SHIFT … static inline uint32_t A7XX_SP_READ_SEL_USPTP(uint32_t val) { … } #define A7XX_SP_READ_SEL_SPTP__MASK … #define A7XX_SP_READ_SEL_SPTP__SHIFT … static inline uint32_t A7XX_SP_READ_SEL_SPTP(uint32_t val) { … } #define REG_A7XX_SP_DBG_CNTL … #define REG_A7XX_SP_UNKNOWN_AE73 … #define REG_A7XX_SP_PERFCTR_SP_SEL(i0) … #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE … #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR … #define REG_A6XX_SP_UNKNOWN_B182 … #define REG_A6XX_SP_UNKNOWN_B183 … #define REG_A6XX_SP_UNKNOWN_B190 … #define REG_A6XX_SP_UNKNOWN_B191 … #define REG_A6XX_SP_TP_RAS_MSAA_CNTL … #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK … #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK … #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT … static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) { … } #define REG_A6XX_SP_TP_DEST_MSAA_CNTL … #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK … #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT … static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE … #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR … #define REG_A6XX_SP_TP_SAMPLE_CONFIG … #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 … #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE … #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { … } #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { … } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK … #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT … static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { … } #define REG_A6XX_SP_TP_WINDOW_OFFSET … #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK … #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) { … } #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK … #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) { … } #define REG_A6XX_SP_TP_MODE_CNTL … #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK … #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT … static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) { … } #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK … #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT … static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) { … } #define REG_A7XX_SP_UNKNOWN_B310 … #define REG_A6XX_SP_PS_2D_SRC_INFO … #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK … #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) { … } #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK … #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) { … } #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK … #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A6XX_SP_PS_2D_SRC_INFO_FLAGS … #define A6XX_SP_PS_2D_SRC_INFO_SRGB … #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK … #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_SP_PS_2D_SRC_INFO_FILTER … #define A6XX_SP_PS_2D_SRC_INFO_UNK17 … #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE … #define A6XX_SP_PS_2D_SRC_INFO_UNK19 … #define A6XX_SP_PS_2D_SRC_INFO_UNK20 … #define A6XX_SP_PS_2D_SRC_INFO_UNK21 … #define A6XX_SP_PS_2D_SRC_INFO_UNK22 … #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK … #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) { … } #define A6XX_SP_PS_2D_SRC_INFO_UNK28 … #define REG_A6XX_SP_PS_2D_SRC_SIZE … #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK … #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) { … } #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK … #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) { … } #define REG_A6XX_SP_PS_2D_SRC … #define REG_A6XX_SP_PS_2D_SRC_PITCH … #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK … #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) { … } #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK … #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) { … } #define REG_A7XX_SP_PS_2D_SRC_INFO … #define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK … #define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) { … } #define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK … #define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) { … } #define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK … #define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A7XX_SP_PS_2D_SRC_INFO_FLAGS … #define A7XX_SP_PS_2D_SRC_INFO_SRGB … #define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK … #define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) { … } #define A7XX_SP_PS_2D_SRC_INFO_FILTER … #define A7XX_SP_PS_2D_SRC_INFO_UNK17 … #define A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE … #define A7XX_SP_PS_2D_SRC_INFO_UNK19 … #define A7XX_SP_PS_2D_SRC_INFO_UNK20 … #define A7XX_SP_PS_2D_SRC_INFO_UNK21 … #define A7XX_SP_PS_2D_SRC_INFO_UNK22 … #define A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK … #define A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) { … } #define A7XX_SP_PS_2D_SRC_INFO_UNK28 … #define REG_A7XX_SP_PS_2D_SRC_SIZE … #define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK … #define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) { … } #define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK … #define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) { … } #define REG_A7XX_SP_PS_2D_SRC … #define REG_A7XX_SP_PS_2D_SRC_PITCH … #define A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK … #define A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) { … } #define A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK … #define A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) { … } #define REG_A6XX_SP_PS_2D_SRC_PLANE1 … #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH … #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK … #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) { … } #define REG_A6XX_SP_PS_2D_SRC_PLANE2 … #define REG_A7XX_SP_PS_2D_SRC_PLANE1 … #define REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH … #define A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK … #define A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) { … } #define REG_A7XX_SP_PS_2D_SRC_PLANE2 … #define REG_A6XX_SP_PS_2D_SRC_FLAGS … #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH … #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK … #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT … static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) { … } #define REG_A7XX_SP_PS_2D_SRC_FLAGS … #define REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH … #define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK … #define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT … static inline uint32_t A7XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) { … } #define REG_A6XX_SP_PS_UNKNOWN_B4CD … #define REG_A6XX_SP_PS_UNKNOWN_B4CE … #define REG_A6XX_SP_PS_UNKNOWN_B4CF … #define REG_A6XX_SP_PS_UNKNOWN_B4D0 … #define REG_A6XX_SP_WINDOW_OFFSET … #define A6XX_SP_WINDOW_OFFSET_X__MASK … #define A6XX_SP_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) { … } #define A6XX_SP_WINDOW_OFFSET_Y__MASK … #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) { … } #define REG_A7XX_SP_PS_UNKNOWN_B4CD … #define REG_A7XX_SP_PS_UNKNOWN_B4CE … #define REG_A7XX_SP_PS_UNKNOWN_B4CF … #define REG_A7XX_SP_PS_UNKNOWN_B4D0 … #define REG_A7XX_SP_PS_2D_WINDOW_OFFSET … #define A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK … #define A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_X(uint32_t val) { … } #define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK … #define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_Y(uint32_t val) { … } #define REG_A7XX_SP_PS_UNKNOWN_B2D2 … #define REG_A7XX_SP_WINDOW_OFFSET … #define A7XX_SP_WINDOW_OFFSET_X__MASK … #define A7XX_SP_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A7XX_SP_WINDOW_OFFSET_X(uint32_t val) { … } #define A7XX_SP_WINDOW_OFFSET_Y__MASK … #define A7XX_SP_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A7XX_SP_WINDOW_OFFSET_Y(uint32_t val) { … } #define REG_A6XX_TPL1_DBG_ECO_CNTL … #define REG_A6XX_TPL1_ADDR_MODE_CNTL … #define REG_A6XX_TPL1_DBG_ECO_CNTL1 … #define REG_A6XX_TPL1_NC_MODE_CNTL … #define A6XX_TPL1_NC_MODE_CNTL_MODE … #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK … #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT … static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) { … } #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH … #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK … #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT … static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) { … } #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK … #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT … static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) { … } #define REG_A6XX_TPL1_UNKNOWN_B605 … #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 … #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 … #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 … #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 … #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 … #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 … #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 … #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 … #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 … #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 … #define REG_A6XX_TPL1_PERFCTR_TP_SEL(i0) … #define REG_A6XX_HLSQ_VS_CNTL … #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK … #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) { … } #define A6XX_HLSQ_VS_CNTL_ENABLED … #define A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A6XX_HLSQ_HS_CNTL … #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK … #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) { … } #define A6XX_HLSQ_HS_CNTL_ENABLED … #define A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A6XX_HLSQ_DS_CNTL … #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK … #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) { … } #define A6XX_HLSQ_DS_CNTL_ENABLED … #define A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A6XX_HLSQ_GS_CNTL … #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK … #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) { … } #define A6XX_HLSQ_GS_CNTL_ENABLED … #define A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_VS_CNTL … #define A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK … #define A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A7XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) { … } #define A7XX_HLSQ_VS_CNTL_ENABLED … #define A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_HS_CNTL … #define A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK … #define A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A7XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) { … } #define A7XX_HLSQ_HS_CNTL_ENABLED … #define A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_DS_CNTL … #define A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK … #define A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A7XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) { … } #define A7XX_HLSQ_DS_CNTL_ENABLED … #define A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_GS_CNTL … #define A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK … #define A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A7XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) { … } #define A7XX_HLSQ_GS_CNTL_ENABLED … #define A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_FS_UNKNOWN_A9AA … #define A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE … #define REG_A7XX_HLSQ_UNKNOWN_A9AC … #define REG_A7XX_HLSQ_UNKNOWN_A9AD … #define REG_A7XX_HLSQ_UNKNOWN_A9AE … #define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK … #define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT … static inline uint32_t A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(uint32_t val) { … } #define A7XX_HLSQ_UNKNOWN_A9AE_UNK8 … #define A7XX_HLSQ_UNKNOWN_A9AE_UNK9 … #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD … #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR … #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA … #define REG_A6XX_HLSQ_FS_CNTL_0 … #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK … #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT … static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) { … } #define A6XX_HLSQ_FS_CNTL_0_VARYINGS … #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK … #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT … static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) { … } #define REG_A6XX_HLSQ_UNKNOWN_B981 … #define REG_A6XX_HLSQ_CONTROL_1_REG … #define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK … #define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) { … } #define REG_A6XX_HLSQ_CONTROL_2_REG … #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK … #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK … #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK … #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK … #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) { … } #define REG_A6XX_HLSQ_CONTROL_3_REG … #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK … #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK … #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK … #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK … #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) { … } #define REG_A6XX_HLSQ_CONTROL_4_REG … #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK … #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK … #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK … #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK … #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) { … } #define REG_A6XX_HLSQ_CONTROL_5_REG … #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK … #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) { … } #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK … #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT … static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_CNTL … #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK … #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) { … } #define A6XX_HLSQ_CS_CNTL_ENABLED … #define A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_FS_CNTL_0 … #define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK … #define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT … static inline uint32_t A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) { … } #define A7XX_HLSQ_FS_CNTL_0_VARYINGS … #define A7XX_HLSQ_FS_CNTL_0_UNK2__MASK … #define A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT … static inline uint32_t A7XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) { … } #define REG_A7XX_HLSQ_CONTROL_1_REG … #define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK … #define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) { … } #define REG_A7XX_HLSQ_CONTROL_2_REG … #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK … #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK … #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK … #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK … #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) { … } #define REG_A7XX_HLSQ_CONTROL_3_REG … #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK … #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK … #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK … #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK … #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) { … } #define REG_A7XX_HLSQ_CONTROL_4_REG … #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK … #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK … #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK … #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK … #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) { … } #define REG_A7XX_HLSQ_CONTROL_5_REG … #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK … #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) { … } #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK … #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT … static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_CNTL … #define A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK … #define A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A7XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) { … } #define A7XX_HLSQ_CS_CNTL_ENABLED … #define A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A6XX_HLSQ_CS_NDRANGE_0 … #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK … #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) { … } #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK … #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) { … } #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK … #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) { … } #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK … #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_NDRANGE_1 … #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK … #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_NDRANGE_2 … #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK … #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_NDRANGE_3 … #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK … #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_NDRANGE_4 … #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK … #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_NDRANGE_5 … #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK … #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_NDRANGE_6 … #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK … #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT … static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_CNTL_0 … #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK … #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT … static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) { … } #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK … #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT … static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) { … } #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK … #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT … static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) { … } #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK … #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT … static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) { … } #define REG_A6XX_HLSQ_CS_CNTL_1 … #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK … #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT … static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) { … } #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE … #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK … #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT … static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) { … } #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR … #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X … #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y … #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z … #define REG_A7XX_HLSQ_CS_NDRANGE_0 … #define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK … #define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) { … } #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK … #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) { … } #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK … #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) { … } #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK … #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_NDRANGE_1 … #define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK … #define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_NDRANGE_2 … #define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK … #define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_NDRANGE_3 … #define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK … #define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_NDRANGE_4 … #define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK … #define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_NDRANGE_5 … #define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK … #define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_NDRANGE_6 … #define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK … #define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT … static inline uint32_t A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) { … } #define REG_A7XX_HLSQ_CS_KERNEL_GROUP_X … #define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y … #define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z … #define REG_A7XX_HLSQ_CS_CNTL_1 … #define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK … #define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT … static inline uint32_t A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) { … } #define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK … #define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT … static inline uint32_t A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) { … } #define A7XX_HLSQ_CS_CNTL_1_UNK11 … #define A7XX_HLSQ_CS_CNTL_1_UNK22 … #define A7XX_HLSQ_CS_CNTL_1_UNK26 … #define A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK … #define A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT … static inline uint32_t A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val) { … } #define REG_A7XX_HLSQ_CS_LOCAL_SIZE … #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK … #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT … static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(uint32_t val) { … } #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK … #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT … static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(uint32_t val) { … } #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK … #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT … static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(uint32_t val) { … } #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD … #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR … #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA … #define REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0) … static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { … } #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK … #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT … static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { … } #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK … #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT … static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { … } #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 … #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK … #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT … static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) { … } #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 … #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 … #define REG_A6XX_HLSQ_DRAW_CMD … #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK … #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) { … } #define REG_A6XX_HLSQ_DISPATCH_CMD … #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK … #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) { … } #define REG_A6XX_HLSQ_EVENT_CMD … #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK … #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) { … } #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK … #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT … static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) { … } #define REG_A6XX_HLSQ_INVALIDATE_CMD … #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE … #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE … #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE … #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE … #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE … #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE … #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO … #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO … #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST … #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST … #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK … #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT … static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) { … } #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK … #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT … static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) { … } #define REG_A7XX_HLSQ_INVALIDATE_CMD … #define A7XX_HLSQ_INVALIDATE_CMD_VS_STATE … #define A7XX_HLSQ_INVALIDATE_CMD_HS_STATE … #define A7XX_HLSQ_INVALIDATE_CMD_DS_STATE … #define A7XX_HLSQ_INVALIDATE_CMD_GS_STATE … #define A7XX_HLSQ_INVALIDATE_CMD_FS_STATE … #define A7XX_HLSQ_INVALIDATE_CMD_CS_STATE … #define A7XX_HLSQ_INVALIDATE_CMD_CS_IBO … #define A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO … #define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK … #define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT … static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) { … } #define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK … #define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT … static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) { … } #define REG_A6XX_HLSQ_FS_CNTL … #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK … #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) { … } #define A6XX_HLSQ_FS_CNTL_ENABLED … #define A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_FS_CNTL … #define A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK … #define A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT … static inline uint32_t A7XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) { … } #define A7XX_HLSQ_FS_CNTL_ENABLED … #define A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS … #define REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0) … #define REG_A6XX_HLSQ_SHARED_CONSTS … #define A6XX_HLSQ_SHARED_CONSTS_ENABLE … #define REG_A6XX_HLSQ_BINDLESS_BASE(i0) … static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { … } #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK … #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT … static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { … } #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK … #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT … static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { … } #define REG_A6XX_HLSQ_2D_EVENT_CMD … #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK … #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT … static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) { … } #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK … #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT … static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) { … } #define REG_A6XX_HLSQ_UNKNOWN_BE00 … #define REG_A6XX_HLSQ_UNKNOWN_BE01 … #define REG_A6XX_HLSQ_DBG_ECO_CNTL … #define REG_A6XX_HLSQ_ADDR_MODE_CNTL … #define REG_A6XX_HLSQ_UNKNOWN_BE08 … #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0) … #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE … #define REG_A7XX_SP_AHB_READ_APERTURE … #define REG_A7XX_SP_UNKNOWN_0CE2 … #define REG_A7XX_SP_UNKNOWN_0CE4 … #define REG_A7XX_SP_UNKNOWN_0CE6 … #define REG_A6XX_CP_EVENT_START … #define A6XX_CP_EVENT_START_STATE_ID__MASK … #define A6XX_CP_EVENT_START_STATE_ID__SHIFT … static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) { … } #define REG_A6XX_CP_EVENT_END … #define A6XX_CP_EVENT_END_STATE_ID__MASK … #define A6XX_CP_EVENT_END_STATE_ID__SHIFT … static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) { … } #define REG_A6XX_CP_2D_EVENT_START … #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK … #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT … static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) { … } #define REG_A6XX_CP_2D_EVENT_END … #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK … #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT … static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) { … } #define REG_A6XX_TEX_SAMP_0 … #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR … #define A6XX_TEX_SAMP_0_XY_MAG__MASK … #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT … static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) { … } #define A6XX_TEX_SAMP_0_XY_MIN__MASK … #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT … static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) { … } #define A6XX_TEX_SAMP_0_WRAP_S__MASK … #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT … static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) { … } #define A6XX_TEX_SAMP_0_WRAP_T__MASK … #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT … static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) { … } #define A6XX_TEX_SAMP_0_WRAP_R__MASK … #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT … static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) { … } #define A6XX_TEX_SAMP_0_ANISO__MASK … #define A6XX_TEX_SAMP_0_ANISO__SHIFT … static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) { … } #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK … #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT … static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) { … } #define REG_A6XX_TEX_SAMP_1 … #define A6XX_TEX_SAMP_1_CLAMPENABLE … #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK … #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT … static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) { … } #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF … #define A6XX_TEX_SAMP_1_UNNORM_COORDS … #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR … #define A6XX_TEX_SAMP_1_MAX_LOD__MASK … #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT … static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) { … } #define A6XX_TEX_SAMP_1_MIN_LOD__MASK … #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT … static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) { … } #define REG_A6XX_TEX_SAMP_2 … #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK … #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT … static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) { … } #define A6XX_TEX_SAMP_2_CHROMA_LINEAR … #define A6XX_TEX_SAMP_2_BCOLOR__MASK … #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT … static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) { … } #define REG_A6XX_TEX_SAMP_3 … #define REG_A6XX_TEX_CONST_0 … #define A6XX_TEX_CONST_0_TILE_MODE__MASK … #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) { … } #define A6XX_TEX_CONST_0_SRGB … #define A6XX_TEX_CONST_0_SWIZ_X__MASK … #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) { … } #define A6XX_TEX_CONST_0_SWIZ_Y__MASK … #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) { … } #define A6XX_TEX_CONST_0_SWIZ_Z__MASK … #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) { … } #define A6XX_TEX_CONST_0_SWIZ_W__MASK … #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) { … } #define A6XX_TEX_CONST_0_MIPLVLS__MASK … #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) { … } #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X … #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y … #define A6XX_TEX_CONST_0_SAMPLES__MASK … #define A6XX_TEX_CONST_0_SAMPLES__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) { … } #define A6XX_TEX_CONST_0_FMT__MASK … #define A6XX_TEX_CONST_0_FMT__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) { … } #define A6XX_TEX_CONST_0_SWAP__MASK … #define A6XX_TEX_CONST_0_SWAP__SHIFT … static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) { … } #define REG_A6XX_TEX_CONST_1 … #define A6XX_TEX_CONST_1_WIDTH__MASK … #define A6XX_TEX_CONST_1_WIDTH__SHIFT … static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) { … } #define A6XX_TEX_CONST_1_HEIGHT__MASK … #define A6XX_TEX_CONST_1_HEIGHT__SHIFT … static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) { … } #define REG_A6XX_TEX_CONST_2 … #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK … #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT … static inline uint32_t A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val) { … } #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK … #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT … static inline uint32_t A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val) { … } #define A6XX_TEX_CONST_2_PITCHALIGN__MASK … #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT … static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) { … } #define A6XX_TEX_CONST_2_PITCH__MASK … #define A6XX_TEX_CONST_2_PITCH__SHIFT … static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) { … } #define A6XX_TEX_CONST_2_TYPE__MASK … #define A6XX_TEX_CONST_2_TYPE__SHIFT … static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) { … } #define REG_A6XX_TEX_CONST_3 … #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK … #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) { … } #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK … #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT … static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) { … } #define A6XX_TEX_CONST_3_TILE_ALL … #define A6XX_TEX_CONST_3_FLAG … #define REG_A6XX_TEX_CONST_4 … #define A6XX_TEX_CONST_4_BASE_LO__MASK … #define A6XX_TEX_CONST_4_BASE_LO__SHIFT … static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) { … } #define REG_A6XX_TEX_CONST_5 … #define A6XX_TEX_CONST_5_BASE_HI__MASK … #define A6XX_TEX_CONST_5_BASE_HI__SHIFT … static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) { … } #define A6XX_TEX_CONST_5_DEPTH__MASK … #define A6XX_TEX_CONST_5_DEPTH__SHIFT … static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) { … } #define REG_A6XX_TEX_CONST_6 … #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK … #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT … static inline uint32_t A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val) { … } #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK … #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT … static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) { … } #define REG_A6XX_TEX_CONST_7 … #define A6XX_TEX_CONST_7_FLAG_LO__MASK … #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT … static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) { … } #define REG_A6XX_TEX_CONST_8 … #define A6XX_TEX_CONST_8_FLAG_HI__MASK … #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT … static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) { … } #define REG_A6XX_TEX_CONST_9 … #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK … #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT … static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) { … } #define REG_A6XX_TEX_CONST_10 … #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK … #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT … static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) { … } #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK … #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT … static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) { … } #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK … #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT … static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) { … } #define REG_A6XX_TEX_CONST_11 … #define REG_A6XX_TEX_CONST_12 … #define REG_A6XX_TEX_CONST_13 … #define REG_A6XX_TEX_CONST_14 … #define REG_A6XX_TEX_CONST_15 … #define REG_A6XX_UBO_0 … #define A6XX_UBO_0_BASE_LO__MASK … #define A6XX_UBO_0_BASE_LO__SHIFT … static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) { … } #define REG_A6XX_UBO_1 … #define A6XX_UBO_1_BASE_HI__MASK … #define A6XX_UBO_1_BASE_HI__SHIFT … static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) { … } #define A6XX_UBO_1_SIZE__MASK … #define A6XX_UBO_1_SIZE__SHIFT … static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) { … } #define REG_A6XX_PDC_GPU_ENABLE_PDC … #define REG_A6XX_PDC_GPU_SEQ_START_ADDR … #define REG_A6XX_PDC_GPU_TCS0_CONTROL … #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK … #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK … #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID … #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR … #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA … #define REG_A6XX_PDC_GPU_TCS1_CONTROL … #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK … #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK … #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID … #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR … #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA … #define REG_A6XX_PDC_GPU_TCS2_CONTROL … #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK … #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK … #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID … #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR … #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA … #define REG_A6XX_PDC_GPU_TCS3_CONTROL … #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK … #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK … #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID … #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR … #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA … #define REG_A6XX_PDC_GPU_SEQ_MEM_0 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A … #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) { … } #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT … #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) { … } #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM … #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) { … } #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) { … } #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) { … } #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK … #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT … static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) { … } #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 … #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 … #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 … #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 … #define REG_A7XX_CX_MISC_TCM_RET_CNTL … #define REG_A7XX_CX_MISC_SW_FUSE_VALUE … #define A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND … #define A7XX_CX_MISC_SW_FUSE_VALUE_LPAC … #define A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING … #ifdef __cplusplus template<chip CHIP> constexpr inline uint16_t CMD_REGS[] = {}; template<chip CHIP> constexpr inline uint16_t RP_BLIT_REGS[] = {}; template<> constexpr inline uint16_t CMD_REGS<A7XX>[] = { 0xc03, 0xc04, 0xc30, 0xc31, 0xc32, 0xc33, 0xc34, 0xc35, 0xc36, 0xc37, 0xce2, 0xce3, 0xce4, 0xce5, 0xce6, 0xce7, 0xe10, 0xe11, 0xe12, 0xe17, 0xe19, 0x8008, 0x8009, 0x800a, 0x800b, 0x800c, 0x8099, 0x80a7, 0x80af, 0x80f4, 0x80f5, 0x80f5, 0x80f6, 0x80f6, 0x80f7, 0x80f8, 0x80f9, 0x80f9, 0x80fa, 0x80fa, 0x80fb, 0x810a, 0x810b, 0x8110, 0x8120, 0x8121, 0x8600, 0x880e, 0x8811, 0x8818, 0x8819, 0x881a, 0x881b, 0x881c, 0x881d, 0x881e, 0x8864, 0x8891, 0x8899, 0x88e5, 0x88f0, 0x8927, 0x8928, 0x8e01, 0x8e04, 0x8e06, 0x8e07, 0x8e09, 0x8e79, 0x9218, 0x9219, 0x921a, 0x921b, 0x921c, 0x921d, 0x921e, 0x921f, 0x9220, 0x9221, 0x9222, 0x9223, 0x9224, 0x9225, 0x9226, 0x9227, 0x9228, 0x9229, 0x922a, 0x922b, 0x922c, 0x922d, 0x922e, 0x922f, 0x9230, 0x9231, 0x9232, 0x9233, 0x9234, 0x9235, 0x9236, 0x9300, 0x9600, 0x9601, 0x9602, 0x9810, 0x9811, 0x9885, 0x9886, 0x9e24, 0x9e72, 0xa007, 0xa009, 0xa600, 0xa82d, 0xa82f, 0xa868, 0xa899, 0xa8a0, 0xa8a1, 0xa8a2, 0xa8a3, 0xa8a4, 0xa8a5, 0xa8a6, 0xa8a7, 0xa8a8, 0xa8a9, 0xa8aa, 0xa8ab, 0xa8ac, 0xa8ad, 0xa8ae, 0xa8af, 0xa9a8, 0xa9ac, 0xa9ad, 0xa9b0, 0xa9b1, 0xa9b2, 0xa9b3, 0xa9b4, 0xa9b5, 0xa9b6, 0xa9b7, 0xa9b8, 0xa9b9, 0xa9ba, 0xa9bb, 0xa9bc, 0xa9bd, 0xa9be, 0xa9c2, 0xa9c3, 0xa9c5, 0xa9cd, 0xa9df, 0xa9e2, 0xa9e3, 0xa9e6, 0xa9e7, 0xa9e8, 0xa9e9, 0xa9ea, 0xa9eb, 0xa9ec, 0xa9ed, 0xa9ee, 0xa9ef, 0xa9f0, 0xa9f1, 0xa9f2, 0xa9f3, 0xa9f4, 0xa9f5, 0xa9f6, 0xa9f7, 0xaa01, 0xaa02, 0xaa03, 0xaaf2, 0xab01, 0xab02, 0xab1a, 0xab1b, 0xab1f, 0xab20, 0xab22, 0xae00, 0xae03, 0xae04, 0xae06, 0xae08, 0xae09, 0xae0a, 0xae0f, 0xae6a, 0xae6b, 0xae6c, 0xae73, 0xb180, 0xb181, 0xb182, 0xb183, 0xb302, 0xb303, 0xb309, 0xb310, 0xb600, 0xb602, 0xb608, 0xb609, 0xb60a, 0xb60b, 0xb60c, }; template<> constexpr inline uint16_t CMD_REGS<A6XX>[] = { 0xc03, 0xc04, 0xc30, 0xc31, 0xc32, 0xc33, 0xc34, 0xc35, 0xc36, 0xc37, 0xe12, 0xe17, 0xe19, 0x8099, 0x80af, 0x810a, 0x8110, 0x8600, 0x880e, 0x8811, 0x8818, 0x8819, 0x881a, 0x881b, 0x881c, 0x881d, 0x881e, 0x8864, 0x8891, 0x88f0, 0x8927, 0x8928, 0x8e01, 0x8e04, 0x8e07, 0x9210, 0x9211, 0x9218, 0x9219, 0x921a, 0x921b, 0x921c, 0x921d, 0x921e, 0x921f, 0x9220, 0x9221, 0x9222, 0x9223, 0x9224, 0x9225, 0x9226, 0x9227, 0x9228, 0x9229, 0x922a, 0x922b, 0x922c, 0x922d, 0x922e, 0x922f, 0x9230, 0x9231, 0x9232, 0x9233, 0x9234, 0x9235, 0x9236, 0x9300, 0x9600, 0x9601, 0x9602, 0x9e08, 0x9e09, 0x9e72, 0xa007, 0xa009, 0xa8a0, 0xa8a1, 0xa8a2, 0xa8a3, 0xa8a4, 0xa8a5, 0xa8a6, 0xa8a7, 0xa8a8, 0xa8a9, 0xa8aa, 0xa8ab, 0xa8ac, 0xa8ad, 0xa8ae, 0xa8af, 0xa9a8, 0xa9b0, 0xa9b1, 0xa9b2, 0xa9b3, 0xa9b4, 0xa9b5, 0xa9b6, 0xa9b7, 0xa9b8, 0xa9b9, 0xa9ba, 0xa9bb, 0xa9bc, 0xa9bd, 0xa9c2, 0xa9c3, 0xa9e2, 0xa9e3, 0xa9e6, 0xa9e7, 0xa9e8, 0xa9e9, 0xa9ea, 0xa9eb, 0xa9ec, 0xa9ed, 0xa9ee, 0xa9ef, 0xa9f0, 0xa9f1, 0xaaf2, 0xab1a, 0xab1b, 0xab20, 0xae00, 0xae03, 0xae04, 0xae0f, 0xb180, 0xb181, 0xb182, 0xb183, 0xb302, 0xb303, 0xb309, 0xb600, 0xb602, 0xb605, 0xb987, 0xb9d0, 0xbb08, 0xbb11, 0xbb20, 0xbb21, 0xbb22, 0xbb23, 0xbb24, 0xbb25, 0xbb26, 0xbb27, 0xbb28, 0xbb29, 0xbe00, 0xbe01, 0xbe04, }; template<> constexpr inline uint16_t RP_BLIT_REGS<A7XX>[] = { 0xc02, 0xc06, 0xc10, 0xc11, 0xc12, 0xc13, 0xc14, 0xc15, 0xc16, 0xc17, 0xc18, 0xc19, 0xc1a, 0xc1b, 0xc1c, 0xc1d, 0xc1e, 0xc1f, 0xc20, 0xc21, 0xc22, 0xc23, 0xc24, 0xc25, 0xc26, 0xc27, 0xc28, 0xc29, 0xc2a, 0xc2b, 0xc2c, 0xc2d, 0xc2e, 0xc2f, 0xc38, 0xc39, 0xc3a, 0xc3b, 0xc3c, 0xc3d, 0xc3e, 0xc3f, 0xc40, 0xc41, 0xc42, 0xc43, 0xc44, 0xc45, 0xc46, 0xc47, 0xc48, 0xc49, 0xc4a, 0xc4b, 0xc4c, 0xc4d, 0xc4e, 0xc4f, 0xc50, 0xc51, 0xc52, 0xc53, 0xc54, 0xc55, 0xc56, 0xc57, 0xd08, 0x8000, 0x8001, 0x8002, 0x8003, 0x8004, 0x8005, 0x8006, 0x8007, 0x8010, 0x8011, 0x8012, 0x8013, 0x8014, 0x8015, 0x8016, 0x8017, 0x8018, 0x8019, 0x801a, 0x801b, 0x801c, 0x801d, 0x801e, 0x801f, 0x8020, 0x8021, 0x8022, 0x8023, 0x8024, 0x8025, 0x8026, 0x8027, 0x8028, 0x8029, 0x802a, 0x802b, 0x802c, 0x802d, 0x802e, 0x802f, 0x8030, 0x8031, 0x8032, 0x8033, 0x8034, 0x8035, 0x8036, 0x8037, 0x8038, 0x8039, 0x803a, 0x803b, 0x803c, 0x803d, 0x803e, 0x803f, 0x8040, 0x8041, 0x8042, 0x8043, 0x8044, 0x8045, 0x8046, 0x8047, 0x8048, 0x8049, 0x804a, 0x804b, 0x804c, 0x804d, 0x804e, 0x804f, 0x8050, 0x8051, 0x8052, 0x8053, 0x8054, 0x8055, 0x8056, 0x8057, 0x8058, 0x8059, 0x805a, 0x805b, 0x805c, 0x805d, 0x805e, 0x805f, 0x8060, 0x8061, 0x8062, 0x8063, 0x8064, 0x8065, 0x8066, 0x8067, 0x8068, 0x8069, 0x806a, 0x806b, 0x806c, 0x806d, 0x806e, 0x806f, 0x8070, 0x8071, 0x8072, 0x8073, 0x8074, 0x8075, 0x8076, 0x8077, 0x8078, 0x8079, 0x807a, 0x807b, 0x807c, 0x807d, 0x807e, 0x807f, 0x8080, 0x8081, 0x8082, 0x8083, 0x8084, 0x8085, 0x8086, 0x8087, 0x8088, 0x8089, 0x808a, 0x808b, 0x808c, 0x808d, 0x808e, 0x808f, 0x8090, 0x8091, 0x8092, 0x8094, 0x8095, 0x8096, 0x8097, 0x8098, 0x809b, 0x809c, 0x809d, 0x80a0, 0x80a1, 0x80a2, 0x80a3, 0x80a4, 0x80a5, 0x80a6, 0x80b0, 0x80b1, 0x80b2, 0x80b3, 0x80b4, 0x80b5, 0x80b6, 0x80b7, 0x80b8, 0x80b9, 0x80ba, 0x80bb, 0x80bc, 0x80bd, 0x80be, 0x80bf, 0x80c0, 0x80c1, 0x80c2, 0x80c3, 0x80c4, 0x80c5, 0x80c6, 0x80c7, 0x80c8, 0x80c9, 0x80ca, 0x80cb, 0x80cc, 0x80cd, 0x80ce, 0x80cf, 0x80d0, 0x80d1, 0x80d2, 0x80d3, 0x80d4, 0x80d5, 0x80d6, 0x80d7, 0x80d8, 0x80d9, 0x80da, 0x80db, 0x80dc, 0x80dd, 0x80de, 0x80df, 0x80e0, 0x80e1, 0x80e2, 0x80e3, 0x80e4, 0x80e5, 0x80e6, 0x80e7, 0x80e8, 0x80e9, 0x80ea, 0x80eb, 0x80ec, 0x80ed, 0x80ee, 0x80ef, 0x80f0, 0x80f1, 0x8100, 0x8101, 0x8102, 0x8103, 0x8104, 0x8105, 0x8106, 0x8107, 0x8109, 0x8113, 0x8114, 0x8115, 0x8116, 0x8400, 0x8401, 0x8402, 0x8403, 0x8404, 0x8405, 0x8406, 0x840a, 0x840b, 0x8800, 0x8801, 0x8802, 0x8803, 0x8804, 0x8805, 0x8806, 0x8809, 0x880a, 0x880b, 0x880c, 0x880d, 0x880f, 0x8810, 0x8812, 0x8820, 0x8821, 0x8822, 0x8823, 0x8824, 0x8825, 0x8826, 0x8827, 0x8828, 0x8829, 0x882a, 0x882b, 0x882c, 0x882d, 0x882e, 0x882f, 0x8830, 0x8831, 0x8832, 0x8833, 0x8834, 0x8835, 0x8836, 0x8837, 0x8838, 0x8839, 0x883a, 0x883b, 0x883c, 0x883d, 0x883e, 0x883f, 0x8840, 0x8841, 0x8842, 0x8843, 0x8844, 0x8845, 0x8846, 0x8847, 0x8848, 0x8849, 0x884a, 0x884b, 0x884c, 0x884d, 0x884e, 0x884f, 0x8850, 0x8851, 0x8852, 0x8853, 0x8854, 0x8855, 0x8856, 0x8857, 0x8858, 0x8859, 0x885a, 0x885b, 0x885c, 0x885d, 0x885e, 0x885f, 0x8860, 0x8861, 0x8862, 0x8863, 0x8865, 0x8870, 0x8871, 0x8872, 0x8873, 0x8874, 0x8875, 0x8876, 0x8877, 0x8878, 0x8879, 0x8880, 0x8881, 0x8882, 0x8883, 0x8884, 0x8885, 0x8886, 0x8887, 0x8888, 0x8889, 0x8890, 0x8898, 0x88c0, 0x88c1, 0x88d0, 0x88d1, 0x88d2, 0x88d3, 0x88d4, 0x88d5, 0x88d6, 0x88d7, 0x88d8, 0x88d9, 0x88da, 0x88db, 0x88dc, 0x88dd, 0x88de, 0x88df, 0x88e0, 0x88e1, 0x88e2, 0x88e3, 0x88e4, 0x8900, 0x8901, 0x8902, 0x8903, 0x8904, 0x8905, 0x8906, 0x8907, 0x8908, 0x8909, 0x890a, 0x890b, 0x890c, 0x890d, 0x890e, 0x890f, 0x8910, 0x8911, 0x8912, 0x8913, 0x8914, 0x8915, 0x8916, 0x8917, 0x8918, 0x8919, 0x891a, 0x8c00, 0x8c01, 0x8c17, 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 0x8c20, 0x8c21, 0x8c22, 0x8c23, 0x8c24, 0x8c25, 0x8c2c, 0x8c2d, 0x8c2e, 0x8c2f, 0x9101, 0x9102, 0x9103, 0x9104, 0x9105, 0x9106, 0x9107, 0x9108, 0x9109, 0x910a, 0x910b, 0x910c, 0x9200, 0x9201, 0x9202, 0x9203, 0x9204, 0x9205, 0x9206, 0x9207, 0x9208, 0x9209, 0x920a, 0x920b, 0x920c, 0x920d, 0x920e, 0x920f, 0x9212, 0x9213, 0x9214, 0x9215, 0x9216, 0x9217, 0x9301, 0x9302, 0x9303, 0x9304, 0x9305, 0x9306, 0x9307, 0x9308, 0x9309, 0x9311, 0x9312, 0x9313, 0x9314, 0x9315, 0x9316, 0x9317, 0x9800, 0x9801, 0x9802, 0x9803, 0x9804, 0x9805, 0x9806, 0x9808, 0x9809, 0x9b00, 0x9b01, 0x9b02, 0x9b03, 0x9b04, 0x9b05, 0x9b07, 0x9b08, 0x9b09, 0xa000, 0xa001, 0xa002, 0xa003, 0xa004, 0xa005, 0xa006, 0xa008, 0xa00e, 0xa00f, 0xa010, 0xa011, 0xa012, 0xa013, 0xa014, 0xa015, 0xa016, 0xa017, 0xa018, 0xa019, 0xa01a, 0xa01b, 0xa01c, 0xa01d, 0xa01e, 0xa01f, 0xa020, 0xa021, 0xa022, 0xa023, 0xa024, 0xa025, 0xa026, 0xa027, 0xa028, 0xa029, 0xa02a, 0xa02b, 0xa02c, 0xa02d, 0xa02e, 0xa02f, 0xa030, 0xa031, 0xa032, 0xa033, 0xa034, 0xa035, 0xa036, 0xa037, 0xa038, 0xa039, 0xa03a, 0xa03b, 0xa03c, 0xa03d, 0xa03e, 0xa03f, 0xa040, 0xa041, 0xa042, 0xa043, 0xa044, 0xa045, 0xa046, 0xa047, 0xa048, 0xa049, 0xa04a, 0xa04b, 0xa04c, 0xa04d, 0xa04e, 0xa04f, 0xa050, 0xa051, 0xa052, 0xa053, 0xa054, 0xa055, 0xa056, 0xa057, 0xa058, 0xa059, 0xa05a, 0xa05b, 0xa05c, 0xa05d, 0xa05e, 0xa05f, 0xa060, 0xa061, 0xa062, 0xa063, 0xa064, 0xa065, 0xa066, 0xa067, 0xa068, 0xa069, 0xa06a, 0xa06b, 0xa06c, 0xa06d, 0xa06e, 0xa06f, 0xa070, 0xa071, 0xa072, 0xa073, 0xa074, 0xa075, 0xa076, 0xa077, 0xa078, 0xa079, 0xa07a, 0xa07b, 0xa07c, 0xa07d, 0xa07e, 0xa07f, 0xa080, 0xa081, 0xa082, 0xa083, 0xa084, 0xa085, 0xa086, 0xa087, 0xa088, 0xa089, 0xa08a, 0xa08b, 0xa08c, 0xa08d, 0xa08e, 0xa08f, 0xa090, 0xa091, 0xa092, 0xa093, 0xa094, 0xa095, 0xa096, 0xa097, 0xa098, 0xa099, 0xa09a, 0xa09b, 0xa09c, 0xa09d, 0xa09e, 0xa09f, 0xa0a0, 0xa0a1, 0xa0a2, 0xa0a3, 0xa0a4, 0xa0a5, 0xa0a6, 0xa0a7, 0xa0a8, 0xa0a9, 0xa0aa, 0xa0ab, 0xa0ac, 0xa0ad, 0xa0ae, 0xa0af, 0xa0b0, 0xa0b1, 0xa0b2, 0xa0b3, 0xa0b4, 0xa0b5, 0xa0b6, 0xa0b7, 0xa0b8, 0xa0b9, 0xa0ba, 0xa0bb, 0xa0bc, 0xa0bd, 0xa0be, 0xa0bf, 0xa0c0, 0xa0c1, 0xa0c2, 0xa0c3, 0xa0c4, 0xa0c5, 0xa0c6, 0xa0c7, 0xa0c8, 0xa0c9, 0xa0ca, 0xa0cb, 0xa0cc, 0xa0cd, 0xa0ce, 0xa0cf, 0xa0d0, 0xa0d1, 0xa0d2, 0xa0d3, 0xa0d4, 0xa0d5, 0xa0d6, 0xa0d7, 0xa0d8, 0xa0d9, 0xa0da, 0xa0db, 0xa0dc, 0xa0dd, 0xa0de, 0xa0df, 0xa0e0, 0xa0e1, 0xa0e2, 0xa0e3, 0xa0e4, 0xa0e5, 0xa0e6, 0xa0e7, 0xa0e8, 0xa0e9, 0xa0ea, 0xa0eb, 0xa0ec, 0xa0ed, 0xa0ee, 0xa0ef, 0xa0f8, 0xa800, 0xa802, 0xa803, 0xa804, 0xa805, 0xa806, 0xa807, 0xa808, 0xa809, 0xa80a, 0xa80b, 0xa80c, 0xa80d, 0xa80e, 0xa80f, 0xa810, 0xa811, 0xa812, 0xa813, 0xa814, 0xa815, 0xa816, 0xa817, 0xa818, 0xa819, 0xa81a, 0xa81b, 0xa81c, 0xa81d, 0xa81e, 0xa81f, 0xa820, 0xa821, 0xa822, 0xa823, 0xa824, 0xa825, 0xa827, 0xa830, 0xa831, 0xa832, 0xa833, 0xa834, 0xa835, 0xa836, 0xa837, 0xa838, 0xa839, 0xa83a, 0xa83b, 0xa83c, 0xa83d, 0xa83f, 0xa840, 0xa842, 0xa843, 0xa844, 0xa845, 0xa846, 0xa847, 0xa848, 0xa849, 0xa84a, 0xa84b, 0xa84c, 0xa84d, 0xa84e, 0xa84f, 0xa850, 0xa851, 0xa852, 0xa853, 0xa854, 0xa855, 0xa856, 0xa857, 0xa858, 0xa859, 0xa85a, 0xa85b, 0xa85c, 0xa85d, 0xa85e, 0xa85f, 0xa860, 0xa861, 0xa862, 0xa863, 0xa864, 0xa865, 0xa867, 0xa870, 0xa871, 0xa872, 0xa873, 0xa874, 0xa875, 0xa876, 0xa877, 0xa878, 0xa879, 0xa87a, 0xa87b, 0xa87c, 0xa87d, 0xa87e, 0xa87f, 0xa880, 0xa881, 0xa882, 0xa883, 0xa884, 0xa885, 0xa886, 0xa887, 0xa888, 0xa889, 0xa88a, 0xa88b, 0xa88c, 0xa88d, 0xa88e, 0xa88f, 0xa890, 0xa891, 0xa892, 0xa893, 0xa894, 0xa895, 0xa896, 0xa898, 0xa980, 0xa982, 0xa983, 0xa984, 0xa985, 0xa986, 0xa987, 0xa988, 0xa989, 0xa98a, 0xa98b, 0xa98c, 0xa98d, 0xa98e, 0xa98f, 0xa990, 0xa991, 0xa992, 0xa993, 0xa994, 0xa995, 0xa996, 0xa997, 0xa998, 0xa999, 0xa99a, 0xa99b, 0xa99c, 0xa99d, 0xa99e, 0xa99f, 0xa9a0, 0xa9a1, 0xa9a2, 0xa9a3, 0xa9a4, 0xa9a5, 0xa9a6, 0xa9a7, 0xa9a9, 0xa9aa, 0xa9ae, 0xa9bf, 0xa9c6, 0xa9c7, 0xa9c8, 0xa9c9, 0xa9ca, 0xa9cb, 0xa9d4, 0xa9d5, 0xa9d6, 0xa9d7, 0xa9d8, 0xa9d9, 0xa9da, 0xa9db, 0xa9dc, 0xa9dd, 0xa9de, 0xa9e0, 0xa9e1, 0xa9e4, 0xa9e5, 0xab00, 0xab03, 0xab04, 0xab05, 0xab0a, 0xab0b, 0xab0c, 0xab0d, 0xab0e, 0xab0f, 0xab10, 0xab11, 0xab12, 0xab13, 0xab14, 0xab15, 0xab16, 0xab17, 0xab18, 0xab19, 0xab21, 0xb2c0, 0xb2c2, 0xb2c3, 0xb2ca, 0xb2cb, 0xb2cc, 0xb2d2, 0xb300, 0xb301, 0xb304, 0xb305, 0xb306, 0xb307, }; template<> constexpr inline uint16_t RP_BLIT_REGS<A6XX>[] = { 0xc02, 0xc06, 0xc10, 0xc11, 0xc12, 0xc13, 0xc14, 0xc15, 0xc16, 0xc17, 0xc18, 0xc19, 0xc1a, 0xc1b, 0xc1c, 0xc1d, 0xc1e, 0xc1f, 0xc20, 0xc21, 0xc22, 0xc23, 0xc24, 0xc25, 0xc26, 0xc27, 0xc28, 0xc29, 0xc2a, 0xc2b, 0xc2c, 0xc2d, 0xc2e, 0xc2f, 0xc38, 0xc39, 0xc3a, 0xc3b, 0xc3c, 0xc3d, 0xc3e, 0xc3f, 0xc40, 0xc41, 0xc42, 0xc43, 0xc44, 0xc45, 0xc46, 0xc47, 0xc48, 0xc49, 0xc4a, 0xc4b, 0xc4c, 0xc4d, 0xc4e, 0xc4f, 0xc50, 0xc51, 0xc52, 0xc53, 0xc54, 0xc55, 0xc56, 0xc57, 0xc58, 0xc59, 0xc5a, 0xc5b, 0xc5c, 0xc5d, 0xc5e, 0xc5f, 0xc60, 0xc61, 0xc62, 0xc63, 0xc64, 0xc65, 0xc66, 0xc67, 0xc68, 0xc69, 0xc6a, 0xc6b, 0xc6c, 0xc6d, 0xc6e, 0xc6f, 0xc70, 0xc71, 0xc72, 0xc73, 0xc74, 0xc75, 0xc76, 0xc77, 0xc78, 0xc79, 0xc7a, 0xc7b, 0xc7c, 0xc7d, 0xc7e, 0xc7f, 0xc80, 0xc81, 0xc82, 0xc83, 0xc84, 0xc85, 0xc86, 0xc87, 0xc88, 0xc89, 0xc8a, 0xc8b, 0xc8c, 0xc8d, 0xc8e, 0xc8f, 0xc90, 0xc91, 0xc92, 0xc93, 0xc94, 0xc95, 0xc96, 0xc97, 0x8000, 0x8001, 0x8002, 0x8003, 0x8004, 0x8005, 0x8006, 0x8010, 0x8011, 0x8012, 0x8013, 0x8014, 0x8015, 0x8016, 0x8017, 0x8018, 0x8019, 0x801a, 0x801b, 0x801c, 0x801d, 0x801e, 0x801f, 0x8020, 0x8021, 0x8022, 0x8023, 0x8024, 0x8025, 0x8026, 0x8027, 0x8028, 0x8029, 0x802a, 0x802b, 0x802c, 0x802d, 0x802e, 0x802f, 0x8030, 0x8031, 0x8032, 0x8033, 0x8034, 0x8035, 0x8036, 0x8037, 0x8038, 0x8039, 0x803a, 0x803b, 0x803c, 0x803d, 0x803e, 0x803f, 0x8040, 0x8041, 0x8042, 0x8043, 0x8044, 0x8045, 0x8046, 0x8047, 0x8048, 0x8049, 0x804a, 0x804b, 0x804c, 0x804d, 0x804e, 0x804f, 0x8050, 0x8051, 0x8052, 0x8053, 0x8054, 0x8055, 0x8056, 0x8057, 0x8058, 0x8059, 0x805a, 0x805b, 0x805c, 0x805d, 0x805e, 0x805f, 0x8060, 0x8061, 0x8062, 0x8063, 0x8064, 0x8065, 0x8066, 0x8067, 0x8068, 0x8069, 0x806a, 0x806b, 0x806c, 0x806d, 0x806e, 0x806f, 0x8070, 0x8071, 0x8072, 0x8073, 0x8074, 0x8075, 0x8076, 0x8077, 0x8078, 0x8079, 0x807a, 0x807b, 0x807c, 0x807d, 0x807e, 0x807f, 0x8080, 0x8081, 0x8082, 0x8083, 0x8084, 0x8085, 0x8086, 0x8087, 0x8088, 0x8089, 0x808a, 0x808b, 0x808c, 0x808d, 0x808e, 0x808f, 0x8090, 0x8091, 0x8092, 0x8094, 0x8095, 0x8096, 0x8097, 0x8098, 0x809b, 0x809c, 0x809d, 0x80a0, 0x80a1, 0x80a2, 0x80a3, 0x80a4, 0x80a5, 0x80a6, 0x80b0, 0x80b1, 0x80b2, 0x80b3, 0x80b4, 0x80b5, 0x80b6, 0x80b7, 0x80b8, 0x80b9, 0x80ba, 0x80bb, 0x80bc, 0x80bd, 0x80be, 0x80bf, 0x80c0, 0x80c1, 0x80c2, 0x80c3, 0x80c4, 0x80c5, 0x80c6, 0x80c7, 0x80c8, 0x80c9, 0x80ca, 0x80cb, 0x80cc, 0x80cd, 0x80ce, 0x80cf, 0x80d0, 0x80d1, 0x80d2, 0x80d3, 0x80d4, 0x80d5, 0x80d6, 0x80d7, 0x80d8, 0x80d9, 0x80da, 0x80db, 0x80dc, 0x80dd, 0x80de, 0x80df, 0x80e0, 0x80e1, 0x80e2, 0x80e3, 0x80e4, 0x80e5, 0x80e6, 0x80e7, 0x80e8, 0x80e9, 0x80ea, 0x80eb, 0x80ec, 0x80ed, 0x80ee, 0x80ef, 0x80f0, 0x80f1, 0x8100, 0x8101, 0x8102, 0x8103, 0x8104, 0x8105, 0x8106, 0x8107, 0x8109, 0x8114, 0x8115, 0x8400, 0x8401, 0x8402, 0x8403, 0x8404, 0x8405, 0x8406, 0x840a, 0x840b, 0x8800, 0x8801, 0x8802, 0x8803, 0x8804, 0x8805, 0x8806, 0x8809, 0x880a, 0x880b, 0x880c, 0x880d, 0x880f, 0x8810, 0x8820, 0x8821, 0x8822, 0x8823, 0x8824, 0x8825, 0x8826, 0x8827, 0x8828, 0x8829, 0x882a, 0x882b, 0x882c, 0x882d, 0x882e, 0x882f, 0x8830, 0x8831, 0x8832, 0x8833, 0x8834, 0x8835, 0x8836, 0x8837, 0x8838, 0x8839, 0x883a, 0x883b, 0x883c, 0x883d, 0x883e, 0x883f, 0x8840, 0x8841, 0x8842, 0x8843, 0x8844, 0x8845, 0x8846, 0x8847, 0x8848, 0x8849, 0x884a, 0x884b, 0x884c, 0x884d, 0x884e, 0x884f, 0x8850, 0x8851, 0x8852, 0x8853, 0x8854, 0x8855, 0x8856, 0x8857, 0x8858, 0x8859, 0x885a, 0x885b, 0x885c, 0x885d, 0x885e, 0x885f, 0x8860, 0x8861, 0x8862, 0x8863, 0x8865, 0x8870, 0x8871, 0x8872, 0x8873, 0x8874, 0x8875, 0x8876, 0x8877, 0x8878, 0x8879, 0x8880, 0x8881, 0x8882, 0x8883, 0x8884, 0x8885, 0x8886, 0x8887, 0x8888, 0x8889, 0x8890, 0x8898, 0x88c0, 0x88c1, 0x88d0, 0x88d1, 0x88d2, 0x88d3, 0x88d4, 0x88d5, 0x88d6, 0x88d7, 0x88d8, 0x88d9, 0x88da, 0x88db, 0x88dc, 0x88dd, 0x88de, 0x88df, 0x88e0, 0x88e1, 0x88e2, 0x88e3, 0x8900, 0x8901, 0x8902, 0x8903, 0x8904, 0x8905, 0x8906, 0x8907, 0x8908, 0x8909, 0x890a, 0x890b, 0x890c, 0x890d, 0x890e, 0x890f, 0x8910, 0x8911, 0x8912, 0x8913, 0x8914, 0x8915, 0x8916, 0x8917, 0x8918, 0x8919, 0x891a, 0x8a00, 0x8a10, 0x8a20, 0x8a30, 0x8c00, 0x8c01, 0x8c17, 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 0x8c20, 0x8c21, 0x8c22, 0x8c23, 0x8c24, 0x8c25, 0x8c2c, 0x8c2d, 0x8c2e, 0x8c2f, 0x9100, 0x9101, 0x9102, 0x9103, 0x9104, 0x9105, 0x9106, 0x9107, 0x9108, 0x9200, 0x9201, 0x9202, 0x9203, 0x9204, 0x9205, 0x9206, 0x9207, 0x9208, 0x9209, 0x920a, 0x920b, 0x920c, 0x920d, 0x920e, 0x920f, 0x9212, 0x9213, 0x9214, 0x9215, 0x9216, 0x9217, 0x9301, 0x9302, 0x9303, 0x9304, 0x9305, 0x9306, 0x9311, 0x9312, 0x9313, 0x9314, 0x9315, 0x9316, 0x9800, 0x9801, 0x9802, 0x9803, 0x9804, 0x9805, 0x9806, 0x9808, 0x9980, 0x9981, 0x9b00, 0x9b01, 0x9b02, 0x9b03, 0x9b04, 0x9b05, 0x9b06, 0x9b07, 0x9b08, 0xa000, 0xa001, 0xa002, 0xa003, 0xa004, 0xa005, 0xa006, 0xa008, 0xa00e, 0xa00f, 0xa010, 0xa011, 0xa012, 0xa013, 0xa014, 0xa015, 0xa016, 0xa017, 0xa018, 0xa019, 0xa01a, 0xa01b, 0xa01c, 0xa01d, 0xa01e, 0xa01f, 0xa020, 0xa021, 0xa022, 0xa023, 0xa024, 0xa025, 0xa026, 0xa027, 0xa028, 0xa029, 0xa02a, 0xa02b, 0xa02c, 0xa02d, 0xa02e, 0xa02f, 0xa030, 0xa031, 0xa032, 0xa033, 0xa034, 0xa035, 0xa036, 0xa037, 0xa038, 0xa039, 0xa03a, 0xa03b, 0xa03c, 0xa03d, 0xa03e, 0xa03f, 0xa040, 0xa041, 0xa042, 0xa043, 0xa044, 0xa045, 0xa046, 0xa047, 0xa048, 0xa049, 0xa04a, 0xa04b, 0xa04c, 0xa04d, 0xa04e, 0xa04f, 0xa050, 0xa051, 0xa052, 0xa053, 0xa054, 0xa055, 0xa056, 0xa057, 0xa058, 0xa059, 0xa05a, 0xa05b, 0xa05c, 0xa05d, 0xa05e, 0xa05f, 0xa060, 0xa061, 0xa062, 0xa063, 0xa064, 0xa065, 0xa066, 0xa067, 0xa068, 0xa069, 0xa06a, 0xa06b, 0xa06c, 0xa06d, 0xa06e, 0xa06f, 0xa070, 0xa071, 0xa072, 0xa073, 0xa074, 0xa075, 0xa076, 0xa077, 0xa078, 0xa079, 0xa07a, 0xa07b, 0xa07c, 0xa07d, 0xa07e, 0xa07f, 0xa080, 0xa081, 0xa082, 0xa083, 0xa084, 0xa085, 0xa086, 0xa087, 0xa088, 0xa089, 0xa08a, 0xa08b, 0xa08c, 0xa08d, 0xa08e, 0xa08f, 0xa090, 0xa091, 0xa092, 0xa093, 0xa094, 0xa095, 0xa096, 0xa097, 0xa098, 0xa099, 0xa09a, 0xa09b, 0xa09c, 0xa09d, 0xa09e, 0xa09f, 0xa0a0, 0xa0a1, 0xa0a2, 0xa0a3, 0xa0a4, 0xa0a5, 0xa0a6, 0xa0a7, 0xa0a8, 0xa0a9, 0xa0aa, 0xa0ab, 0xa0ac, 0xa0ad, 0xa0ae, 0xa0af, 0xa0b0, 0xa0b1, 0xa0b2, 0xa0b3, 0xa0b4, 0xa0b5, 0xa0b6, 0xa0b7, 0xa0b8, 0xa0b9, 0xa0ba, 0xa0bb, 0xa0bc, 0xa0bd, 0xa0be, 0xa0bf, 0xa0c0, 0xa0c1, 0xa0c2, 0xa0c3, 0xa0c4, 0xa0c5, 0xa0c6, 0xa0c7, 0xa0c8, 0xa0c9, 0xa0ca, 0xa0cb, 0xa0cc, 0xa0cd, 0xa0ce, 0xa0cf, 0xa0d0, 0xa0d1, 0xa0d2, 0xa0d3, 0xa0d4, 0xa0d5, 0xa0d6, 0xa0d7, 0xa0d8, 0xa0d9, 0xa0da, 0xa0db, 0xa0dc, 0xa0dd, 0xa0de, 0xa0df, 0xa0e0, 0xa0e1, 0xa0e2, 0xa0e3, 0xa0e4, 0xa0e5, 0xa0e6, 0xa0e7, 0xa0e8, 0xa0e9, 0xa0ea, 0xa0eb, 0xa0ec, 0xa0ed, 0xa0ee, 0xa0ef, 0xa0f8, 0xa800, 0xa802, 0xa803, 0xa804, 0xa805, 0xa806, 0xa807, 0xa808, 0xa809, 0xa80a, 0xa80b, 0xa80c, 0xa80d, 0xa80e, 0xa80f, 0xa810, 0xa811, 0xa812, 0xa813, 0xa814, 0xa815, 0xa816, 0xa817, 0xa818, 0xa819, 0xa81a, 0xa81b, 0xa81c, 0xa81d, 0xa81e, 0xa81f, 0xa820, 0xa821, 0xa822, 0xa823, 0xa824, 0xa825, 0xa830, 0xa831, 0xa832, 0xa833, 0xa834, 0xa835, 0xa836, 0xa837, 0xa838, 0xa839, 0xa83a, 0xa83b, 0xa83c, 0xa83d, 0xa840, 0xa842, 0xa843, 0xa844, 0xa845, 0xa846, 0xa847, 0xa848, 0xa849, 0xa84a, 0xa84b, 0xa84c, 0xa84d, 0xa84e, 0xa84f, 0xa850, 0xa851, 0xa852, 0xa853, 0xa854, 0xa855, 0xa856, 0xa857, 0xa858, 0xa859, 0xa85a, 0xa85b, 0xa85c, 0xa85d, 0xa85e, 0xa85f, 0xa860, 0xa861, 0xa862, 0xa863, 0xa864, 0xa865, 0xa870, 0xa871, 0xa872, 0xa873, 0xa874, 0xa875, 0xa876, 0xa877, 0xa878, 0xa879, 0xa87a, 0xa87b, 0xa87c, 0xa87d, 0xa87e, 0xa87f, 0xa880, 0xa881, 0xa882, 0xa883, 0xa884, 0xa885, 0xa886, 0xa887, 0xa888, 0xa889, 0xa88a, 0xa88b, 0xa88c, 0xa88d, 0xa88e, 0xa88f, 0xa890, 0xa891, 0xa892, 0xa893, 0xa894, 0xa895, 0xa896, 0xa980, 0xa982, 0xa983, 0xa984, 0xa985, 0xa986, 0xa987, 0xa988, 0xa989, 0xa98a, 0xa98b, 0xa98c, 0xa98d, 0xa98e, 0xa98f, 0xa990, 0xa991, 0xa992, 0xa993, 0xa994, 0xa995, 0xa996, 0xa997, 0xa998, 0xa999, 0xa99a, 0xa99b, 0xa99c, 0xa99d, 0xa99e, 0xa99f, 0xa9a0, 0xa9a1, 0xa9a2, 0xa9a3, 0xa9a4, 0xa9a5, 0xa9a6, 0xa9a7, 0xa9a9, 0xa9e0, 0xa9e1, 0xa9e4, 0xa9e5, 0xab00, 0xab04, 0xab05, 0xab10, 0xab11, 0xab12, 0xab13, 0xab14, 0xab15, 0xab16, 0xab17, 0xab18, 0xab19, 0xacc0, 0xb300, 0xb301, 0xb304, 0xb305, 0xb306, 0xb307, 0xb4c0, 0xb4c1, 0xb4c2, 0xb4c3, 0xb4c4, 0xb4ca, 0xb4cb, 0xb4cc, 0xb4d1, 0xb800, 0xb801, 0xb802, 0xb803, 0xb980, 0xb982, 0xb983, 0xb984, 0xb985, 0xb986, 0xb990, 0xb991, 0xb992, 0xb993, 0xb994, 0xb995, 0xb996, 0xb997, 0xb998, 0xb999, 0xb99a, 0xb99b, 0xb9c0, 0xb9c1, 0xb9c2, 0xb9c3, 0xb9c4, 0xb9c5, 0xb9c6, 0xb9c7, 0xb9c8, 0xb9c9, 0xbb10, }; #endif #endif /* A6XX_XML */
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