#ifndef A2XX_XML #define A2XX_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/a2xx.xml ( 91939 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml ( 85907 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum a2xx_rb_dither_type { … }; enum a2xx_colorformatx { … }; enum a2xx_sq_surfaceformat { … }; enum a2xx_sq_ps_vtx_mode { … }; enum a2xx_sq_sample_cntl { … }; enum a2xx_dx_clip_space { … }; enum a2xx_pa_su_sc_polymode { … }; enum a2xx_rb_edram_mode { … }; enum a2xx_pa_sc_pattern_bit_order { … }; enum a2xx_pa_sc_auto_reset_cntl { … }; enum a2xx_pa_pixcenter { … }; enum a2xx_pa_roundmode { … }; enum a2xx_pa_quantmode { … }; enum a2xx_rb_copy_sample_select { … }; enum a2xx_rb_blend_opcode { … }; enum a2xx_su_perfcnt_select { … }; enum a2xx_sc_perfcnt_select { … }; enum a2xx_vgt_perfcount_select { … }; enum a2xx_tcr_perfcount_select { … }; enum a2xx_tp_perfcount_select { … }; enum a2xx_tcm_perfcount_select { … }; enum a2xx_tcf_perfcount_select { … }; enum a2xx_sq_perfcnt_select { … }; enum a2xx_sx_perfcnt_select { … }; enum a2xx_rbbm_perfcount1_sel { … }; enum a2xx_cp_perfcount_sel { … }; enum a2xx_rb_perfcnt_select { … }; enum a2xx_mh_perfcnt_select { … }; enum perf_mode_cnt { … }; enum adreno_mmu_clnt_beh { … }; enum sq_tex_clamp { … }; enum sq_tex_swiz { … }; enum sq_tex_filter { … }; enum sq_tex_aniso_filter { … }; enum sq_tex_dimension { … }; enum sq_tex_border_color { … }; enum sq_tex_sign { … }; enum sq_tex_endian { … }; enum sq_tex_clamp_policy { … }; enum sq_tex_num_format { … }; enum sq_tex_type { … }; #define REG_A2XX_RBBM_PATCH_RELEASE … #define REG_A2XX_RBBM_CNTL … #define REG_A2XX_RBBM_SOFT_RESET … #define REG_A2XX_CP_PFP_UCODE_ADDR … #define REG_A2XX_CP_PFP_UCODE_DATA … #define REG_A2XX_MH_MMU_CONFIG … #define A2XX_MH_MMU_CONFIG_MMU_ENABLE … #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE … #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK … #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT … static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) { … } #define REG_A2XX_MH_MMU_VA_RANGE … #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK … #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT … static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) { … } #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK … #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT … static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) { … } #define REG_A2XX_MH_MMU_PT_BASE … #define REG_A2XX_MH_MMU_PAGE_FAULT … #define REG_A2XX_MH_MMU_TRAN_ERROR … #define REG_A2XX_MH_MMU_INVALIDATE … #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL … #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC … #define REG_A2XX_MH_MMU_MPU_BASE … #define REG_A2XX_MH_MMU_MPU_END … #define REG_A2XX_NQWAIT_UNTIL … #define REG_A2XX_RBBM_PERFCOUNTER0_SELECT … #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT … #define REG_A2XX_RBBM_PERFCOUNTER0_LO … #define REG_A2XX_RBBM_PERFCOUNTER0_HI … #define REG_A2XX_RBBM_PERFCOUNTER1_LO … #define REG_A2XX_RBBM_PERFCOUNTER1_HI … #define REG_A2XX_RBBM_DEBUG … #define REG_A2XX_RBBM_PM_OVERRIDE1 … #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE … #define REG_A2XX_RBBM_PM_OVERRIDE2 … #define A2XX_RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE … #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE … #define REG_A2XX_RBBM_DEBUG_OUT … #define REG_A2XX_RBBM_DEBUG_CNTL … #define REG_A2XX_RBBM_READ_ERROR … #define REG_A2XX_RBBM_INT_CNTL … #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK … #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK … #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK … #define REG_A2XX_RBBM_INT_STATUS … #define REG_A2XX_RBBM_INT_ACK … #define REG_A2XX_MASTER_INT_SIGNAL … #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT … #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT … #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT … #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT … #define REG_A2XX_RBBM_PERIPHID1 … #define REG_A2XX_RBBM_PERIPHID2 … #define REG_A2XX_CP_PERFMON_CNTL … #define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__MASK … #define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__SHIFT … static inline uint32_t A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT(enum perf_mode_cnt val) { … } #define REG_A2XX_CP_PERFCOUNTER_SELECT … #define REG_A2XX_CP_PERFCOUNTER_LO … #define REG_A2XX_CP_PERFCOUNTER_HI … #define REG_A2XX_RBBM_STATUS … #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK … #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT … static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) { … } #define A2XX_RBBM_STATUS_TC_BUSY … #define A2XX_RBBM_STATUS_HIRQ_PENDING … #define A2XX_RBBM_STATUS_CPRQ_PENDING … #define A2XX_RBBM_STATUS_CFRQ_PENDING … #define A2XX_RBBM_STATUS_PFRQ_PENDING … #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA … #define A2XX_RBBM_STATUS_RBBM_WU_BUSY … #define A2XX_RBBM_STATUS_CP_NRT_BUSY … #define A2XX_RBBM_STATUS_MH_BUSY … #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY … #define A2XX_RBBM_STATUS_SX_BUSY … #define A2XX_RBBM_STATUS_TPC_BUSY … #define A2XX_RBBM_STATUS_SC_CNTX_BUSY … #define A2XX_RBBM_STATUS_PA_BUSY … #define A2XX_RBBM_STATUS_VGT_BUSY … #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY … #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY … #define A2XX_RBBM_STATUS_RB_CNTX_BUSY … #define A2XX_RBBM_STATUS_GUI_ACTIVE … #define REG_A2XX_MH_ARBITER_CONFIG … #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK … #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT … static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) { … } #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY … #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE … #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE … #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL … #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK … #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT … static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) { … } #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE … #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE … #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE … #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK … #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT … static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) { … } #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE … #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE … #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE … #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE … #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE … #define REG_A2XX_MH_INTERRUPT_MASK … #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR … #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR … #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT … #define REG_A2XX_MH_INTERRUPT_STATUS … #define REG_A2XX_MH_INTERRUPT_CLEAR … #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 … #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 … #define REG_A2XX_A220_VSC_BIN_SIZE … #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK … #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT … static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) { … } #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK … #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT … static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) { … } #define REG_A2XX_VSC_PIPE(i0) … static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { … } static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { … } static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { … } #define REG_A2XX_PC_DEBUG_CNTL … #define REG_A2XX_PC_DEBUG_DATA … #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS … #define REG_A2XX_GRAS_DEBUG_CNTL … #define REG_A2XX_PA_SU_DEBUG_CNTL … #define REG_A2XX_GRAS_DEBUG_DATA … #define REG_A2XX_PA_SU_DEBUG_DATA … #define REG_A2XX_PA_SU_FACE_DATA … #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK … #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT … static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) { … } #define REG_A2XX_SQ_GPR_MANAGEMENT … #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC … #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK … #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT … static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) { … } #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK … #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT … static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) { … } #define REG_A2XX_SQ_FLOW_CONTROL … #define REG_A2XX_SQ_INST_STORE_MANAGMENT … #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK … #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT … static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) { … } #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK … #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT … static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) { … } #define REG_A2XX_SQ_DEBUG_MISC … #define REG_A2XX_SQ_INT_CNTL … #define REG_A2XX_SQ_INT_STATUS … #define REG_A2XX_SQ_INT_ACK … #define REG_A2XX_SQ_DEBUG_INPUT_FSM … #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM … #define REG_A2XX_SQ_DEBUG_TP_FSM … #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 … #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 … #define REG_A2XX_SQ_DEBUG_EXP_ALLOC … #define REG_A2XX_SQ_DEBUG_PTR_BUFF … #define REG_A2XX_SQ_DEBUG_GPR_VTX … #define REG_A2XX_SQ_DEBUG_GPR_PIX … #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL … #define REG_A2XX_SQ_DEBUG_VTX_TB_0 … #define REG_A2XX_SQ_DEBUG_VTX_TB_1 … #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG … #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM … #define REG_A2XX_SQ_DEBUG_PIX_TB_0 … #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 … #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 … #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 … #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 … #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM … #define REG_A2XX_TC_CNTL_STATUS … #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE … #define REG_A2XX_TP0_CHICKEN … #define REG_A2XX_RB_BC_CONTROL … #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE … #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK … #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT … static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) { … } #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM … #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH … #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP … #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP … #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE … #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK … #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT … static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) { … } #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE … #define A2XX_RB_BC_CONTROL_CRC_MODE … #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS … #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM … #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK … #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT … static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) { … } #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE … #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK … #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT … static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) { … } #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK … #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT … static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) { … } #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE … #define A2XX_RB_BC_CONTROL_CRC_SYSTEM … #define A2XX_RB_BC_CONTROL_RESERVED6 … #define REG_A2XX_RB_EDRAM_INFO … #define REG_A2XX_RB_DEBUG_CNTL … #define REG_A2XX_RB_DEBUG_DATA … #define REG_A2XX_RB_SURFACE_INFO … #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK … #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT … static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) { … } #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK … #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT … static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) { … } #define REG_A2XX_RB_COLOR_INFO … #define A2XX_RB_COLOR_INFO_FORMAT__MASK … #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT … static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) { … } #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK … #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT … static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) { … } #define A2XX_RB_COLOR_INFO_LINEAR … #define A2XX_RB_COLOR_INFO_ENDIAN__MASK … #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT … static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) { … } #define A2XX_RB_COLOR_INFO_SWAP__MASK … #define A2XX_RB_COLOR_INFO_SWAP__SHIFT … static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) { … } #define A2XX_RB_COLOR_INFO_BASE__MASK … #define A2XX_RB_COLOR_INFO_BASE__SHIFT … static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) { … } #define REG_A2XX_RB_DEPTH_INFO … #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK … #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) { … } #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK … #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT … static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { … } #define REG_A2XX_A225_RB_COLOR_INFO3 … #define REG_A2XX_COHER_DEST_BASE_0 … #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL … #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE … #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK … #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT … static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) { … } #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK … #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT … static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR … #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE … #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK … #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT … static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) { … } #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK … #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT … static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A2XX_PA_SC_WINDOW_OFFSET … #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK … #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) { … } #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK … #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) { … } #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE … #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL … #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE … #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK … #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT … static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) { … } #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK … #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT … static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR … #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE … #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK … #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT … static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) { … } #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK … #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT … static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A2XX_UNKNOWN_2010 … #define REG_A2XX_VGT_MAX_VTX_INDX … #define REG_A2XX_VGT_MIN_VTX_INDX … #define REG_A2XX_VGT_INDX_OFFSET … #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX … #define REG_A2XX_RB_COLOR_MASK … #define A2XX_RB_COLOR_MASK_WRITE_RED … #define A2XX_RB_COLOR_MASK_WRITE_GREEN … #define A2XX_RB_COLOR_MASK_WRITE_BLUE … #define A2XX_RB_COLOR_MASK_WRITE_ALPHA … #define REG_A2XX_RB_BLEND_RED … #define REG_A2XX_RB_BLEND_GREEN … #define REG_A2XX_RB_BLEND_BLUE … #define REG_A2XX_RB_BLEND_ALPHA … #define REG_A2XX_RB_FOG_COLOR … #define A2XX_RB_FOG_COLOR_FOG_RED__MASK … #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT … static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) { … } #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK … #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT … static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) { … } #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK … #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT … static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) { … } #define REG_A2XX_RB_STENCILREFMASK_BF … #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK … #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT … static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) { … } #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK … #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT … static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) { … } #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK … #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT … static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) { … } #define REG_A2XX_RB_STENCILREFMASK … #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK … #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT … static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) { … } #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK … #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT … static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) { … } #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK … #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT … static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) { … } #define REG_A2XX_RB_ALPHA_REF … #define REG_A2XX_PA_CL_VPORT_XSCALE … #define A2XX_PA_CL_VPORT_XSCALE__MASK … #define A2XX_PA_CL_VPORT_XSCALE__SHIFT … static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) { … } #define REG_A2XX_PA_CL_VPORT_XOFFSET … #define A2XX_PA_CL_VPORT_XOFFSET__MASK … #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT … static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) { … } #define REG_A2XX_PA_CL_VPORT_YSCALE … #define A2XX_PA_CL_VPORT_YSCALE__MASK … #define A2XX_PA_CL_VPORT_YSCALE__SHIFT … static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) { … } #define REG_A2XX_PA_CL_VPORT_YOFFSET … #define A2XX_PA_CL_VPORT_YOFFSET__MASK … #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT … static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) { … } #define REG_A2XX_PA_CL_VPORT_ZSCALE … #define A2XX_PA_CL_VPORT_ZSCALE__MASK … #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT … static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) { … } #define REG_A2XX_PA_CL_VPORT_ZOFFSET … #define A2XX_PA_CL_VPORT_ZOFFSET__MASK … #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT … static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) { … } #define REG_A2XX_SQ_PROGRAM_CNTL … #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK … #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT … static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) { … } #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK … #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT … static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) { … } #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE … #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE … #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN … #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX … #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK … #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT … static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) { … } #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK … #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT … static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) { … } #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK … #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT … static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) { … } #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX … #define REG_A2XX_SQ_CONTEXT_MISC … #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE … #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY … #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK … #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT … static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) { … } #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK … #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT … static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) { … } #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF … #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE … #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL … #define REG_A2XX_SQ_INTERPOLATOR_CNTL … #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK … #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT … static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) { … } #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK … #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT … static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) { … } #define REG_A2XX_SQ_WRAPPING_0 … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) { … } #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) { … } #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) { … } #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) { … } #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) { … } #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) { … } #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) { … } #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK … #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) { … } #define REG_A2XX_SQ_WRAPPING_1 … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) { … } #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) { … } #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) { … } #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) { … } #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) { … } #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) { … } #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) { … } #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK … #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT … static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) { … } #define REG_A2XX_SQ_PS_PROGRAM … #define A2XX_SQ_PS_PROGRAM_BASE__MASK … #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT … static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) { … } #define A2XX_SQ_PS_PROGRAM_SIZE__MASK … #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT … static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) { … } #define REG_A2XX_SQ_VS_PROGRAM … #define A2XX_SQ_VS_PROGRAM_BASE__MASK … #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT … static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) { … } #define A2XX_SQ_VS_PROGRAM_SIZE__MASK … #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT … static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) { … } #define REG_A2XX_VGT_EVENT_INITIATOR … #define REG_A2XX_VGT_DRAW_INITIATOR … #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK … #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT … static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) { … } #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK … #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT … static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK … #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT … static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK … #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT … static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) { … } #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP … #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX … #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE … #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK … #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT … static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) { … } #define REG_A2XX_VGT_IMMED_DATA … #define REG_A2XX_RB_DEPTHCONTROL … #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE … #define A2XX_RB_DEPTHCONTROL_Z_ENABLE … #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE … #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE … #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK … #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) { … } #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE … #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) { … } #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) { … } #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) { … } #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) { … } #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) { … } #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) { … } #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) { … } #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK … #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT … static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) { … } #define REG_A2XX_RB_BLEND_CONTROL … #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK … #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT … static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) { … } #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK … #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT … static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) { … } #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK … #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT … static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) { … } #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK … #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT … static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) { … } #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK … #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT … static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) { … } #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK … #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT … static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) { … } #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE … #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE … #define REG_A2XX_RB_COLORCONTROL … #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK … #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) { … } #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE … #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE … #define A2XX_RB_COLORCONTROL_BLEND_DISABLE … #define A2XX_RB_COLORCONTROL_VOB_ENABLE … #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG … #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK … #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) { … } #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK … #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) { … } #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK … #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) { … } #define A2XX_RB_COLORCONTROL_PIXEL_FOG … #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK … #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) { … } #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK … #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) { … } #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK … #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) { … } #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK … #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT … static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) { … } #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX … #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK … #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT … static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) { … } #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK … #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT … static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) { … } #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK … #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT … static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) { … } #define REG_A2XX_PA_CL_CLIP_CNTL … #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE … #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA … #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK … #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT … static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) { … } #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT … #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR … #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN … #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN … #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN … #define REG_A2XX_PA_SU_SC_MODE_CNTL … #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT … #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK … #define A2XX_PA_SU_SC_MODE_CNTL_FACE … #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK … #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT … static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) { … } #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK … #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT … static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK … #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT … static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST … #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS … #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA … #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI … #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE … #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS … #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS … #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE … #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE … #define REG_A2XX_PA_CL_VTE_CNTL … #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA … #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA … #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA … #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA … #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA … #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA … #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT … #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT … #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT … #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF … #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN … #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK … #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT … static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) { … } #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK … #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT … static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) { … } #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK … #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT … static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) { … } #define REG_A2XX_RB_MODECONTROL … #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK … #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT … static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) { … } #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL … #define REG_A2XX_RB_SAMPLE_POS … #define REG_A2XX_CLEAR_COLOR … #define A2XX_CLEAR_COLOR_RED__MASK … #define A2XX_CLEAR_COLOR_RED__SHIFT … static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) { … } #define A2XX_CLEAR_COLOR_GREEN__MASK … #define A2XX_CLEAR_COLOR_GREEN__SHIFT … static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) { … } #define A2XX_CLEAR_COLOR_BLUE__MASK … #define A2XX_CLEAR_COLOR_BLUE__SHIFT … static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) { … } #define A2XX_CLEAR_COLOR_ALPHA__MASK … #define A2XX_CLEAR_COLOR_ALPHA__SHIFT … static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) { … } #define REG_A2XX_A220_GRAS_CONTROL … #define REG_A2XX_PA_SU_POINT_SIZE … #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK … #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT … static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) { … } #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK … #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT … static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) { … } #define REG_A2XX_PA_SU_POINT_MINMAX … #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK … #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT … static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) { … } #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK … #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT … static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) { … } #define REG_A2XX_PA_SU_LINE_CNTL … #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK … #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT … static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) { … } #define REG_A2XX_PA_SC_LINE_STIPPLE … #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK … #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT … static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) { … } #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK … #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT … static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) { … } #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK … #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT … static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) { … } #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK … #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT … static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) { … } #define REG_A2XX_PA_SC_VIZ_QUERY … #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA … #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK … #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT … static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) { … } #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z … #define REG_A2XX_VGT_ENHANCE … #define REG_A2XX_PA_SC_LINE_CNTL … #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK … #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT … static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) { … } #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL … #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH … #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL … #define REG_A2XX_PA_SC_AA_CONFIG … #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK … #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT … static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) { … } #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK … #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT … static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) { … } #define REG_A2XX_PA_SU_VTX_CNTL … #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK … #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT … static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) { … } #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK … #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT … static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) { … } #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK … #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT … static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) { … } #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ … #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK … #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT … static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) { … } #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ … #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK … #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT … static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) { … } #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ … #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK … #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT … static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) { … } #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ … #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK … #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT … static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) { … } #define REG_A2XX_SQ_VS_CONST … #define A2XX_SQ_VS_CONST_BASE__MASK … #define A2XX_SQ_VS_CONST_BASE__SHIFT … static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) { … } #define A2XX_SQ_VS_CONST_SIZE__MASK … #define A2XX_SQ_VS_CONST_SIZE__SHIFT … static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) { … } #define REG_A2XX_SQ_PS_CONST … #define A2XX_SQ_PS_CONST_BASE__MASK … #define A2XX_SQ_PS_CONST_BASE__SHIFT … static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) { … } #define A2XX_SQ_PS_CONST_SIZE__MASK … #define A2XX_SQ_PS_CONST_SIZE__SHIFT … static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) { … } #define REG_A2XX_SQ_DEBUG_MISC_0 … #define REG_A2XX_SQ_DEBUG_MISC_1 … #define REG_A2XX_PA_SC_AA_MASK … #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL … #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK … #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT … static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) { … } #define REG_A2XX_VGT_OUT_DEALLOC_CNTL … #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK … #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT … static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) { … } #define REG_A2XX_RB_COPY_CONTROL … #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK … #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT … static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) { … } #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE … #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK … #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT … static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) { … } #define REG_A2XX_RB_COPY_DEST_BASE … #define REG_A2XX_RB_COPY_DEST_PITCH … #define A2XX_RB_COPY_DEST_PITCH__MASK … #define A2XX_RB_COPY_DEST_PITCH__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) { … } #define REG_A2XX_RB_COPY_DEST_INFO … #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK … #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) { … } #define A2XX_RB_COPY_DEST_INFO_LINEAR … #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK … #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) { … } #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK … #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) { … } #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK … #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) { … } #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK … #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) { … } #define A2XX_RB_COPY_DEST_INFO_WRITE_RED … #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN … #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE … #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA … #define REG_A2XX_RB_COPY_DEST_OFFSET … #define A2XX_RB_COPY_DEST_OFFSET_X__MASK … #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) { … } #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK … #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT … static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) { … } #define REG_A2XX_RB_DEPTH_CLEAR … #define REG_A2XX_RB_SAMPLE_COUNT_CTL … #define REG_A2XX_RB_COLOR_DEST_MASK … #define REG_A2XX_A225_GRAS_UCP0X … #define REG_A2XX_A225_GRAS_UCP5W … #define REG_A2XX_A225_GRAS_UCP_ENABLED … #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE … #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET … #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE … #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET … #define REG_A2XX_SQ_CONSTANT_0 … #define REG_A2XX_SQ_FETCH_0 … #define REG_A2XX_SQ_CF_BOOLEANS … #define REG_A2XX_SQ_CF_LOOP … #define REG_A2XX_COHER_SIZE_PM4 … #define REG_A2XX_COHER_BASE_PM4 … #define REG_A2XX_COHER_STATUS_PM4 … #define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT … #define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT … #define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT … #define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT … #define REG_A2XX_PA_SU_PERFCOUNTER0_LOW … #define REG_A2XX_PA_SU_PERFCOUNTER0_HI … #define REG_A2XX_PA_SU_PERFCOUNTER1_LOW … #define REG_A2XX_PA_SU_PERFCOUNTER1_HI … #define REG_A2XX_PA_SU_PERFCOUNTER2_LOW … #define REG_A2XX_PA_SU_PERFCOUNTER2_HI … #define REG_A2XX_PA_SU_PERFCOUNTER3_LOW … #define REG_A2XX_PA_SU_PERFCOUNTER3_HI … #define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT … #define REG_A2XX_PA_SC_PERFCOUNTER0_LOW … #define REG_A2XX_PA_SC_PERFCOUNTER0_HI … #define REG_A2XX_VGT_PERFCOUNTER0_SELECT … #define REG_A2XX_VGT_PERFCOUNTER1_SELECT … #define REG_A2XX_VGT_PERFCOUNTER2_SELECT … #define REG_A2XX_VGT_PERFCOUNTER3_SELECT … #define REG_A2XX_VGT_PERFCOUNTER0_LOW … #define REG_A2XX_VGT_PERFCOUNTER1_LOW … #define REG_A2XX_VGT_PERFCOUNTER2_LOW … #define REG_A2XX_VGT_PERFCOUNTER3_LOW … #define REG_A2XX_VGT_PERFCOUNTER0_HI … #define REG_A2XX_VGT_PERFCOUNTER1_HI … #define REG_A2XX_VGT_PERFCOUNTER2_HI … #define REG_A2XX_VGT_PERFCOUNTER3_HI … #define REG_A2XX_TCR_PERFCOUNTER0_SELECT … #define REG_A2XX_TCR_PERFCOUNTER1_SELECT … #define REG_A2XX_TCR_PERFCOUNTER0_HI … #define REG_A2XX_TCR_PERFCOUNTER1_HI … #define REG_A2XX_TCR_PERFCOUNTER0_LOW … #define REG_A2XX_TCR_PERFCOUNTER1_LOW … #define REG_A2XX_TP0_PERFCOUNTER0_SELECT … #define REG_A2XX_TP0_PERFCOUNTER0_HI … #define REG_A2XX_TP0_PERFCOUNTER0_LOW … #define REG_A2XX_TP0_PERFCOUNTER1_SELECT … #define REG_A2XX_TP0_PERFCOUNTER1_HI … #define REG_A2XX_TP0_PERFCOUNTER1_LOW … #define REG_A2XX_TCM_PERFCOUNTER0_SELECT … #define REG_A2XX_TCM_PERFCOUNTER1_SELECT … #define REG_A2XX_TCM_PERFCOUNTER0_HI … #define REG_A2XX_TCM_PERFCOUNTER1_HI … #define REG_A2XX_TCM_PERFCOUNTER0_LOW … #define REG_A2XX_TCM_PERFCOUNTER1_LOW … #define REG_A2XX_TCF_PERFCOUNTER0_SELECT … #define REG_A2XX_TCF_PERFCOUNTER1_SELECT … #define REG_A2XX_TCF_PERFCOUNTER2_SELECT … #define REG_A2XX_TCF_PERFCOUNTER3_SELECT … #define REG_A2XX_TCF_PERFCOUNTER4_SELECT … #define REG_A2XX_TCF_PERFCOUNTER5_SELECT … #define REG_A2XX_TCF_PERFCOUNTER6_SELECT … #define REG_A2XX_TCF_PERFCOUNTER7_SELECT … #define REG_A2XX_TCF_PERFCOUNTER8_SELECT … #define REG_A2XX_TCF_PERFCOUNTER9_SELECT … #define REG_A2XX_TCF_PERFCOUNTER10_SELECT … #define REG_A2XX_TCF_PERFCOUNTER11_SELECT … #define REG_A2XX_TCF_PERFCOUNTER0_HI … #define REG_A2XX_TCF_PERFCOUNTER1_HI … #define REG_A2XX_TCF_PERFCOUNTER2_HI … #define REG_A2XX_TCF_PERFCOUNTER3_HI … #define REG_A2XX_TCF_PERFCOUNTER4_HI … #define REG_A2XX_TCF_PERFCOUNTER5_HI … #define REG_A2XX_TCF_PERFCOUNTER6_HI … #define REG_A2XX_TCF_PERFCOUNTER7_HI … #define REG_A2XX_TCF_PERFCOUNTER8_HI … #define REG_A2XX_TCF_PERFCOUNTER9_HI … #define REG_A2XX_TCF_PERFCOUNTER10_HI … #define REG_A2XX_TCF_PERFCOUNTER11_HI … #define REG_A2XX_TCF_PERFCOUNTER0_LOW … #define REG_A2XX_TCF_PERFCOUNTER1_LOW … #define REG_A2XX_TCF_PERFCOUNTER2_LOW … #define REG_A2XX_TCF_PERFCOUNTER3_LOW … #define REG_A2XX_TCF_PERFCOUNTER4_LOW … #define REG_A2XX_TCF_PERFCOUNTER5_LOW … #define REG_A2XX_TCF_PERFCOUNTER6_LOW … #define REG_A2XX_TCF_PERFCOUNTER7_LOW … #define REG_A2XX_TCF_PERFCOUNTER8_LOW … #define REG_A2XX_TCF_PERFCOUNTER9_LOW … #define REG_A2XX_TCF_PERFCOUNTER10_LOW … #define REG_A2XX_TCF_PERFCOUNTER11_LOW … #define REG_A2XX_SQ_PERFCOUNTER0_SELECT … #define REG_A2XX_SQ_PERFCOUNTER1_SELECT … #define REG_A2XX_SQ_PERFCOUNTER2_SELECT … #define REG_A2XX_SQ_PERFCOUNTER3_SELECT … #define REG_A2XX_SQ_PERFCOUNTER0_LOW … #define REG_A2XX_SQ_PERFCOUNTER0_HI … #define REG_A2XX_SQ_PERFCOUNTER1_LOW … #define REG_A2XX_SQ_PERFCOUNTER1_HI … #define REG_A2XX_SQ_PERFCOUNTER2_LOW … #define REG_A2XX_SQ_PERFCOUNTER2_HI … #define REG_A2XX_SQ_PERFCOUNTER3_LOW … #define REG_A2XX_SQ_PERFCOUNTER3_HI … #define REG_A2XX_SX_PERFCOUNTER0_SELECT … #define REG_A2XX_SX_PERFCOUNTER0_LOW … #define REG_A2XX_SX_PERFCOUNTER0_HI … #define REG_A2XX_MH_PERFCOUNTER0_SELECT … #define REG_A2XX_MH_PERFCOUNTER1_SELECT … #define REG_A2XX_MH_PERFCOUNTER0_CONFIG … #define REG_A2XX_MH_PERFCOUNTER1_CONFIG … #define REG_A2XX_MH_PERFCOUNTER0_LOW … #define REG_A2XX_MH_PERFCOUNTER1_LOW … #define REG_A2XX_MH_PERFCOUNTER0_HI … #define REG_A2XX_MH_PERFCOUNTER1_HI … #define REG_A2XX_RB_PERFCOUNTER0_SELECT … #define REG_A2XX_RB_PERFCOUNTER1_SELECT … #define REG_A2XX_RB_PERFCOUNTER2_SELECT … #define REG_A2XX_RB_PERFCOUNTER3_SELECT … #define REG_A2XX_RB_PERFCOUNTER0_LOW … #define REG_A2XX_RB_PERFCOUNTER0_HI … #define REG_A2XX_RB_PERFCOUNTER1_LOW … #define REG_A2XX_RB_PERFCOUNTER1_HI … #define REG_A2XX_RB_PERFCOUNTER2_LOW … #define REG_A2XX_RB_PERFCOUNTER2_HI … #define REG_A2XX_RB_PERFCOUNTER3_LOW … #define REG_A2XX_RB_PERFCOUNTER3_HI … #define REG_A2XX_SQ_TEX_0 … #define A2XX_SQ_TEX_0_TYPE__MASK … #define A2XX_SQ_TEX_0_TYPE__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) { … } #define A2XX_SQ_TEX_0_SIGN_X__MASK … #define A2XX_SQ_TEX_0_SIGN_X__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) { … } #define A2XX_SQ_TEX_0_SIGN_Y__MASK … #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) { … } #define A2XX_SQ_TEX_0_SIGN_Z__MASK … #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) { … } #define A2XX_SQ_TEX_0_SIGN_W__MASK … #define A2XX_SQ_TEX_0_SIGN_W__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) { … } #define A2XX_SQ_TEX_0_CLAMP_X__MASK … #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) { … } #define A2XX_SQ_TEX_0_CLAMP_Y__MASK … #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) { … } #define A2XX_SQ_TEX_0_CLAMP_Z__MASK … #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) { … } #define A2XX_SQ_TEX_0_PITCH__MASK … #define A2XX_SQ_TEX_0_PITCH__SHIFT … static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) { … } #define A2XX_SQ_TEX_0_TILED … #define REG_A2XX_SQ_TEX_1 … #define A2XX_SQ_TEX_1_FORMAT__MASK … #define A2XX_SQ_TEX_1_FORMAT__SHIFT … static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) { … } #define A2XX_SQ_TEX_1_ENDIANNESS__MASK … #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT … static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) { … } #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK … #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT … static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) { … } #define A2XX_SQ_TEX_1_STACKED … #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK … #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT … static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) { … } #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK … #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT … static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) { … } #define REG_A2XX_SQ_TEX_2 … #define A2XX_SQ_TEX_2_WIDTH__MASK … #define A2XX_SQ_TEX_2_WIDTH__SHIFT … static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) { … } #define A2XX_SQ_TEX_2_HEIGHT__MASK … #define A2XX_SQ_TEX_2_HEIGHT__SHIFT … static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) { … } #define A2XX_SQ_TEX_2_DEPTH__MASK … #define A2XX_SQ_TEX_2_DEPTH__SHIFT … static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) { … } #define REG_A2XX_SQ_TEX_3 … #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK … #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) { … } #define A2XX_SQ_TEX_3_SWIZ_X__MASK … #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) { … } #define A2XX_SQ_TEX_3_SWIZ_Y__MASK … #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) { … } #define A2XX_SQ_TEX_3_SWIZ_Z__MASK … #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) { … } #define A2XX_SQ_TEX_3_SWIZ_W__MASK … #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) { … } #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK … #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val) { … } #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK … #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) { … } #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK … #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) { … } #define A2XX_SQ_TEX_3_MIP_FILTER__MASK … #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) { … } #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK … #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) { … } #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK … #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT … static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) { … } #define REG_A2XX_SQ_TEX_4 … #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK … #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT … static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) { … } #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK … #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT … static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) { … } #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK … #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT … static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) { … } #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK … #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT … static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) { … } #define A2XX_SQ_TEX_4_MAX_ANISO_WALK … #define A2XX_SQ_TEX_4_MIN_ANISO_WALK … #define A2XX_SQ_TEX_4_LOD_BIAS__MASK … #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT … static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) { … } #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK … #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT … static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) { … } #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK … #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT … static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) { … } #define REG_A2XX_SQ_TEX_5 … #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK … #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT … static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) { … } #define A2XX_SQ_TEX_5_FORCE_BCW_MAX … #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK … #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT … static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) { … } #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK … #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT … static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) { … } #define A2XX_SQ_TEX_5_DIMENSION__MASK … #define A2XX_SQ_TEX_5_DIMENSION__SHIFT … static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) { … } #define A2XX_SQ_TEX_5_PACKED_MIPS … #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK … #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT … static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) { … } #ifdef __cplusplus #endif #endif /* A2XX_XML */
Codebase Browser
linux