#ifndef A3XX_XML #define A3XX_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/a3xx.xml ( 84333 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml ( 85907 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum a3xx_tile_mode { … }; enum a3xx_state_block_id { … }; enum a3xx_cache_opcode { … }; enum a3xx_vtx_fmt { … }; enum a3xx_tex_fmt { … }; enum a3xx_color_fmt { … }; enum a3xx_cp_perfcounter_select { … }; enum a3xx_gras_tse_perfcounter_select { … }; enum a3xx_gras_ras_perfcounter_select { … }; enum a3xx_hlsq_perfcounter_select { … }; enum a3xx_pc_perfcounter_select { … }; enum a3xx_rb_perfcounter_select { … }; enum a3xx_rbbm_perfcounter_select { … }; enum a3xx_sp_perfcounter_select { … }; enum a3xx_tp_perfcounter_select { … }; enum a3xx_vfd_perfcounter_select { … }; enum a3xx_vpc_perfcounter_select { … }; enum a3xx_uche_perfcounter_select { … }; enum a3xx_intp_mode { … }; enum a3xx_repl_mode { … }; enum a3xx_tex_filter { … }; enum a3xx_tex_clamp { … }; enum a3xx_tex_aniso { … }; enum a3xx_tex_swiz { … }; enum a3xx_tex_type { … }; enum a3xx_tex_msaa { … }; #define A3XX_INT0_RBBM_GPU_IDLE … #define A3XX_INT0_RBBM_AHB_ERROR … #define A3XX_INT0_RBBM_REG_TIMEOUT … #define A3XX_INT0_RBBM_ME_MS_TIMEOUT … #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT … #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW … #define A3XX_INT0_VFD_ERROR … #define A3XX_INT0_CP_SW_INT … #define A3XX_INT0_CP_T0_PACKET_IN_IB … #define A3XX_INT0_CP_OPCODE_ERROR … #define A3XX_INT0_CP_RESERVED_BIT_ERROR … #define A3XX_INT0_CP_HW_FAULT … #define A3XX_INT0_CP_DMA … #define A3XX_INT0_CP_IB2_INT … #define A3XX_INT0_CP_IB1_INT … #define A3XX_INT0_CP_RB_INT … #define A3XX_INT0_CP_REG_PROTECT_FAULT … #define A3XX_INT0_CP_RB_DONE_TS … #define A3XX_INT0_CP_VS_DONE_TS … #define A3XX_INT0_CP_PS_DONE_TS … #define A3XX_INT0_CACHE_FLUSH_TS … #define A3XX_INT0_CP_AHB_ERROR_HALT … #define A3XX_INT0_MISC_HANG_DETECT … #define A3XX_INT0_UCHE_OOB_ACCESS … #define REG_A3XX_RBBM_HW_VERSION … #define REG_A3XX_RBBM_HW_RELEASE … #define REG_A3XX_RBBM_HW_CONFIGURATION … #define REG_A3XX_RBBM_CLOCK_CTL … #define REG_A3XX_RBBM_SP_HYST_CNT … #define REG_A3XX_RBBM_SW_RESET_CMD … #define REG_A3XX_RBBM_AHB_CTL0 … #define REG_A3XX_RBBM_AHB_CTL1 … #define REG_A3XX_RBBM_AHB_CMD … #define REG_A3XX_RBBM_AHB_ERROR_STATUS … #define REG_A3XX_RBBM_GPR0_CTL … #define REG_A3XX_RBBM_STATUS … #define A3XX_RBBM_STATUS_HI_BUSY … #define A3XX_RBBM_STATUS_CP_ME_BUSY … #define A3XX_RBBM_STATUS_CP_PFP_BUSY … #define A3XX_RBBM_STATUS_CP_NRT_BUSY … #define A3XX_RBBM_STATUS_VBIF_BUSY … #define A3XX_RBBM_STATUS_TSE_BUSY … #define A3XX_RBBM_STATUS_RAS_BUSY … #define A3XX_RBBM_STATUS_RB_BUSY … #define A3XX_RBBM_STATUS_PC_DCALL_BUSY … #define A3XX_RBBM_STATUS_PC_VSD_BUSY … #define A3XX_RBBM_STATUS_VFD_BUSY … #define A3XX_RBBM_STATUS_VPC_BUSY … #define A3XX_RBBM_STATUS_UCHE_BUSY … #define A3XX_RBBM_STATUS_SP_BUSY … #define A3XX_RBBM_STATUS_TPL1_BUSY … #define A3XX_RBBM_STATUS_MARB_BUSY … #define A3XX_RBBM_STATUS_VSC_BUSY … #define A3XX_RBBM_STATUS_ARB_BUSY … #define A3XX_RBBM_STATUS_HLSQ_BUSY … #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC … #define A3XX_RBBM_STATUS_GPU_BUSY … #define REG_A3XX_RBBM_NQWAIT_UNTIL … #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL … #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL … #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 … #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 … #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 … #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 … #define REG_A3XX_RBBM_INT_SET_CMD … #define REG_A3XX_RBBM_INT_CLEAR_CMD … #define REG_A3XX_RBBM_INT_0_MASK … #define REG_A3XX_RBBM_INT_0_STATUS … #define REG_A3XX_RBBM_PERFCTR_CTL … #define A3XX_RBBM_PERFCTR_CTL_ENABLE … #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 … #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 … #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO … #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI … #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT … #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT … #define REG_A3XX_RBBM_GPU_BUSY_MASKED … #define REG_A3XX_RBBM_PERFCTR_CP_0_LO … #define REG_A3XX_RBBM_PERFCTR_CP_0_HI … #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO … #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI … #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO … #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI … #define REG_A3XX_RBBM_PERFCTR_PC_0_LO … #define REG_A3XX_RBBM_PERFCTR_PC_0_HI … #define REG_A3XX_RBBM_PERFCTR_PC_1_LO … #define REG_A3XX_RBBM_PERFCTR_PC_1_HI … #define REG_A3XX_RBBM_PERFCTR_PC_2_LO … #define REG_A3XX_RBBM_PERFCTR_PC_2_HI … #define REG_A3XX_RBBM_PERFCTR_PC_3_LO … #define REG_A3XX_RBBM_PERFCTR_PC_3_HI … #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO … #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI … #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO … #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI … #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO … #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI … #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO … #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI … #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO … #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI … #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO … #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI … #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO … #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI … #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO … #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI … #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO … #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI … #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO … #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI … #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO … #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI … #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO … #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI … #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO … #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI … #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO … #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI … #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO … #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI … #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO … #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI … #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO … #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI … #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO … #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI … #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO … #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI … #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO … #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI … #define REG_A3XX_RBBM_PERFCTR_TP_0_LO … #define REG_A3XX_RBBM_PERFCTR_TP_0_HI … #define REG_A3XX_RBBM_PERFCTR_TP_1_LO … #define REG_A3XX_RBBM_PERFCTR_TP_1_HI … #define REG_A3XX_RBBM_PERFCTR_TP_2_LO … #define REG_A3XX_RBBM_PERFCTR_TP_2_HI … #define REG_A3XX_RBBM_PERFCTR_TP_3_LO … #define REG_A3XX_RBBM_PERFCTR_TP_3_HI … #define REG_A3XX_RBBM_PERFCTR_TP_4_LO … #define REG_A3XX_RBBM_PERFCTR_TP_4_HI … #define REG_A3XX_RBBM_PERFCTR_TP_5_LO … #define REG_A3XX_RBBM_PERFCTR_TP_5_HI … #define REG_A3XX_RBBM_PERFCTR_SP_0_LO … #define REG_A3XX_RBBM_PERFCTR_SP_0_HI … #define REG_A3XX_RBBM_PERFCTR_SP_1_LO … #define REG_A3XX_RBBM_PERFCTR_SP_1_HI … #define REG_A3XX_RBBM_PERFCTR_SP_2_LO … #define REG_A3XX_RBBM_PERFCTR_SP_2_HI … #define REG_A3XX_RBBM_PERFCTR_SP_3_LO … #define REG_A3XX_RBBM_PERFCTR_SP_3_HI … #define REG_A3XX_RBBM_PERFCTR_SP_4_LO … #define REG_A3XX_RBBM_PERFCTR_SP_4_HI … #define REG_A3XX_RBBM_PERFCTR_SP_5_LO … #define REG_A3XX_RBBM_PERFCTR_SP_5_HI … #define REG_A3XX_RBBM_PERFCTR_SP_6_LO … #define REG_A3XX_RBBM_PERFCTR_SP_6_HI … #define REG_A3XX_RBBM_PERFCTR_SP_7_LO … #define REG_A3XX_RBBM_PERFCTR_SP_7_HI … #define REG_A3XX_RBBM_PERFCTR_RB_0_LO … #define REG_A3XX_RBBM_PERFCTR_RB_0_HI … #define REG_A3XX_RBBM_PERFCTR_RB_1_LO … #define REG_A3XX_RBBM_PERFCTR_RB_1_HI … #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO … #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI … #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO … #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI … #define REG_A3XX_RBBM_RBBM_CTL … #define REG_A3XX_RBBM_DEBUG_BUS_CTL … #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS … #define REG_A3XX_CP_PFP_UCODE_ADDR … #define REG_A3XX_CP_PFP_UCODE_DATA … #define REG_A3XX_CP_ROQ_ADDR … #define REG_A3XX_CP_ROQ_DATA … #define REG_A3XX_CP_MERCIU_ADDR … #define REG_A3XX_CP_MERCIU_DATA … #define REG_A3XX_CP_MERCIU_DATA2 … #define REG_A3XX_CP_MEQ_ADDR … #define REG_A3XX_CP_MEQ_DATA … #define REG_A3XX_CP_WFI_PEND_CTR … #define REG_A3XX_RBBM_PM_OVERRIDE2 … #define REG_A3XX_CP_PERFCOUNTER_SELECT … #define REG_A3XX_CP_HW_FAULT … #define REG_A3XX_CP_PROTECT_CTRL … #define REG_A3XX_CP_PROTECT_STATUS … #define REG_A3XX_CP_PROTECT(i0) … static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { … } #define REG_A3XX_CP_AHB_FAULT … #define REG_A3XX_SQ_GPR_MANAGEMENT … #define REG_A3XX_SQ_INST_STORE_MANAGMENT … #define REG_A3XX_TP0_CHICKEN … #define REG_A3XX_SP_GLOBAL_MEM_SIZE … #define REG_A3XX_SP_GLOBAL_MEM_ADDR … #define REG_A3XX_GRAS_CL_CLIP_CNTL … #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER … #define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER … #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID … #define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID … #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE … #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE … #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE … #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE … #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE … #define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z … #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD … #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD … #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE … #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK … #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT … static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) { … } #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ … #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK … #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT … static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) { … } #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK … #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT … static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) { … } #define REG_A3XX_GRAS_CL_VPORT_XOFFSET … #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK … #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT … static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) { … } #define REG_A3XX_GRAS_CL_VPORT_XSCALE … #define A3XX_GRAS_CL_VPORT_XSCALE__MASK … #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT … static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) { … } #define REG_A3XX_GRAS_CL_VPORT_YOFFSET … #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK … #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT … static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) { … } #define REG_A3XX_GRAS_CL_VPORT_YSCALE … #define A3XX_GRAS_CL_VPORT_YSCALE__MASK … #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT … static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) { … } #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET … #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK … #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT … static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) { … } #define REG_A3XX_GRAS_CL_VPORT_ZSCALE … #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK … #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT … static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) { … } #define REG_A3XX_GRAS_SU_POINT_MINMAX … #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK … #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT … static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) { … } #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK … #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT … static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) { … } #define REG_A3XX_GRAS_SU_POINT_SIZE … #define A3XX_GRAS_SU_POINT_SIZE__MASK … #define A3XX_GRAS_SU_POINT_SIZE__SHIFT … static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) { … } #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE … #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK … #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT … static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) { … } #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET … #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK … #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT … static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) { … } #define REG_A3XX_GRAS_SU_MODE_CONTROL … #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT … #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK … #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW … #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK … #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT … static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) { … } #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET … #define REG_A3XX_GRAS_SC_CONTROL … #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK … #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT … static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) { … } #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK … #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT … static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) { … } #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK … #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT … static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) { … } #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL … #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE … #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK … #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT … static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) { … } #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK … #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT … static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR … #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE … #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK … #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT … static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) { … } #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK … #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT … static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL … #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE … #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK … #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT … static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) { … } #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK … #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT … static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR … #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE … #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK … #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT … static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) { … } #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK … #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT … static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A3XX_RB_MODE_CONTROL … #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS … #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK … #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT … static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) { … } #define A3XX_RB_MODE_CONTROL_MRT__MASK … #define A3XX_RB_MODE_CONTROL_MRT__SHIFT … static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) { … } #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE … #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE … #define REG_A3XX_RB_RENDER_CONTROL … #define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE … #define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE … #define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE … #define A3XX_RB_RENDER_CONTROL_FACENESS … #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK … #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT … static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) { … } #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE … #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM … #define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK … #define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT … static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val) { … } #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE … #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE … #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST … #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK … #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT … static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) { … } #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE … #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE … #define REG_A3XX_RB_MSAA_CONTROL … #define A3XX_RB_MSAA_CONTROL_DISABLE … #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK … #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT … static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) { … } #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK … #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT … static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) { … } #define REG_A3XX_RB_ALPHA_REF … #define A3XX_RB_ALPHA_REF_UINT__MASK … #define A3XX_RB_ALPHA_REF_UINT__SHIFT … static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) { … } #define A3XX_RB_ALPHA_REF_FLOAT__MASK … #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT … static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) { … } #define REG_A3XX_RB_MRT(i0) … static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { … } #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE … #define A3XX_RB_MRT_CONTROL_BLEND … #define A3XX_RB_MRT_CONTROL_BLEND2 … #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK … #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT … static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) { … } #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK … #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT … static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) { … } #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK … #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT … static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) { … } static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { … } #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK … #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) { … } #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK … #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT … static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) { … } #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK … #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB … #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK … #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT … static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) { … } static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { … } #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK … #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT … static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) { … } static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { … } #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK … #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT … static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK … #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT … static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK … #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT … static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK … #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT … static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK … #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT … static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK … #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT … static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE … #define REG_A3XX_RB_BLEND_RED … #define A3XX_RB_BLEND_RED_UINT__MASK … #define A3XX_RB_BLEND_RED_UINT__SHIFT … static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) { … } #define A3XX_RB_BLEND_RED_FLOAT__MASK … #define A3XX_RB_BLEND_RED_FLOAT__SHIFT … static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) { … } #define REG_A3XX_RB_BLEND_GREEN … #define A3XX_RB_BLEND_GREEN_UINT__MASK … #define A3XX_RB_BLEND_GREEN_UINT__SHIFT … static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) { … } #define A3XX_RB_BLEND_GREEN_FLOAT__MASK … #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT … static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) { … } #define REG_A3XX_RB_BLEND_BLUE … #define A3XX_RB_BLEND_BLUE_UINT__MASK … #define A3XX_RB_BLEND_BLUE_UINT__SHIFT … static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) { … } #define A3XX_RB_BLEND_BLUE_FLOAT__MASK … #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT … static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) { … } #define REG_A3XX_RB_BLEND_ALPHA … #define A3XX_RB_BLEND_ALPHA_UINT__MASK … #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT … static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) { … } #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK … #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT … static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) { … } #define REG_A3XX_RB_CLEAR_COLOR_DW0 … #define REG_A3XX_RB_CLEAR_COLOR_DW1 … #define REG_A3XX_RB_CLEAR_COLOR_DW2 … #define REG_A3XX_RB_CLEAR_COLOR_DW3 … #define REG_A3XX_RB_COPY_CONTROL … #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK … #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT … static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) { … } #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR … #define A3XX_RB_COPY_CONTROL_MODE__MASK … #define A3XX_RB_COPY_CONTROL_MODE__SHIFT … static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) { … } #define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE … #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK … #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT … static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) { … } #define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE … #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK … #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT … static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) { … } #define REG_A3XX_RB_COPY_DEST_BASE … #define A3XX_RB_COPY_DEST_BASE_BASE__MASK … #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) { … } #define REG_A3XX_RB_COPY_DEST_PITCH … #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK … #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) { … } #define REG_A3XX_RB_COPY_DEST_INFO … #define A3XX_RB_COPY_DEST_INFO_TILE__MASK … #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) { … } #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK … #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) { … } #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK … #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) { … } #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK … #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) { … } #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK … #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) { … } #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK … #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT … static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) { … } #define REG_A3XX_RB_DEPTH_CONTROL … #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z … #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE … #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE … #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE … #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK … #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT … static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) { … } #define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE … #define A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE … #define REG_A3XX_RB_DEPTH_CLEAR … #define REG_A3XX_RB_DEPTH_INFO … #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK … #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) { … } #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK … #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT … static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { … } #define REG_A3XX_RB_DEPTH_PITCH … #define A3XX_RB_DEPTH_PITCH__MASK … #define A3XX_RB_DEPTH_PITCH__SHIFT … static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) { … } #define REG_A3XX_RB_STENCIL_CONTROL … #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE … #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF … #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ … #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK … #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) { … } #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK … #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) { … } #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK … #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) { … } #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK … #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) { … } #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK … #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) { … } #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK … #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) { … } #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK … #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) { … } #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK … #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT … static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) { … } #define REG_A3XX_RB_STENCIL_CLEAR … #define REG_A3XX_RB_STENCIL_INFO … #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK … #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT … static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) { … } #define REG_A3XX_RB_STENCIL_PITCH … #define A3XX_RB_STENCIL_PITCH__MASK … #define A3XX_RB_STENCIL_PITCH__SHIFT … static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) { … } #define REG_A3XX_RB_STENCILREFMASK … #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK … #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT … static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) { … } #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK … #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT … static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) { … } #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK … #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT … static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) { … } #define REG_A3XX_RB_STENCILREFMASK_BF … #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK … #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT … static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) { … } #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK … #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT … static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) { … } #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK … #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT … static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) { … } #define REG_A3XX_RB_LRZ_VSC_CONTROL … #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE … #define REG_A3XX_RB_WINDOW_OFFSET … #define A3XX_RB_WINDOW_OFFSET_X__MASK … #define A3XX_RB_WINDOW_OFFSET_X__SHIFT … static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) { … } #define A3XX_RB_WINDOW_OFFSET_Y__MASK … #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT … static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) { … } #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL … #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET … #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY … #define REG_A3XX_RB_SAMPLE_COUNT_ADDR … #define REG_A3XX_RB_Z_CLAMP_MIN … #define REG_A3XX_RB_Z_CLAMP_MAX … #define REG_A3XX_VGT_BIN_BASE … #define REG_A3XX_VGT_BIN_SIZE … #define REG_A3XX_PC_VSTREAM_CONTROL … #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK … #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT … static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) { … } #define A3XX_PC_VSTREAM_CONTROL_N__MASK … #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT … static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) { … } #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL … #define REG_A3XX_PC_PRIM_VTX_CNTL … #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK … #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT … static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) { … } #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK … #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT … static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK … #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT … static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE … #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART … #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST … #define A3XX_PC_PRIM_VTX_CNTL_PSIZE … #define REG_A3XX_PC_RESTART_INDEX … #define REG_A3XX_HLSQ_CONTROL_0_REG … #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK … #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) { … } #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE … #define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE … #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART … #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 … #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK … #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX … #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE … #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK … #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE … #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE … #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE … #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT … #define REG_A3XX_HLSQ_CONTROL_1_REG … #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK … #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) { … } #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE … #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK … #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK … #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) { … } #define REG_A3XX_HLSQ_CONTROL_2_REG … #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK … #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK … #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK … #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) { … } #define REG_A3XX_HLSQ_CONTROL_3_REG … #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK … #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK … #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK … #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val) { … } #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK … #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT … static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val) { … } #define REG_A3XX_HLSQ_VS_CONTROL_REG … #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK … #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK … #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT … static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) { … } #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK … #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A3XX_HLSQ_FS_CONTROL_REG … #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK … #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK … #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT … static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) { … } #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK … #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG … #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK … #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT … static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) { … } #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK … #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT … static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) { … } #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG … #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK … #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT … static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) { … } #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK … #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT … static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) { … } #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG … #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK … #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT … static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) { … } #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK … #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT … static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) { … } #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK … #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT … static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) { … } #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK … #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT … static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) { … } #define REG_A3XX_HLSQ_CL_GLOBAL_WORK(i0) … static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { … } static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { … } #define REG_A3XX_HLSQ_CL_CONTROL_0_REG … #define REG_A3XX_HLSQ_CL_CONTROL_1_REG … #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG … #define REG_A3XX_HLSQ_CL_KERNEL_GROUP(i0) … static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { … } #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG … #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG … #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG … #define REG_A3XX_VFD_CONTROL_0 … #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK … #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) { … } #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK … #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) { … } #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK … #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) { … } #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK … #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) { … } #define REG_A3XX_VFD_CONTROL_1 … #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK … #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) { … } #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK … #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) { … } #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK … #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) { … } #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK … #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) { … } #define A3XX_VFD_CONTROL_1_REGID4INST__MASK … #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT … static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) { … } #define REG_A3XX_VFD_INDEX_MIN … #define REG_A3XX_VFD_INDEX_MAX … #define REG_A3XX_VFD_INSTANCEID_OFFSET … #define REG_A3XX_VFD_INDEX_OFFSET … #define REG_A3XX_VFD_FETCH(i0) … static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { … } #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK … #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT … static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) { … } #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK … #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT … static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) { … } #define A3XX_VFD_FETCH_INSTR_0_INSTANCED … #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT … #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK … #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT … static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) { … } #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK … #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT … static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) { … } static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { … } #define REG_A3XX_VFD_DECODE(i0) … static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { … } #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK … #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT … static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) { … } #define A3XX_VFD_DECODE_INSTR_CONSTFILL … #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK … #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT … static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) { … } #define A3XX_VFD_DECODE_INSTR_REGID__MASK … #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT … static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) { … } #define A3XX_VFD_DECODE_INSTR_INT … #define A3XX_VFD_DECODE_INSTR_SWAP__MASK … #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT … static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) { … } #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK … #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT … static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) { … } #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID … #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT … #define REG_A3XX_VFD_VS_THREADING_THRESHOLD … #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK … #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT … static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) { … } #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK … #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT … static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) { … } #define REG_A3XX_VPC_ATTR … #define A3XX_VPC_ATTR_TOTALATTR__MASK … #define A3XX_VPC_ATTR_TOTALATTR__SHIFT … static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) { … } #define A3XX_VPC_ATTR_PSIZE … #define A3XX_VPC_ATTR_THRDASSIGN__MASK … #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT … static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) { … } #define A3XX_VPC_ATTR_LMSIZE__MASK … #define A3XX_VPC_ATTR_LMSIZE__SHIFT … static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) { … } #define REG_A3XX_VPC_PACK … #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK … #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT … static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) { … } #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK … #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT … static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) { … } #define REG_A3XX_VPC_VARYING_INTERP(i0) … static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) { … } #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK … #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT … static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) { … } #define REG_A3XX_VPC_VARYING_PS_REPL(i0) … static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) { … } #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK … #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT … static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) { … } #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 … #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 … #define REG_A3XX_SP_SP_CTRL_REG … #define A3XX_SP_SP_CTRL_REG_RESOLVE … #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK … #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT … static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) { … } #define A3XX_SP_SP_CTRL_REG_BINNING … #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK … #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT … static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) { … } #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK … #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT … static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) { … } #define REG_A3XX_SP_VS_CTRL_REG0 … #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK … #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK … #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) { … } #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID … #define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE … #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK … #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE … #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK … #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) { … } #define REG_A3XX_SP_VS_CTRL_REG1 … #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK … #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) { … } #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK … #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) { … } #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK … #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT … static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) { … } #define REG_A3XX_SP_VS_PARAM_REG … #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK … #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT … static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) { … } #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK … #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT … static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) { … } #define A3XX_SP_VS_PARAM_REG_POS2DMODE … #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK … #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT … static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) { … } #define REG_A3XX_SP_VS_OUT(i0) … static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { … } #define A3XX_SP_VS_OUT_REG_A_REGID__MASK … #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) { … } #define A3XX_SP_VS_OUT_REG_A_HALF … #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK … #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A3XX_SP_VS_OUT_REG_B_REGID__MASK … #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) { … } #define A3XX_SP_VS_OUT_REG_B_HALF … #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK … #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A3XX_SP_VS_VPC_DST(i0) … static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { … } #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK … #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK … #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK … #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK … #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A3XX_SP_VS_OBJ_OFFSET_REG … #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK … #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT … static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) { … } #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK … #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK … #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A3XX_SP_VS_OBJ_START_REG … #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG … #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK … #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT … static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) { … } #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK … #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT … static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) { … } #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK … #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG … #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK … #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT … static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) { … } #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK … #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT … static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) { … } #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG … #define REG_A3XX_SP_VS_LENGTH_REG … #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK … #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT … static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) { … } #define REG_A3XX_SP_FS_CTRL_REG0 … #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK … #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK … #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) { … } #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID … #define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE … #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE … #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP … #define A3XX_SP_FS_CTRL_REG0_OUTORDERED … #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK … #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE … #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE … #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE … #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK … #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) { … } #define REG_A3XX_SP_FS_CTRL_REG1 … #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK … #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) { … } #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK … #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) { … } #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK … #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) { … } #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK … #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT … static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) { … } #define REG_A3XX_SP_FS_OBJ_OFFSET_REG … #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK … #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT … static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) { … } #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK … #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK … #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A3XX_SP_FS_OBJ_START_REG … #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG … #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK … #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT … static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) { … } #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK … #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT … static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) { … } #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK … #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT … static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) { … } #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG … #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK … #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT … static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) { … } #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK … #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT … static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) { … } #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG … #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 … #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 … #define REG_A3XX_SP_FS_OUTPUT_REG … #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK … #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT … static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) { … } #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE … #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK … #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT … static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) { … } #define REG_A3XX_SP_FS_MRT(i0) … static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { … } #define A3XX_SP_FS_MRT_REG_REGID__MASK … #define A3XX_SP_FS_MRT_REG_REGID__SHIFT … static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) { … } #define A3XX_SP_FS_MRT_REG_HALF_PRECISION … #define A3XX_SP_FS_MRT_REG_SINT … #define A3XX_SP_FS_MRT_REG_UINT … #define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) … static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { … } #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK … #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT … static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) { … } #define REG_A3XX_SP_FS_LENGTH_REG … #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK … #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT … static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) { … } #define REG_A3XX_PA_SC_AA_CONFIG … #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET … #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK … #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT … static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) { … } #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK … #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT … static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) { … } #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK … #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT … static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) { … } #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR … #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET … #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK … #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT … static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) { … } #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK … #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT … static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) { … } #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK … #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT … static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) { … } #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR … #define REG_A3XX_VBIF_CLKON … #define REG_A3XX_VBIF_FIXED_SORT_EN … #define REG_A3XX_VBIF_FIXED_SORT_SEL0 … #define REG_A3XX_VBIF_FIXED_SORT_SEL1 … #define REG_A3XX_VBIF_ABIT_SORT … #define REG_A3XX_VBIF_ABIT_SORT_CONF … #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN … #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 … #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 … #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 … #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 … #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 … #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 … #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST … #define REG_A3XX_VBIF_ARB_CTL … #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB … #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 … #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN … #define REG_A3XX_VBIF_OUT_AXI_AOOO … #define REG_A3XX_VBIF_PERF_CNT_EN … #define A3XX_VBIF_PERF_CNT_EN_CNT0 … #define A3XX_VBIF_PERF_CNT_EN_CNT1 … #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 … #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 … #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 … #define REG_A3XX_VBIF_PERF_CNT_CLR … #define A3XX_VBIF_PERF_CNT_CLR_CNT0 … #define A3XX_VBIF_PERF_CNT_CLR_CNT1 … #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 … #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 … #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 … #define REG_A3XX_VBIF_PERF_CNT_SEL … #define REG_A3XX_VBIF_PERF_CNT0_LO … #define REG_A3XX_VBIF_PERF_CNT0_HI … #define REG_A3XX_VBIF_PERF_CNT1_LO … #define REG_A3XX_VBIF_PERF_CNT1_HI … #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO … #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI … #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO … #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI … #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO … #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI … #define REG_A3XX_VSC_BIN_SIZE … #define A3XX_VSC_BIN_SIZE_WIDTH__MASK … #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT … static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { … } #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK … #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT … static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { … } #define REG_A3XX_VSC_SIZE_ADDRESS … #define REG_A3XX_VSC_PIPE(i0) … static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { … } #define A3XX_VSC_PIPE_CONFIG_X__MASK … #define A3XX_VSC_PIPE_CONFIG_X__SHIFT … static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) { … } #define A3XX_VSC_PIPE_CONFIG_Y__MASK … #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT … static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) { … } #define A3XX_VSC_PIPE_CONFIG_W__MASK … #define A3XX_VSC_PIPE_CONFIG_W__SHIFT … static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) { … } #define A3XX_VSC_PIPE_CONFIG_H__MASK … #define A3XX_VSC_PIPE_CONFIG_H__SHIFT … static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) { … } static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { … } static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { … } #define REG_A3XX_VSC_BIN_CONTROL … #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE … #define REG_A3XX_UNKNOWN_0C3D … #define REG_A3XX_PC_PERFCOUNTER0_SELECT … #define REG_A3XX_PC_PERFCOUNTER1_SELECT … #define REG_A3XX_PC_PERFCOUNTER2_SELECT … #define REG_A3XX_PC_PERFCOUNTER3_SELECT … #define REG_A3XX_GRAS_TSE_DEBUG_ECO … #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT … #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT … #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT … #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT … #define REG_A3XX_GRAS_CL_USER_PLANE(i0) … static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { … } static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { … } static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { … } static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { … } #define REG_A3XX_RB_GMEM_BASE_ADDR … #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR … #define REG_A3XX_RB_PERFCOUNTER0_SELECT … #define REG_A3XX_RB_PERFCOUNTER1_SELECT … #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION … #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK … #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT … static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) { … } #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK … #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT … static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) { … } #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT … #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT … #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT … #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT … #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT … #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT … #define REG_A3XX_UNKNOWN_0E43 … #define REG_A3XX_VFD_PERFCOUNTER0_SELECT … #define REG_A3XX_VFD_PERFCOUNTER1_SELECT … #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL … #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ … #define REG_A3XX_VPC_PERFCOUNTER0_SELECT … #define REG_A3XX_VPC_PERFCOUNTER1_SELECT … #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG … #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT … #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT … #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT … #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT … #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT … #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT … #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG … #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK … #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT … static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) { … } #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG … #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK … #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT … static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) { … } #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK … #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT … static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) { … } #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE … #define REG_A3XX_UNKNOWN_0EA6 … #define REG_A3XX_SP_PERFCOUNTER0_SELECT … #define REG_A3XX_SP_PERFCOUNTER1_SELECT … #define REG_A3XX_SP_PERFCOUNTER2_SELECT … #define REG_A3XX_SP_PERFCOUNTER3_SELECT … #define REG_A3XX_SP_PERFCOUNTER4_SELECT … #define REG_A3XX_SP_PERFCOUNTER5_SELECT … #define REG_A3XX_SP_PERFCOUNTER6_SELECT … #define REG_A3XX_SP_PERFCOUNTER7_SELECT … #define REG_A3XX_UNKNOWN_0EE0 … #define REG_A3XX_UNKNOWN_0F03 … #define REG_A3XX_TP_PERFCOUNTER0_SELECT … #define REG_A3XX_TP_PERFCOUNTER1_SELECT … #define REG_A3XX_TP_PERFCOUNTER2_SELECT … #define REG_A3XX_TP_PERFCOUNTER3_SELECT … #define REG_A3XX_TP_PERFCOUNTER4_SELECT … #define REG_A3XX_TP_PERFCOUNTER5_SELECT … #define REG_A3XX_VGT_CL_INITIATOR … #define REG_A3XX_VGT_EVENT_INITIATOR … #define REG_A3XX_VGT_DRAW_INITIATOR … #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK … #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT … static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) { … } #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK … #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT … static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) { … } #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK … #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT … static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) { … } #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK … #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT … static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) { … } #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP … #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX … #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE … #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK … #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT … static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) { … } #define REG_A3XX_VGT_IMMED_DATA … #define REG_A3XX_TEX_SAMP_0 … #define A3XX_TEX_SAMP_0_CLAMPENABLE … #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR … #define A3XX_TEX_SAMP_0_XY_MAG__MASK … #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT … static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) { … } #define A3XX_TEX_SAMP_0_XY_MIN__MASK … #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT … static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) { … } #define A3XX_TEX_SAMP_0_WRAP_S__MASK … #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT … static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) { … } #define A3XX_TEX_SAMP_0_WRAP_T__MASK … #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT … static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) { … } #define A3XX_TEX_SAMP_0_WRAP_R__MASK … #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT … static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) { … } #define A3XX_TEX_SAMP_0_ANISO__MASK … #define A3XX_TEX_SAMP_0_ANISO__SHIFT … static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) { … } #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK … #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT … static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) { … } #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF … #define A3XX_TEX_SAMP_0_UNNORM_COORDS … #define REG_A3XX_TEX_SAMP_1 … #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK … #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT … static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) { … } #define A3XX_TEX_SAMP_1_MAX_LOD__MASK … #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT … static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) { … } #define A3XX_TEX_SAMP_1_MIN_LOD__MASK … #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT … static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) { … } #define REG_A3XX_TEX_CONST_0 … #define A3XX_TEX_CONST_0_TILE_MODE__MASK … #define A3XX_TEX_CONST_0_TILE_MODE__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val) { … } #define A3XX_TEX_CONST_0_SRGB … #define A3XX_TEX_CONST_0_SWIZ_X__MASK … #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) { … } #define A3XX_TEX_CONST_0_SWIZ_Y__MASK … #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) { … } #define A3XX_TEX_CONST_0_SWIZ_Z__MASK … #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) { … } #define A3XX_TEX_CONST_0_SWIZ_W__MASK … #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) { … } #define A3XX_TEX_CONST_0_MIPLVLS__MASK … #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) { … } #define A3XX_TEX_CONST_0_MSAATEX__MASK … #define A3XX_TEX_CONST_0_MSAATEX__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) { … } #define A3XX_TEX_CONST_0_FMT__MASK … #define A3XX_TEX_CONST_0_FMT__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) { … } #define A3XX_TEX_CONST_0_NOCONVERT … #define A3XX_TEX_CONST_0_TYPE__MASK … #define A3XX_TEX_CONST_0_TYPE__SHIFT … static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) { … } #define REG_A3XX_TEX_CONST_1 … #define A3XX_TEX_CONST_1_HEIGHT__MASK … #define A3XX_TEX_CONST_1_HEIGHT__SHIFT … static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) { … } #define A3XX_TEX_CONST_1_WIDTH__MASK … #define A3XX_TEX_CONST_1_WIDTH__SHIFT … static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) { … } #define A3XX_TEX_CONST_1_PITCHALIGN__MASK … #define A3XX_TEX_CONST_1_PITCHALIGN__SHIFT … static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val) { … } #define REG_A3XX_TEX_CONST_2 … #define A3XX_TEX_CONST_2_INDX__MASK … #define A3XX_TEX_CONST_2_INDX__SHIFT … static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) { … } #define A3XX_TEX_CONST_2_PITCH__MASK … #define A3XX_TEX_CONST_2_PITCH__SHIFT … static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) { … } #define A3XX_TEX_CONST_2_SWAP__MASK … #define A3XX_TEX_CONST_2_SWAP__SHIFT … static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) { … } #define REG_A3XX_TEX_CONST_3 … #define A3XX_TEX_CONST_3_LAYERSZ1__MASK … #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT … static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) { … } #define A3XX_TEX_CONST_3_DEPTH__MASK … #define A3XX_TEX_CONST_3_DEPTH__SHIFT … static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) { … } #define A3XX_TEX_CONST_3_LAYERSZ2__MASK … #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT … static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) { … } #ifdef __cplusplus #endif #endif /* A3XX_XML */
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