#ifndef A4XX_XML #define A4XX_XML /* Autogenerated file, DO NOT EDIT manually! This file was generated by the rules-ng-ng gen_header.py tool in this git repository: http://gitlab.freedesktop.org/mesa/mesa/ git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/a4xx.xml ( 113484 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/freedreno_copyright.xml ( 1582 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml ( 15485 bytes, from Fri Aug 9 23:22:40 2024) - /var/lib/territory/DaFxbRzcpd9fAwobsLd9/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml ( 85907 bytes, from Fri Aug 9 23:22:40 2024) Copyright (C) 2013-2024 by the following authors: - Rob Clark <[email protected]> Rob Clark - Ilia Mirkin <[email protected]> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice (including the next paragraph) shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifdef __KERNEL__ #include <linux/bug.h> #define assert(x) … #else #include <assert.h> #endif #ifdef __cplusplus #define __struct_cast … #else #define __struct_cast(X) … #endif enum a4xx_color_fmt { … }; enum a4xx_tile_mode { … }; enum a4xx_vtx_fmt { … }; enum a4xx_tex_fmt { … }; enum a4xx_depth_format { … }; enum a4xx_ccu_perfcounter_select { … }; enum a4xx_cp_perfcounter_select { … }; enum a4xx_gras_ras_perfcounter_select { … }; enum a4xx_gras_tse_perfcounter_select { … }; enum a4xx_hlsq_perfcounter_select { … }; enum a4xx_pc_perfcounter_select { … }; enum a4xx_pwr_perfcounter_select { … }; enum a4xx_rb_perfcounter_select { … }; enum a4xx_rbbm_perfcounter_select { … }; enum a4xx_sp_perfcounter_select { … }; enum a4xx_tp_perfcounter_select { … }; enum a4xx_uche_perfcounter_select { … }; enum a4xx_vbif_perfcounter_select { … }; enum a4xx_vfd_perfcounter_select { … }; enum a4xx_vpc_perfcounter_select { … }; enum a4xx_vsc_perfcounter_select { … }; enum a4xx_tex_filter { … }; enum a4xx_tex_clamp { … }; enum a4xx_tex_aniso { … }; enum a4xx_tex_swiz { … }; enum a4xx_tex_type { … }; #define A4XX_CGC_HLSQ_EARLY_CYC__MASK … #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT … static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) { … } #define A4XX_INT0_RBBM_GPU_IDLE … #define A4XX_INT0_RBBM_AHB_ERROR … #define A4XX_INT0_RBBM_REG_TIMEOUT … #define A4XX_INT0_RBBM_ME_MS_TIMEOUT … #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT … #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW … #define A4XX_INT0_VFD_ERROR … #define A4XX_INT0_CP_SW_INT … #define A4XX_INT0_CP_T0_PACKET_IN_IB … #define A4XX_INT0_CP_OPCODE_ERROR … #define A4XX_INT0_CP_RESERVED_BIT_ERROR … #define A4XX_INT0_CP_HW_FAULT … #define A4XX_INT0_CP_DMA … #define A4XX_INT0_CP_IB2_INT … #define A4XX_INT0_CP_IB1_INT … #define A4XX_INT0_CP_RB_INT … #define A4XX_INT0_CP_REG_PROTECT_FAULT … #define A4XX_INT0_CP_RB_DONE_TS … #define A4XX_INT0_CP_VS_DONE_TS … #define A4XX_INT0_CP_PS_DONE_TS … #define A4XX_INT0_CACHE_FLUSH_TS … #define A4XX_INT0_CP_AHB_ERROR_HALT … #define A4XX_INT0_MISC_HANG_DETECT … #define A4XX_INT0_UCHE_OOB_ACCESS … #define REG_A4XX_RB_GMEM_BASE_ADDR … #define REG_A4XX_RB_PERFCTR_RB_SEL_0 … #define REG_A4XX_RB_PERFCTR_RB_SEL_1 … #define REG_A4XX_RB_PERFCTR_RB_SEL_2 … #define REG_A4XX_RB_PERFCTR_RB_SEL_3 … #define REG_A4XX_RB_PERFCTR_RB_SEL_4 … #define REG_A4XX_RB_PERFCTR_RB_SEL_5 … #define REG_A4XX_RB_PERFCTR_RB_SEL_6 … #define REG_A4XX_RB_PERFCTR_RB_SEL_7 … #define REG_A4XX_RB_PERFCTR_CCU_SEL_0 … #define REG_A4XX_RB_PERFCTR_CCU_SEL_1 … #define REG_A4XX_RB_PERFCTR_CCU_SEL_2 … #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 … #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION … #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK … #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT … static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) { … } #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK … #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT … static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) { … } #define REG_A4XX_RB_CLEAR_COLOR_DW0 … #define REG_A4XX_RB_CLEAR_COLOR_DW1 … #define REG_A4XX_RB_CLEAR_COLOR_DW2 … #define REG_A4XX_RB_CLEAR_COLOR_DW3 … #define REG_A4XX_RB_MODE_CONTROL … #define A4XX_RB_MODE_CONTROL_WIDTH__MASK … #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT … static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) { … } #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK … #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT … static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) { … } #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM … #define REG_A4XX_RB_RENDER_CONTROL … #define A4XX_RB_RENDER_CONTROL_BINNING_PASS … #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE … #define REG_A4XX_RB_MSAA_CONTROL … #define A4XX_RB_MSAA_CONTROL_DISABLE … #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK … #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT … static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) { … } #define REG_A4XX_RB_RENDER_CONTROL2 … #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK … #define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT … static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val) { … } #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK … #define A4XX_RB_RENDER_CONTROL2_FACENESS … #define A4XX_RB_RENDER_CONTROL2_SAMPLEID … #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK … #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT … static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) { … } #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR … #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL … #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID … #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE … #define A4XX_RB_RENDER_CONTROL2_SIZE … #define REG_A4XX_RB_MRT(i0) … static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { … } #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE … #define A4XX_RB_MRT_CONTROL_BLEND … #define A4XX_RB_MRT_CONTROL_BLEND2 … #define A4XX_RB_MRT_CONTROL_ROP_ENABLE … #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK … #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT … static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) { … } #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK … #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT … static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) { … } static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { … } #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK … #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT … static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) { … } #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK … #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT … static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) { … } #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK … #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT … static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) { … } #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK … #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT … static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) { … } #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB … #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK … #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT … static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) { … } static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { … } static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { … } #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK … #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT … static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) { … } static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { … } #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK … #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT … static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK … #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT … static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK … #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT … static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK … #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT … static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) { … } #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK … #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT … static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) { … } #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK … #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT … static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) { … } #define REG_A4XX_RB_BLEND_RED … #define A4XX_RB_BLEND_RED_UINT__MASK … #define A4XX_RB_BLEND_RED_UINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) { … } #define A4XX_RB_BLEND_RED_SINT__MASK … #define A4XX_RB_BLEND_RED_SINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val) { … } #define A4XX_RB_BLEND_RED_FLOAT__MASK … #define A4XX_RB_BLEND_RED_FLOAT__SHIFT … static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) { … } #define REG_A4XX_RB_BLEND_RED_F32 … #define A4XX_RB_BLEND_RED_F32__MASK … #define A4XX_RB_BLEND_RED_F32__SHIFT … static inline uint32_t A4XX_RB_BLEND_RED_F32(float val) { … } #define REG_A4XX_RB_BLEND_GREEN … #define A4XX_RB_BLEND_GREEN_UINT__MASK … #define A4XX_RB_BLEND_GREEN_UINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) { … } #define A4XX_RB_BLEND_GREEN_SINT__MASK … #define A4XX_RB_BLEND_GREEN_SINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val) { … } #define A4XX_RB_BLEND_GREEN_FLOAT__MASK … #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT … static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) { … } #define REG_A4XX_RB_BLEND_GREEN_F32 … #define A4XX_RB_BLEND_GREEN_F32__MASK … #define A4XX_RB_BLEND_GREEN_F32__SHIFT … static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val) { … } #define REG_A4XX_RB_BLEND_BLUE … #define A4XX_RB_BLEND_BLUE_UINT__MASK … #define A4XX_RB_BLEND_BLUE_UINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) { … } #define A4XX_RB_BLEND_BLUE_SINT__MASK … #define A4XX_RB_BLEND_BLUE_SINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val) { … } #define A4XX_RB_BLEND_BLUE_FLOAT__MASK … #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT … static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) { … } #define REG_A4XX_RB_BLEND_BLUE_F32 … #define A4XX_RB_BLEND_BLUE_F32__MASK … #define A4XX_RB_BLEND_BLUE_F32__SHIFT … static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val) { … } #define REG_A4XX_RB_BLEND_ALPHA … #define A4XX_RB_BLEND_ALPHA_UINT__MASK … #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) { … } #define A4XX_RB_BLEND_ALPHA_SINT__MASK … #define A4XX_RB_BLEND_ALPHA_SINT__SHIFT … static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val) { … } #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK … #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT … static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) { … } #define REG_A4XX_RB_BLEND_ALPHA_F32 … #define A4XX_RB_BLEND_ALPHA_F32__MASK … #define A4XX_RB_BLEND_ALPHA_F32__SHIFT … static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val) { … } #define REG_A4XX_RB_ALPHA_CONTROL … #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK … #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT … static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) { … } #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST … #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK … #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT … static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) { … } #define REG_A4XX_RB_FS_OUTPUT … #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK … #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT … static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) { … } #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND … #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK … #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT … static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) { … } #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL … #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY … #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK … #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT … static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) { … } #define REG_A4XX_RB_RENDER_COMPONENTS … #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) { … } #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) { … } #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) { … } #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) { … } #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) { … } #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) { … } #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) { … } #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK … #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT … static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) { … } #define REG_A4XX_RB_COPY_CONTROL … #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK … #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT … static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) { … } #define A4XX_RB_COPY_CONTROL_MODE__MASK … #define A4XX_RB_COPY_CONTROL_MODE__SHIFT … static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) { … } #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK … #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT … static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) { … } #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK … #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT … static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) { … } #define REG_A4XX_RB_COPY_DEST_BASE … #define A4XX_RB_COPY_DEST_BASE_BASE__MASK … #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) { … } #define REG_A4XX_RB_COPY_DEST_PITCH … #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK … #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) { … } #define REG_A4XX_RB_COPY_DEST_INFO … #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK … #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) { … } #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK … #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) { … } #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK … #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) { … } #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK … #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) { … } #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK … #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) { … } #define A4XX_RB_COPY_DEST_INFO_TILE__MASK … #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT … static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) { … } #define REG_A4XX_RB_FS_OUTPUT_REG … #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK … #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT … static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) { … } #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z … #define REG_A4XX_RB_DEPTH_CONTROL … #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z … #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE … #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE … #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK … #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT … static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) { … } #define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE … #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE … #define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS … #define A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE … #define REG_A4XX_RB_DEPTH_CLEAR … #define REG_A4XX_RB_DEPTH_INFO … #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK … #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT … static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) { … } #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK … #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT … static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { … } #define REG_A4XX_RB_DEPTH_PITCH … #define A4XX_RB_DEPTH_PITCH__MASK … #define A4XX_RB_DEPTH_PITCH__SHIFT … static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) { … } #define REG_A4XX_RB_DEPTH_PITCH2 … #define A4XX_RB_DEPTH_PITCH2__MASK … #define A4XX_RB_DEPTH_PITCH2__SHIFT … static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) { … } #define REG_A4XX_RB_STENCIL_CONTROL … #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE … #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF … #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ … #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK … #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) { … } #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK … #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) { … } #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK … #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) { … } #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK … #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) { … } #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK … #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) { … } #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK … #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) { … } #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK … #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) { … } #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK … #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT … static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) { … } #define REG_A4XX_RB_STENCIL_CONTROL2 … #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER … #define REG_A4XX_RB_STENCIL_INFO … #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL … #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK … #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT … static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) { … } #define REG_A4XX_RB_STENCIL_PITCH … #define A4XX_RB_STENCIL_PITCH__MASK … #define A4XX_RB_STENCIL_PITCH__SHIFT … static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) { … } #define REG_A4XX_RB_STENCILREFMASK … #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK … #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT … static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) { … } #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK … #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT … static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) { … } #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK … #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT … static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) { … } #define REG_A4XX_RB_STENCILREFMASK_BF … #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK … #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT … static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) { … } #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK … #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT … static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) { … } #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK … #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT … static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) { … } #define REG_A4XX_RB_BIN_OFFSET … #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE … #define A4XX_RB_BIN_OFFSET_X__MASK … #define A4XX_RB_BIN_OFFSET_X__SHIFT … static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) { … } #define A4XX_RB_BIN_OFFSET_Y__MASK … #define A4XX_RB_BIN_OFFSET_Y__SHIFT … static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) { … } #define REG_A4XX_RB_VPORT_Z_CLAMP(i0) … static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { … } static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { … } #define REG_A4XX_RBBM_HW_VERSION … #define REG_A4XX_RBBM_HW_CONFIGURATION … #define REG_A4XX_RBBM_CLOCK_CTL_TP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_CTL2_TP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_HYST_TP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_DELAY_TP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_CTL_UCHE … #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE … #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE … #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE … #define REG_A4XX_RBBM_CLOCK_HYST_UCHE … #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE … #define REG_A4XX_RBBM_CLOCK_MODE_GPC … #define REG_A4XX_RBBM_CLOCK_DELAY_GPC … #define REG_A4XX_RBBM_CLOCK_HYST_GPC … #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM … #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM … #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM … #define REG_A4XX_RBBM_CLOCK_CTL … #define REG_A4XX_RBBM_SP_HYST_CNT … #define REG_A4XX_RBBM_SW_RESET_CMD … #define REG_A4XX_RBBM_AHB_CTL0 … #define REG_A4XX_RBBM_AHB_CTL1 … #define REG_A4XX_RBBM_AHB_CMD … #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL … #define REG_A4XX_RBBM_RAM_ACC_63_32 … #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL … #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL … #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 … #define REG_A4XX_RBBM_INT_CLEAR_CMD … #define REG_A4XX_RBBM_INT_0_MASK … #define REG_A4XX_RBBM_RBBM_CTL … #define REG_A4XX_RBBM_AHB_DEBUG_CTL … #define REG_A4XX_RBBM_VBIF_DEBUG_CTL … #define REG_A4XX_RBBM_CLOCK_CTL2 … #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD … #define REG_A4XX_RBBM_RESET_CYCLES … #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL … #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A … #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B … #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C … #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D … #define REG_A4XX_RBBM_POWER_CNTL_IP … #define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE … #define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON … #define REG_A4XX_RBBM_PERFCTR_CP_0_LO … #define REG_A4XX_RBBM_PERFCTR_CP_0_HI … #define REG_A4XX_RBBM_PERFCTR_CP_1_LO … #define REG_A4XX_RBBM_PERFCTR_CP_1_HI … #define REG_A4XX_RBBM_PERFCTR_CP_2_LO … #define REG_A4XX_RBBM_PERFCTR_CP_2_HI … #define REG_A4XX_RBBM_PERFCTR_CP_3_LO … #define REG_A4XX_RBBM_PERFCTR_CP_3_HI … #define REG_A4XX_RBBM_PERFCTR_CP_4_LO … #define REG_A4XX_RBBM_PERFCTR_CP_4_HI … #define REG_A4XX_RBBM_PERFCTR_CP_5_LO … #define REG_A4XX_RBBM_PERFCTR_CP_5_HI … #define REG_A4XX_RBBM_PERFCTR_CP_6_LO … #define REG_A4XX_RBBM_PERFCTR_CP_6_HI … #define REG_A4XX_RBBM_PERFCTR_CP_7_LO … #define REG_A4XX_RBBM_PERFCTR_CP_7_HI … #define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO … #define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI … #define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO … #define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI … #define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO … #define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI … #define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO … #define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI … #define REG_A4XX_RBBM_PERFCTR_PC_0_LO … #define REG_A4XX_RBBM_PERFCTR_PC_0_HI … #define REG_A4XX_RBBM_PERFCTR_PC_1_LO … #define REG_A4XX_RBBM_PERFCTR_PC_1_HI … #define REG_A4XX_RBBM_PERFCTR_PC_2_LO … #define REG_A4XX_RBBM_PERFCTR_PC_2_HI … #define REG_A4XX_RBBM_PERFCTR_PC_3_LO … #define REG_A4XX_RBBM_PERFCTR_PC_3_HI … #define REG_A4XX_RBBM_PERFCTR_PC_4_LO … #define REG_A4XX_RBBM_PERFCTR_PC_4_HI … #define REG_A4XX_RBBM_PERFCTR_PC_5_LO … #define REG_A4XX_RBBM_PERFCTR_PC_5_HI … #define REG_A4XX_RBBM_PERFCTR_PC_6_LO … #define REG_A4XX_RBBM_PERFCTR_PC_6_HI … #define REG_A4XX_RBBM_PERFCTR_PC_7_LO … #define REG_A4XX_RBBM_PERFCTR_PC_7_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_0_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_0_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_1_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_1_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_2_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_2_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_3_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_3_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_4_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_4_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_5_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_5_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_6_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_6_HI … #define REG_A4XX_RBBM_PERFCTR_VFD_7_LO … #define REG_A4XX_RBBM_PERFCTR_VFD_7_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI … #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO … #define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI … #define REG_A4XX_RBBM_PERFCTR_VPC_0_LO … #define REG_A4XX_RBBM_PERFCTR_VPC_0_HI … #define REG_A4XX_RBBM_PERFCTR_VPC_1_LO … #define REG_A4XX_RBBM_PERFCTR_VPC_1_HI … #define REG_A4XX_RBBM_PERFCTR_VPC_2_LO … #define REG_A4XX_RBBM_PERFCTR_VPC_2_HI … #define REG_A4XX_RBBM_PERFCTR_VPC_3_LO … #define REG_A4XX_RBBM_PERFCTR_VPC_3_HI … #define REG_A4XX_RBBM_PERFCTR_CCU_0_LO … #define REG_A4XX_RBBM_PERFCTR_CCU_0_HI … #define REG_A4XX_RBBM_PERFCTR_CCU_1_LO … #define REG_A4XX_RBBM_PERFCTR_CCU_1_HI … #define REG_A4XX_RBBM_PERFCTR_CCU_2_LO … #define REG_A4XX_RBBM_PERFCTR_CCU_2_HI … #define REG_A4XX_RBBM_PERFCTR_CCU_3_LO … #define REG_A4XX_RBBM_PERFCTR_CCU_3_HI … #define REG_A4XX_RBBM_PERFCTR_TSE_0_LO … #define REG_A4XX_RBBM_PERFCTR_TSE_0_HI … #define REG_A4XX_RBBM_PERFCTR_TSE_1_LO … #define REG_A4XX_RBBM_PERFCTR_TSE_1_HI … #define REG_A4XX_RBBM_PERFCTR_TSE_2_LO … #define REG_A4XX_RBBM_PERFCTR_TSE_2_HI … #define REG_A4XX_RBBM_PERFCTR_TSE_3_LO … #define REG_A4XX_RBBM_PERFCTR_TSE_3_HI … #define REG_A4XX_RBBM_PERFCTR_RAS_0_LO … #define REG_A4XX_RBBM_PERFCTR_RAS_0_HI … #define REG_A4XX_RBBM_PERFCTR_RAS_1_LO … #define REG_A4XX_RBBM_PERFCTR_RAS_1_HI … #define REG_A4XX_RBBM_PERFCTR_RAS_2_LO … #define REG_A4XX_RBBM_PERFCTR_RAS_2_HI … #define REG_A4XX_RBBM_PERFCTR_RAS_3_LO … #define REG_A4XX_RBBM_PERFCTR_RAS_3_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI … #define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO … #define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI … #define REG_A4XX_RBBM_PERFCTR_TP_0_LO … #define REG_A4XX_RBBM_PERFCTR_TP_0_HI … #define REG_A4XX_RBBM_PERFCTR_TP_1_LO … #define REG_A4XX_RBBM_PERFCTR_TP_1_HI … #define REG_A4XX_RBBM_PERFCTR_TP_2_LO … #define REG_A4XX_RBBM_PERFCTR_TP_2_HI … #define REG_A4XX_RBBM_PERFCTR_TP_3_LO … #define REG_A4XX_RBBM_PERFCTR_TP_3_HI … #define REG_A4XX_RBBM_PERFCTR_TP_4_LO … #define REG_A4XX_RBBM_PERFCTR_TP_4_HI … #define REG_A4XX_RBBM_PERFCTR_TP_5_LO … #define REG_A4XX_RBBM_PERFCTR_TP_5_HI … #define REG_A4XX_RBBM_PERFCTR_TP_6_LO … #define REG_A4XX_RBBM_PERFCTR_TP_6_HI … #define REG_A4XX_RBBM_PERFCTR_TP_7_LO … #define REG_A4XX_RBBM_PERFCTR_TP_7_HI … #define REG_A4XX_RBBM_PERFCTR_SP_0_LO … #define REG_A4XX_RBBM_PERFCTR_SP_0_HI … #define REG_A4XX_RBBM_PERFCTR_SP_1_LO … #define REG_A4XX_RBBM_PERFCTR_SP_1_HI … #define REG_A4XX_RBBM_PERFCTR_SP_2_LO … #define REG_A4XX_RBBM_PERFCTR_SP_2_HI … #define REG_A4XX_RBBM_PERFCTR_SP_3_LO … #define REG_A4XX_RBBM_PERFCTR_SP_3_HI … #define REG_A4XX_RBBM_PERFCTR_SP_4_LO … #define REG_A4XX_RBBM_PERFCTR_SP_4_HI … #define REG_A4XX_RBBM_PERFCTR_SP_5_LO … #define REG_A4XX_RBBM_PERFCTR_SP_5_HI … #define REG_A4XX_RBBM_PERFCTR_SP_6_LO … #define REG_A4XX_RBBM_PERFCTR_SP_6_HI … #define REG_A4XX_RBBM_PERFCTR_SP_7_LO … #define REG_A4XX_RBBM_PERFCTR_SP_7_HI … #define REG_A4XX_RBBM_PERFCTR_SP_8_LO … #define REG_A4XX_RBBM_PERFCTR_SP_8_HI … #define REG_A4XX_RBBM_PERFCTR_SP_9_LO … #define REG_A4XX_RBBM_PERFCTR_SP_9_HI … #define REG_A4XX_RBBM_PERFCTR_SP_10_LO … #define REG_A4XX_RBBM_PERFCTR_SP_10_HI … #define REG_A4XX_RBBM_PERFCTR_SP_11_LO … #define REG_A4XX_RBBM_PERFCTR_SP_11_HI … #define REG_A4XX_RBBM_PERFCTR_RB_0_LO … #define REG_A4XX_RBBM_PERFCTR_RB_0_HI … #define REG_A4XX_RBBM_PERFCTR_RB_1_LO … #define REG_A4XX_RBBM_PERFCTR_RB_1_HI … #define REG_A4XX_RBBM_PERFCTR_RB_2_LO … #define REG_A4XX_RBBM_PERFCTR_RB_2_HI … #define REG_A4XX_RBBM_PERFCTR_RB_3_LO … #define REG_A4XX_RBBM_PERFCTR_RB_3_HI … #define REG_A4XX_RBBM_PERFCTR_RB_4_LO … #define REG_A4XX_RBBM_PERFCTR_RB_4_HI … #define REG_A4XX_RBBM_PERFCTR_RB_5_LO … #define REG_A4XX_RBBM_PERFCTR_RB_5_HI … #define REG_A4XX_RBBM_PERFCTR_RB_6_LO … #define REG_A4XX_RBBM_PERFCTR_RB_6_HI … #define REG_A4XX_RBBM_PERFCTR_RB_7_LO … #define REG_A4XX_RBBM_PERFCTR_RB_7_HI … #define REG_A4XX_RBBM_PERFCTR_VSC_0_LO … #define REG_A4XX_RBBM_PERFCTR_VSC_0_HI … #define REG_A4XX_RBBM_PERFCTR_VSC_1_LO … #define REG_A4XX_RBBM_PERFCTR_VSC_1_HI … #define REG_A4XX_RBBM_PERFCTR_PWR_0_LO … #define REG_A4XX_RBBM_PERFCTR_PWR_0_HI … #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO … #define REG_A4XX_RBBM_PERFCTR_PWR_1_HI … #define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO … #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI … #define REG_A4XX_RBBM_CLOCK_CTL_SP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_CTL2_SP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_HYST_SP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_DELAY_SP(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_CTL_RB(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_CTL2_RB(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM … #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM … #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ … #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ … #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ … #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM … #define REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i0) … static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { … } #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 … #define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 … #define REG_A4XX_RBBM_PERFCTR_CTL … #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 … #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 … #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 … #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO … #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI … #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 … #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 … #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 … #define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 … #define REG_A4XX_RBBM_GPU_BUSY_MASKED … #define REG_A4XX_RBBM_INT_0_STATUS … #define REG_A4XX_RBBM_CLOCK_STATUS … #define REG_A4XX_RBBM_AHB_STATUS … #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS … #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS … #define REG_A4XX_RBBM_AHB_ERROR_STATUS … #define REG_A4XX_RBBM_STATUS … #define A4XX_RBBM_STATUS_HI_BUSY … #define A4XX_RBBM_STATUS_CP_ME_BUSY … #define A4XX_RBBM_STATUS_CP_PFP_BUSY … #define A4XX_RBBM_STATUS_CP_NRT_BUSY … #define A4XX_RBBM_STATUS_VBIF_BUSY … #define A4XX_RBBM_STATUS_TSE_BUSY … #define A4XX_RBBM_STATUS_RAS_BUSY … #define A4XX_RBBM_STATUS_RB_BUSY … #define A4XX_RBBM_STATUS_PC_DCALL_BUSY … #define A4XX_RBBM_STATUS_PC_VSD_BUSY … #define A4XX_RBBM_STATUS_VFD_BUSY … #define A4XX_RBBM_STATUS_VPC_BUSY … #define A4XX_RBBM_STATUS_UCHE_BUSY … #define A4XX_RBBM_STATUS_SP_BUSY … #define A4XX_RBBM_STATUS_TPL1_BUSY … #define A4XX_RBBM_STATUS_MARB_BUSY … #define A4XX_RBBM_STATUS_VSC_BUSY … #define A4XX_RBBM_STATUS_ARB_BUSY … #define A4XX_RBBM_STATUS_HLSQ_BUSY … #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC … #define A4XX_RBBM_STATUS_GPU_BUSY … #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 … #define REG_A4XX_RBBM_POWER_STATUS … #define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON … #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 … #define REG_A4XX_CP_SCRATCH_UMASK … #define REG_A4XX_CP_SCRATCH_ADDR … #define REG_A4XX_CP_RB_BASE … #define REG_A4XX_CP_RB_CNTL … #define REG_A4XX_CP_RB_WPTR … #define REG_A4XX_CP_RB_RPTR_ADDR … #define REG_A4XX_CP_RB_RPTR … #define REG_A4XX_CP_IB1_BASE … #define REG_A4XX_CP_IB1_BUFSZ … #define REG_A4XX_CP_IB2_BASE … #define REG_A4XX_CP_IB2_BUFSZ … #define REG_A4XX_CP_ME_NRT_ADDR … #define REG_A4XX_CP_ME_NRT_DATA … #define REG_A4XX_CP_ME_RB_DONE_DATA … #define REG_A4XX_CP_QUEUE_THRESH2 … #define REG_A4XX_CP_MERCIU_SIZE … #define REG_A4XX_CP_ROQ_ADDR … #define REG_A4XX_CP_ROQ_DATA … #define REG_A4XX_CP_MEQ_ADDR … #define REG_A4XX_CP_MEQ_DATA … #define REG_A4XX_CP_MERCIU_ADDR … #define REG_A4XX_CP_MERCIU_DATA … #define REG_A4XX_CP_MERCIU_DATA2 … #define REG_A4XX_CP_PFP_UCODE_ADDR … #define REG_A4XX_CP_PFP_UCODE_DATA … #define REG_A4XX_CP_ME_RAM_WADDR … #define REG_A4XX_CP_ME_RAM_RADDR … #define REG_A4XX_CP_ME_RAM_DATA … #define REG_A4XX_CP_PREEMPT … #define REG_A4XX_CP_CNTL … #define REG_A4XX_CP_ME_CNTL … #define REG_A4XX_CP_DEBUG … #define REG_A4XX_CP_DEBUG_ECO_CONTROL … #define REG_A4XX_CP_DRAW_STATE_ADDR … #define REG_A4XX_CP_PROTECT(i0) … static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { … } #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK … #define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT … static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) { … } #define A4XX_CP_PROTECT_REG_MASK_LEN__MASK … #define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT … static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) { … } #define A4XX_CP_PROTECT_REG_TRAP_WRITE … #define A4XX_CP_PROTECT_REG_TRAP_READ … #define REG_A4XX_CP_PROTECT_CTRL … #define REG_A4XX_CP_ST_BASE … #define REG_A4XX_CP_STQ_AVAIL … #define REG_A4XX_CP_MERCIU_STAT … #define REG_A4XX_CP_WFI_PEND_CTR … #define REG_A4XX_CP_HW_FAULT … #define REG_A4XX_CP_PROTECT_STATUS … #define REG_A4XX_CP_EVENTS_IN_FLIGHT … #define REG_A4XX_CP_PERFCTR_CP_SEL_0 … #define REG_A4XX_CP_PERFCTR_CP_SEL_1 … #define REG_A4XX_CP_PERFCTR_CP_SEL_2 … #define REG_A4XX_CP_PERFCTR_CP_SEL_3 … #define REG_A4XX_CP_PERFCTR_CP_SEL_4 … #define REG_A4XX_CP_PERFCTR_CP_SEL_5 … #define REG_A4XX_CP_PERFCTR_CP_SEL_6 … #define REG_A4XX_CP_PERFCTR_CP_SEL_7 … #define REG_A4XX_CP_PERFCOMBINER_SELECT … #define REG_A4XX_CP_SCRATCH(i0) … static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { … } #define REG_A4XX_SP_VS_STATUS … #define REG_A4XX_SP_MODE_CONTROL … #define REG_A4XX_SP_PERFCTR_SP_SEL_0 … #define REG_A4XX_SP_PERFCTR_SP_SEL_1 … #define REG_A4XX_SP_PERFCTR_SP_SEL_2 … #define REG_A4XX_SP_PERFCTR_SP_SEL_3 … #define REG_A4XX_SP_PERFCTR_SP_SEL_4 … #define REG_A4XX_SP_PERFCTR_SP_SEL_5 … #define REG_A4XX_SP_PERFCTR_SP_SEL_6 … #define REG_A4XX_SP_PERFCTR_SP_SEL_7 … #define REG_A4XX_SP_PERFCTR_SP_SEL_8 … #define REG_A4XX_SP_PERFCTR_SP_SEL_9 … #define REG_A4XX_SP_PERFCTR_SP_SEL_10 … #define REG_A4XX_SP_PERFCTR_SP_SEL_11 … #define REG_A4XX_SP_SP_CTRL_REG … #define A4XX_SP_SP_CTRL_REG_BINNING_PASS … #define REG_A4XX_SP_INSTR_CACHE_CTRL … #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER … #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER … #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER … #define REG_A4XX_SP_VS_CTRL_REG0 … #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK … #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A4XX_SP_VS_CTRL_REG0_VARYING … #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID … #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK … #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT … static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) { … } #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK … #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE … #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE … #define REG_A4XX_SP_VS_CTRL_REG1 … #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK … #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) { … } #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK … #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT … static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) { … } #define REG_A4XX_SP_VS_PARAM_REG … #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK … #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT … static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) { … } #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK … #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT … static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) { … } #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK … #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT … static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) { … } #define REG_A4XX_SP_VS_OUT(i0) … static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { … } #define A4XX_SP_VS_OUT_REG_A_REGID__MASK … #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) { … } #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK … #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A4XX_SP_VS_OUT_REG_B_REGID__MASK … #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) { … } #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK … #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A4XX_SP_VS_VPC_DST(i0) … static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { … } #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK … #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK … #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK … #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK … #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A4XX_SP_VS_OBJ_OFFSET_REG … #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK … #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A4XX_SP_VS_OBJ_START … #define REG_A4XX_SP_VS_PVT_MEM_PARAM … #define REG_A4XX_SP_VS_PVT_MEM_ADDR … #define REG_A4XX_SP_VS_LENGTH_REG … #define REG_A4XX_SP_FS_CTRL_REG0 … #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK … #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A4XX_SP_FS_CTRL_REG0_VARYING … #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID … #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK … #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT … static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) { … } #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK … #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE … #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE … #define REG_A4XX_SP_FS_CTRL_REG1 … #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK … #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) { … } #define A4XX_SP_FS_CTRL_REG1_FACENESS … #define A4XX_SP_FS_CTRL_REG1_VARYING … #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD … #define REG_A4XX_SP_FS_OBJ_OFFSET_REG … #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK … #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A4XX_SP_FS_OBJ_START … #define REG_A4XX_SP_FS_PVT_MEM_PARAM … #define REG_A4XX_SP_FS_PVT_MEM_ADDR … #define REG_A4XX_SP_FS_LENGTH_REG … #define REG_A4XX_SP_FS_OUTPUT_REG … #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK … #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT … static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) { … } #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE … #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK … #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT … static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) { … } #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK … #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT … static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) { … } #define REG_A4XX_SP_FS_MRT(i0) … static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { … } #define A4XX_SP_FS_MRT_REG_REGID__MASK … #define A4XX_SP_FS_MRT_REG_REGID__SHIFT … static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) { … } #define A4XX_SP_FS_MRT_REG_HALF_PRECISION … #define A4XX_SP_FS_MRT_REG_COLOR_SINT … #define A4XX_SP_FS_MRT_REG_COLOR_UINT … #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK … #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT … static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) { … } #define A4XX_SP_FS_MRT_REG_COLOR_SRGB … #define REG_A4XX_SP_CS_CTRL_REG0 … #define A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK … #define A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT … static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) { … } #define A4XX_SP_CS_CTRL_REG0_VARYING … #define A4XX_SP_CS_CTRL_REG0_CACHEINVALID … #define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK … #define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT … static inline uint32_t A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) { … } #define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK … #define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT … static inline uint32_t A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) { … } #define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK … #define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT … static inline uint32_t A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) { … } #define A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK … #define A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT … static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) { … } #define A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE … #define A4XX_SP_CS_CTRL_REG0_PIXLODENABLE … #define REG_A4XX_SP_CS_OBJ_OFFSET_REG … #define REG_A4XX_SP_CS_OBJ_START … #define REG_A4XX_SP_CS_PVT_MEM_PARAM … #define REG_A4XX_SP_CS_PVT_MEM_ADDR … #define REG_A4XX_SP_CS_PVT_MEM_SIZE … #define REG_A4XX_SP_CS_LENGTH_REG … #define REG_A4XX_SP_HS_OBJ_OFFSET_REG … #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK … #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A4XX_SP_HS_OBJ_START … #define REG_A4XX_SP_HS_PVT_MEM_PARAM … #define REG_A4XX_SP_HS_PVT_MEM_ADDR … #define REG_A4XX_SP_HS_LENGTH_REG … #define REG_A4XX_SP_DS_PARAM_REG … #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK … #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT … static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) { … } #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK … #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT … static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) { … } #define REG_A4XX_SP_DS_OUT(i0) … static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { … } #define A4XX_SP_DS_OUT_REG_A_REGID__MASK … #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) { … } #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK … #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A4XX_SP_DS_OUT_REG_B_REGID__MASK … #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) { … } #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK … #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A4XX_SP_DS_VPC_DST(i0) … static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { … } #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK … #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK … #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK … #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK … #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A4XX_SP_DS_OBJ_OFFSET_REG … #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK … #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A4XX_SP_DS_OBJ_START … #define REG_A4XX_SP_DS_PVT_MEM_PARAM … #define REG_A4XX_SP_DS_PVT_MEM_ADDR … #define REG_A4XX_SP_DS_LENGTH_REG … #define REG_A4XX_SP_GS_PARAM_REG … #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK … #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT … static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) { … } #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK … #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT … static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) { … } #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK … #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT … static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) { … } #define REG_A4XX_SP_GS_OUT(i0) … static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { … } #define A4XX_SP_GS_OUT_REG_A_REGID__MASK … #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT … static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) { … } #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK … #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT … static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) { … } #define A4XX_SP_GS_OUT_REG_B_REGID__MASK … #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT … static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) { … } #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK … #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT … static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) { … } #define REG_A4XX_SP_GS_VPC_DST(i0) … static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { … } #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK … #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT … static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) { … } #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK … #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT … static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) { … } #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK … #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT … static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) { … } #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK … #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT … static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) { … } #define REG_A4XX_SP_GS_OBJ_OFFSET_REG … #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK … #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) { … } #define REG_A4XX_SP_GS_OBJ_START … #define REG_A4XX_SP_GS_PVT_MEM_PARAM … #define REG_A4XX_SP_GS_PVT_MEM_ADDR … #define REG_A4XX_SP_GS_LENGTH_REG … #define REG_A4XX_VPC_DEBUG_RAM_SEL … #define REG_A4XX_VPC_DEBUG_RAM_READ … #define REG_A4XX_VPC_DEBUG_ECO_CONTROL … #define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 … #define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 … #define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 … #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 … #define REG_A4XX_VPC_ATTR … #define A4XX_VPC_ATTR_TOTALATTR__MASK … #define A4XX_VPC_ATTR_TOTALATTR__SHIFT … static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) { … } #define A4XX_VPC_ATTR_PSIZE … #define A4XX_VPC_ATTR_THRDASSIGN__MASK … #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT … static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) { … } #define A4XX_VPC_ATTR_ENABLE … #define REG_A4XX_VPC_PACK … #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK … #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT … static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) { … } #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK … #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT … static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) { … } #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK … #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT … static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) { … } #define REG_A4XX_VPC_VARYING_INTERP(i0) … static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { … } #define REG_A4XX_VPC_VARYING_PS_REPL(i0) … static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { … } #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 … #define REG_A4XX_VSC_BIN_SIZE … #define A4XX_VSC_BIN_SIZE_WIDTH__MASK … #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT … static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { … } #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK … #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT … static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { … } #define REG_A4XX_VSC_SIZE_ADDRESS … #define REG_A4XX_VSC_SIZE_ADDRESS2 … #define REG_A4XX_VSC_DEBUG_ECO_CONTROL … #define REG_A4XX_VSC_PIPE_CONFIG(i0) … static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { … } #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK … #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT … static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) { … } #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK … #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT … static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) { … } #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK … #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT … static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) { … } #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK … #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT … static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) { … } #define REG_A4XX_VSC_PIPE_DATA_ADDRESS(i0) … static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { … } #define REG_A4XX_VSC_PIPE_DATA_LENGTH(i0) … static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { … } #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 … #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 … #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 … #define REG_A4XX_VFD_DEBUG_CONTROL … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 … #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 … #define REG_A4XX_VGT_CL_INITIATOR … #define REG_A4XX_VGT_EVENT_INITIATOR … #define REG_A4XX_VFD_CONTROL_0 … #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK … #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) { … } #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK … #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) { … } #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK … #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) { … } #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK … #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) { … } #define REG_A4XX_VFD_CONTROL_1 … #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK … #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) { … } #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK … #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) { … } #define A4XX_VFD_CONTROL_1_REGID4INST__MASK … #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) { … } #define REG_A4XX_VFD_CONTROL_2 … #define REG_A4XX_VFD_CONTROL_3 … #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK … #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) { … } #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK … #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) { … } #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK … #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT … static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) { … } #define REG_A4XX_VFD_CONTROL_4 … #define REG_A4XX_VFD_INDEX_OFFSET … #define REG_A4XX_VFD_FETCH(i0) … static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { … } #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK … #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT … static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) { … } #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK … #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT … static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) { … } #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT … #define A4XX_VFD_FETCH_INSTR_0_INSTANCED … static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { … } static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { … } #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK … #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT … static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) { … } static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { … } #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK … #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT … static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) { … } #define REG_A4XX_VFD_DECODE(i0) … static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { … } #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK … #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT … static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) { … } #define A4XX_VFD_DECODE_INSTR_CONSTFILL … #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK … #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT … static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) { … } #define A4XX_VFD_DECODE_INSTR_REGID__MASK … #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT … static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) { … } #define A4XX_VFD_DECODE_INSTR_INT … #define A4XX_VFD_DECODE_INSTR_SWAP__MASK … #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT … static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) { … } #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK … #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT … static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) { … } #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID … #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT … #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL … #define REG_A4XX_TPL1_TP_MODE_CONTROL … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 … #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 … #define REG_A4XX_TPL1_TP_TEX_OFFSET … #define REG_A4XX_TPL1_TP_TEX_COUNT … #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK … #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT … static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) { … } #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK … #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT … static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) { … } #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK … #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT … static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) { … } #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK … #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT … static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) { … } #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR … #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR … #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR … #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR … #define REG_A4XX_TPL1_TP_FS_TEX_COUNT … #define A4XX_TPL1_TP_FS_TEX_COUNT_FS__MASK … #define A4XX_TPL1_TP_FS_TEX_COUNT_FS__SHIFT … static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_FS(uint32_t val) { … } #define A4XX_TPL1_TP_FS_TEX_COUNT_CS__MASK … #define A4XX_TPL1_TP_FS_TEX_COUNT_CS__SHIFT … static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_CS(uint32_t val) { … } #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR … #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR … #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR … #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR … #define REG_A4XX_GRAS_TSE_STATUS … #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL … #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 … #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 … #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 … #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 … #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 … #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 … #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 … #define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 … #define REG_A4XX_GRAS_CL_CLIP_CNTL … #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE … #define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE … #define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE … #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z … #define REG_A4XX_GRAS_CNTL … #define A4XX_GRAS_CNTL_IJ_PERSP … #define A4XX_GRAS_CNTL_IJ_LINEAR … #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ … #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK … #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT … static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) { … } #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK … #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT … static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) { … } #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 … #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK … #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT … static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) { … } #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 … #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK … #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT … static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) { … } #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 … #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK … #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT … static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) { … } #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 … #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK … #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT … static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) { … } #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 … #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK … #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT … static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) { … } #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 … #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK … #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT … static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) { … } #define REG_A4XX_GRAS_SU_POINT_MINMAX … #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK … #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT … static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) { … } #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK … #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT … static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) { … } #define REG_A4XX_GRAS_SU_POINT_SIZE … #define A4XX_GRAS_SU_POINT_SIZE__MASK … #define A4XX_GRAS_SU_POINT_SIZE__SHIFT … static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) { … } #define REG_A4XX_GRAS_ALPHA_CONTROL … #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE … #define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS … #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE … #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK … #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT … static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) { … } #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET … #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK … #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT … static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) { … } #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP … #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK … #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT … static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) { … } #define REG_A4XX_GRAS_DEPTH_CONTROL … #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK … #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT … static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) { … } #define REG_A4XX_GRAS_SU_MODE_CONTROL … #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT … #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK … #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW … #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK … #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT … static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) { … } #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET … #define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE … #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS … #define REG_A4XX_GRAS_SC_CONTROL … #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK … #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT … static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) { … } #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK … #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT … static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) { … } #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE … #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK … #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT … static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) { … } #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL … #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE … #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK … #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT … static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) { … } #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK … #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT … static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR … #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE … #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK … #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT … static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) { … } #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK … #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT … static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR … #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE … #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK … #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT … static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) { … } #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK … #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT … static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) { … } #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL … #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE … #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK … #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT … static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) { … } #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK … #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT … static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) { … } #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR … #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE … #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK … #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT … static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) { … } #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK … #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT … static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) { … } #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL … #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE … #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK … #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT … static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) { … } #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK … #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT … static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) { … } #define REG_A4XX_UCHE_CACHE_MODE_CONTROL … #define REG_A4XX_UCHE_TRAP_BASE_LO … #define REG_A4XX_UCHE_TRAP_BASE_HI … #define REG_A4XX_UCHE_CACHE_STATUS … #define REG_A4XX_UCHE_INVALIDATE0 … #define REG_A4XX_UCHE_INVALIDATE1 … #define REG_A4XX_UCHE_CACHE_WAYS_VFD … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 … #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 … #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD … #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL … #define REG_A4XX_HLSQ_MODE_CONTROL … #define REG_A4XX_HLSQ_PERF_PIPE_MASK … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 … #define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 … #define REG_A4XX_HLSQ_CONTROL_0_REG … #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK … #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) { … } #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE … #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART … #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 … #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE … #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK … #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE … #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE … #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE … #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT … #define REG_A4XX_HLSQ_CONTROL_1_REG … #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK … #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) { … } #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE … #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 … #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK … #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK … #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) { … } #define REG_A4XX_HLSQ_CONTROL_2_REG … #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK … #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK … #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK … #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK … #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) { … } #define REG_A4XX_HLSQ_CONTROL_3_REG … #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK … #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK … #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK … #define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK … #define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) { … } #define REG_A4XX_HLSQ_CONTROL_4_REG … #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK … #define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) { … } #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK … #define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT … static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) { … } #define REG_A4XX_HLSQ_VS_CONTROL_REG … #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK … #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE … #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED … #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK … #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) { … } #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK … #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A4XX_HLSQ_FS_CONTROL_REG … #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK … #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE … #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED … #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK … #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) { … } #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK … #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A4XX_HLSQ_HS_CONTROL_REG … #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK … #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE … #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED … #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK … #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) { … } #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK … #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A4XX_HLSQ_DS_CONTROL_REG … #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK … #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE … #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED … #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK … #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) { … } #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK … #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A4XX_HLSQ_GS_CONTROL_REG … #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK … #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE … #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED … #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK … #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) { … } #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK … #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A4XX_HLSQ_CS_CONTROL_REG … #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK … #define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val) { … } #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK … #define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) { … } #define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE … #define A4XX_HLSQ_CS_CONTROL_REG_ENABLED … #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK … #define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT … static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) { … } #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK … #define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT … static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_NDRANGE_0 … #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK … #define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT … static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val) { … } #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK … #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT … static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val) { … } #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK … #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT … static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val) { … } #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK … #define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT … static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_NDRANGE_1 … #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK … #define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT … static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_NDRANGE_2 … #define REG_A4XX_HLSQ_CL_NDRANGE_3 … #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK … #define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT … static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_NDRANGE_4 … #define REG_A4XX_HLSQ_CL_NDRANGE_5 … #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK … #define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT … static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_NDRANGE_6 … #define REG_A4XX_HLSQ_CL_CONTROL_0 … #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK … #define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val) { … } #define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK … #define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val) { … } #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK … #define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_CONTROL_1 … #define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK … #define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val) { … } #define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK … #define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_KERNEL_CONST … #define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK … #define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val) { … } #define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK … #define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val) { … } #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X … #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y … #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z … #define REG_A4XX_HLSQ_CL_WG_OFFSET … #define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK … #define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT … static inline uint32_t A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val) { … } #define REG_A4XX_HLSQ_UPDATE_CONTROL … #define REG_A4XX_PC_BINNING_COMMAND … #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE … #define REG_A4XX_PC_TESSFACTOR_ADDR … #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE … #define REG_A4XX_PC_PERFCTR_PC_SEL_0 … #define REG_A4XX_PC_PERFCTR_PC_SEL_1 … #define REG_A4XX_PC_PERFCTR_PC_SEL_2 … #define REG_A4XX_PC_PERFCTR_PC_SEL_3 … #define REG_A4XX_PC_PERFCTR_PC_SEL_4 … #define REG_A4XX_PC_PERFCTR_PC_SEL_5 … #define REG_A4XX_PC_PERFCTR_PC_SEL_6 … #define REG_A4XX_PC_PERFCTR_PC_SEL_7 … #define REG_A4XX_PC_BIN_BASE … #define REG_A4XX_PC_VSTREAM_CONTROL … #define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK … #define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT … static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) { … } #define A4XX_PC_VSTREAM_CONTROL_N__MASK … #define A4XX_PC_VSTREAM_CONTROL_N__SHIFT … static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val) { … } #define REG_A4XX_PC_PRIM_VTX_CNTL … #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK … #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT … static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) { … } #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART … #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST … #define A4XX_PC_PRIM_VTX_CNTL_PSIZE … #define REG_A4XX_PC_PRIM_VTX_CNTL2 … #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK … #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT … static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK … #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT … static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) { … } #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE … #define REG_A4XX_PC_RESTART_INDEX … #define REG_A4XX_PC_GS_PARAM … #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK … #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT … static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) { … } #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK … #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT … static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) { … } #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK … #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT … static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) { … } #define A4XX_PC_GS_PARAM_LAYER … #define REG_A4XX_PC_HS_PARAM … #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK … #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT … static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) { … } #define A4XX_PC_HS_PARAM_SPACING__MASK … #define A4XX_PC_HS_PARAM_SPACING__SHIFT … static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) { … } #define A4XX_PC_HS_PARAM_CW … #define A4XX_PC_HS_PARAM_CONNECTED … #define REG_A4XX_VBIF_VERSION … #define REG_A4XX_VBIF_CLKON … #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS … #define REG_A4XX_VBIF_ABIT_SORT … #define REG_A4XX_VBIF_ABIT_SORT_CONF … #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN … #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 … #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 … #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 … #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 … #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB … #define REG_A4XX_VBIF_PERF_CNT_EN0 … #define REG_A4XX_VBIF_PERF_CNT_EN1 … #define REG_A4XX_VBIF_PERF_CNT_EN2 … #define REG_A4XX_VBIF_PERF_CNT_EN3 … #define REG_A4XX_VBIF_PERF_CNT_SEL0 … #define REG_A4XX_VBIF_PERF_CNT_SEL1 … #define REG_A4XX_VBIF_PERF_CNT_SEL2 … #define REG_A4XX_VBIF_PERF_CNT_SEL3 … #define REG_A4XX_VBIF_PERF_CNT_LOW0 … #define REG_A4XX_VBIF_PERF_CNT_LOW1 … #define REG_A4XX_VBIF_PERF_CNT_LOW2 … #define REG_A4XX_VBIF_PERF_CNT_LOW3 … #define REG_A4XX_VBIF_PERF_CNT_HIGH0 … #define REG_A4XX_VBIF_PERF_CNT_HIGH1 … #define REG_A4XX_VBIF_PERF_CNT_HIGH2 … #define REG_A4XX_VBIF_PERF_CNT_HIGH3 … #define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 … #define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 … #define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 … #define REG_A4XX_UNKNOWN_0CC5 … #define REG_A4XX_UNKNOWN_0CC6 … #define REG_A4XX_UNKNOWN_0D01 … #define REG_A4XX_UNKNOWN_0E42 … #define REG_A4XX_UNKNOWN_0EC2 … #define REG_A4XX_UNKNOWN_2001 … #define REG_A4XX_UNKNOWN_209B … #define REG_A4XX_UNKNOWN_20EF … #define REG_A4XX_UNKNOWN_2152 … #define REG_A4XX_UNKNOWN_2153 … #define REG_A4XX_UNKNOWN_2154 … #define REG_A4XX_UNKNOWN_2155 … #define REG_A4XX_UNKNOWN_2156 … #define REG_A4XX_UNKNOWN_2157 … #define REG_A4XX_UNKNOWN_21C3 … #define REG_A4XX_UNKNOWN_21E6 … #define REG_A4XX_UNKNOWN_2209 … #define REG_A4XX_UNKNOWN_22D7 … #define REG_A4XX_UNKNOWN_2352 … #define REG_A4XX_TEX_SAMP_0 … #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR … #define A4XX_TEX_SAMP_0_XY_MAG__MASK … #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT … static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) { … } #define A4XX_TEX_SAMP_0_XY_MIN__MASK … #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT … static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) { … } #define A4XX_TEX_SAMP_0_WRAP_S__MASK … #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT … static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) { … } #define A4XX_TEX_SAMP_0_WRAP_T__MASK … #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT … static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) { … } #define A4XX_TEX_SAMP_0_WRAP_R__MASK … #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT … static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) { … } #define A4XX_TEX_SAMP_0_ANISO__MASK … #define A4XX_TEX_SAMP_0_ANISO__SHIFT … static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) { … } #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK … #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT … static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val) { … } #define REG_A4XX_TEX_SAMP_1 … #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK … #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT … static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) { … } #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF … #define A4XX_TEX_SAMP_1_UNNORM_COORDS … #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR … #define A4XX_TEX_SAMP_1_MAX_LOD__MASK … #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT … static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) { … } #define A4XX_TEX_SAMP_1_MIN_LOD__MASK … #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT … static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) { … } #define REG_A4XX_TEX_CONST_0 … #define A4XX_TEX_CONST_0_TILED … #define A4XX_TEX_CONST_0_SRGB … #define A4XX_TEX_CONST_0_SWIZ_X__MASK … #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT … static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) { … } #define A4XX_TEX_CONST_0_SWIZ_Y__MASK … #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT … static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) { … } #define A4XX_TEX_CONST_0_SWIZ_Z__MASK … #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT … static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) { … } #define A4XX_TEX_CONST_0_SWIZ_W__MASK … #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT … static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) { … } #define A4XX_TEX_CONST_0_MIPLVLS__MASK … #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT … static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) { … } #define A4XX_TEX_CONST_0_FMT__MASK … #define A4XX_TEX_CONST_0_FMT__SHIFT … static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) { … } #define A4XX_TEX_CONST_0_TYPE__MASK … #define A4XX_TEX_CONST_0_TYPE__SHIFT … static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) { … } #define REG_A4XX_TEX_CONST_1 … #define A4XX_TEX_CONST_1_HEIGHT__MASK … #define A4XX_TEX_CONST_1_HEIGHT__SHIFT … static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) { … } #define A4XX_TEX_CONST_1_WIDTH__MASK … #define A4XX_TEX_CONST_1_WIDTH__SHIFT … static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) { … } #define REG_A4XX_TEX_CONST_2 … #define A4XX_TEX_CONST_2_PITCHALIGN__MASK … #define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT … static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val) { … } #define A4XX_TEX_CONST_2_BUFFER … #define A4XX_TEX_CONST_2_PITCH__MASK … #define A4XX_TEX_CONST_2_PITCH__SHIFT … static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) { … } #define A4XX_TEX_CONST_2_SWAP__MASK … #define A4XX_TEX_CONST_2_SWAP__SHIFT … static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) { … } #define REG_A4XX_TEX_CONST_3 … #define A4XX_TEX_CONST_3_LAYERSZ__MASK … #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT … static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) { … } #define A4XX_TEX_CONST_3_DEPTH__MASK … #define A4XX_TEX_CONST_3_DEPTH__SHIFT … static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) { … } #define REG_A4XX_TEX_CONST_4 … #define A4XX_TEX_CONST_4_LAYERSZ__MASK … #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT … static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) { … } #define A4XX_TEX_CONST_4_BASE__MASK … #define A4XX_TEX_CONST_4_BASE__SHIFT … static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) { … } #define REG_A4XX_TEX_CONST_5 … #define REG_A4XX_TEX_CONST_6 … #define REG_A4XX_TEX_CONST_7 … #define REG_A4XX_SSBO_0_0 … #define A4XX_SSBO_0_0_BASE__MASK … #define A4XX_SSBO_0_0_BASE__SHIFT … static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) { … } #define REG_A4XX_SSBO_0_1 … #define A4XX_SSBO_0_1_PITCH__MASK … #define A4XX_SSBO_0_1_PITCH__SHIFT … static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) { … } #define REG_A4XX_SSBO_0_2 … #define A4XX_SSBO_0_2_ARRAY_PITCH__MASK … #define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT … static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) { … } #define REG_A4XX_SSBO_0_3 … #define A4XX_SSBO_0_3_CPP__MASK … #define A4XX_SSBO_0_3_CPP__SHIFT … static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val) { … } #define REG_A4XX_SSBO_1_0 … #define A4XX_SSBO_1_0_CPP__MASK … #define A4XX_SSBO_1_0_CPP__SHIFT … static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val) { … } #define A4XX_SSBO_1_0_FMT__MASK … #define A4XX_SSBO_1_0_FMT__SHIFT … static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val) { … } #define A4XX_SSBO_1_0_WIDTH__MASK … #define A4XX_SSBO_1_0_WIDTH__SHIFT … static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val) { … } #define REG_A4XX_SSBO_1_1 … #define A4XX_SSBO_1_1_HEIGHT__MASK … #define A4XX_SSBO_1_1_HEIGHT__SHIFT … static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val) { … } #define A4XX_SSBO_1_1_DEPTH__MASK … #define A4XX_SSBO_1_1_DEPTH__SHIFT … static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) { … } #ifdef __cplusplus #endif #endif /* A4XX_XML */
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